JP3013753U - TV signal tuning station - Google Patents

Abstract

(57) [Summary] (Correction) [Purpose] To provide a television signal tuning / tuning device capable of preset operation in a short time. [Configuration] Phase locked loop circuit 322 and tuner / IF
A television signal tuning / tuning device 10 having a section 321 and at least a tuning means for receiving and tuning a television broadcasting channel.
0, a memory 3 storing and storing a start center frequency data of a plurality of sync signal detection scans set for each television broadcast channel or a data table of the frequency division ratio thereof, and a tuner /
Sync detection means for detecting a sync signal from a television video signal obtained by detecting and amplifying the IF section signal output, and the phase lock loop circuit at the time of tuning, based on the data table stored in the memory, based on the frequency data or Phase synchronization is sequentially started for each frequency division ratio, and if the synchronization detection means detects a synchronization signal during each phase synchronization operation, the control means 31 for storing the channel and its tuning data is provided. Characterize.

Description

[Detailed description of the device]

[0001]

[Industrial applications]

 The present invention relates to a television signal tuning / tuning device, and more particularly to a television signal tuning / tuning device having a phase locked loop tuner unit in a receiver for receiving broadcast radio waves from a television or the like.

[0002]

[Prior art]

 2. Description of the Related Art Some receivers for receiving broadcast radio waves from a television or the like are equipped with a television signal tuning / tuning device having a phase locked loop tuner section (referred to as a PLL tuner section). FIG. 4 shows a block diagram of a receiver 30 provided with such a conventional television signal tuning and tuning apparatus. Further, FIG. 5 is an operation explanatory diagram of a conventional television signal tuning / tuning device. Here, 31 is a microcomputer (hereinafter, referred to as CPU) that is a control unit of the entire system, 32 is a PLL tuner unit that tunes to a selected reception channel, and 33 is a memory that stores the selected reception channel number and the like. Is. The PLL tuner section 32 includes a tuner / IF section 321 and a PLL circuit 322. The PLL circuit 322 includes a band switch 325, an oscillator 326 that outputs a reference oscillation frequency signal of 4 MHz, a phase comparator 327, a low pass filter 328, a prescaler 323, and a frequency divider 324. The tuner / IF unit 321 includes a tuner unit that receives a selected channel, a VCO 321a that functions as a part of the PLL circuit 322, and an intermediate frequency amplification unit 321b. Reference numeral 34 is an antenna for receiving television radio waves transmitted from a broadcasting station. Further, 37 is a video processing circuit, and 38 is a picture tube.

When the receiver 30 starts to use, first, in the memory 33, the presence or absence of a broadcasting station in each channel, and if the synchronization signal of the channel is detected, the center frequency or frequency division ratio thereof is detected. A preset such as writing is made. With this preset, empty channels with no broadcasting stations and center frequencies for tuning and tuning are stored in memory. Therefore, when the receiver 30 is used after presetting, the CPU 31, which is the system control unit, reads the center frequency of the corresponding channel from the memory 33 based on the channel selected by the user, and the PLL tuner unit 32. To the PLL circuit 322, and the center frequency can be used as the start frequency to start the phase synchronization.

The operation of the preset will be described below. In the preset work, it is necessary to automatically tune each channel in sequence to determine the presence or absence of broadcast waves and, if there are broadcast waves, the tuning frequency and store them in memory. FIG. 5 shows the process of this preset operation. In the same figure, normally, in the channel selection method in the preset operation, the CPU 31 reads the center frequency data (initial value) of the first channel from the memory 33, and the PLL tuner unit 32 operates based on this to read the center frequency data. One sampling 21 is performed. That is, the synchronization by the PLL circuit 322 at the center frequency is executed in about 300 milliseconds. If the synchronization is not established at this frequency, it is determined that the synchronization signal is not detected at this frequency, and the second sampling 22 is performed. When the synchronization is established at this frequency and the synchronization lock signal is detected, the operation 1 is entered.

In operation 1, the CPU 31, which is the system control unit, outputs data at 31.25 KHz in one step every 3 steps (waiting step 30 ms), and inputs the AFC signal from the PLL tuner section 32. Detect AFC changes. If there is no AFC change from the center frequency to ± 2.44 MHz, after an appropriate weight (for example, 30 ms), the process proceeds to the next second sampling 22. On the other hand, when the AFC change is detected within ± 2.44 MHz, the operation 2 is entered.

In operation 2, the CPU 31 outputs data every step (waiting time 60 ms between steps) after waiting 100 ms, and when the AFC change is detected within ± 2.44 MHz from the center frequency. , Updates the memory contents using the data of the relevant channel. On the other hand, if there is no AFC change within ± 2.44 MHz, after an appropriate wait (for example, 50 ms), the process proceeds to the next second sampling 22.

In the second sampling 22, the center frequency of 1. The synchronization by the PLL circuit 322 is executed from a frequency as low as 31 MHz. If the synchronization is not established at this frequency, it is determined that the synchronization signal is not detected at this frequency and the third sampling 23 is performed. When synchronization is established at this frequency and a synchronization lock signal is detected, the operation moves to operation 1 and the same operation as described above is repeated. Operations 1 and 2 are similar to the above.

In the third sampling 23, the center frequency 2. The synchronization by the PLL circuit 322 is executed from the frequency as low as 06 MHz. If the synchronization is not established at this frequency, it moves to the fourth sampling 24 as a non-detection of the synchronization signal at this frequency. When synchronization is established at this frequency and a synchronization lock signal is detected, the operation moves to operation 1 and the same operation as described above is repeated. The operation and the operation of the operation 2 are similar to the above.

If the synchronization is not established in the first to third sampling, the process proceeds to the fourth sampling 24. In the fourth sampling 24, the synchronization by the PLL circuit 322 is executed from the frequency 1.31 MHz higher than the center frequency in about 150 milliseconds. When the synchronization is established at this frequency and the synchronization lock signal is detected, the operation shifts to the operation 1 and the same operation as described above is repeated. The operations of the operation 1 and the operation 2 are similar to the above. If synchronization is not established at this frequency, synchronization is not established on this channel, and sampling for the next channel starts.

[0010]

[Problems to be solved by the device]

 As described above, in the conventional TV signal tuning / selecting device, the system control section uses the double operation of detecting the sync lock signal by the phase locked loop circuit and then detecting and confirming the sync lock by AFC detection. I was there. For this reason, there is a drawback in that tuning takes time and extra time is spent in the tuning operation during preset work.

The present invention has been made to solve the above-mentioned drawbacks of the prior art, and an object thereof is to provide a television signal tuning / tuning device capable of performing a preset operation in a short time without requiring a long time for tuning. To provide.

[0012]

[Means for Solving the Problems]

 In order to achieve the above object, a television signal tuning / tuning apparatus according to the present invention has a phase synchronization loop circuit and a tuner / IF section, and is a television equipped with at least tuning means for receiving and tuning a television broadcasting channel. In the signal tuning / tuning device, a memory storing and storing a start center frequency data of a plurality of sync signal detection scans set for each of the television broadcast channels or a data table of the frequency division ratio thereof and the tuner / IF section signal output are stored. Detection and detection of the sync signal from the amplified TV video signal, and the phase lock loop circuit at the time of channel selection, based on the data table stored in the memory, based on the frequency data or its frequency division. Phase synchronization is started sequentially for each ratio, and if the synchronization detection means detects a tuning signal during each phase synchronization operation, the channel and its tuning data are detected. Characterized in that a control means for 憶.

Further, the plurality of start center frequency data set for each of the channels or the division ratio thereof is composed of four data including the center frequency of the channel. The four starting center frequency data or the frequency division ratios thereof are respectively the center frequency of the channel, the frequency lower by 1.31 Mhz from the center frequency, the frequency lower by 2.06 Mhz from the center frequency, and the center. It is characterized by being composed of four frequencies higher by 1.31 Mh z from the frequency.

[0014]

[Action]

 In the television signal tuning / tuning apparatus according to the present invention, the control means controls the phase-locked loop circuit based on a plurality of center frequency data for each channel stored in the memory or each frequency division ratio thereof. If a plurality of times of phase synchronization are sequentially started and the synchronization detecting means detects the synchronization by any one of the plurality of times of phase synchronization, the presence or absence of the channel in the memory and its synchronization are immediately performed without performing the AFC detection. Update the data. This significantly reduces the time required for preset operation for each channel.

[0015]

【Example】

 An embodiment of the present invention will be described below with reference to the accompanying drawings. FIG. 1 is a block diagram of an embodiment of a television signal tuning / tuning device according to the present invention. FIG. 2 is a process explanatory diagram of a preset operation of the television signal tuning / tuning device according to the present invention. FIG. 3 is an explanatory diagram of data stored in the memory of the television signal tuning / tuning device according to the present invention. In FIG. 1, the same functions as those of FIG. The receiver 100 equipped with the television signal tuning / selecting device according to the present invention shown in FIG. 1 comprises, as its main parts, a CPU 1 and a PLL tuner 2, a memory 3, and a video processing circuit 37 for system control of the entire device. To be done. Here, the CPU 1 detects a video sync signal from the video processing circuit 37, a sync detection port 1a, an AFC detection port 1b that detects an AFC signal from the output port 2b of the PLL tuner unit 2, and a PLL tuner unit 2 and data. , A data input / output port 1c for inputting / outputting data, an input port 2d, 2e of the PLL tuner unit 2, an enable signal for output data, an output port 1d, 1e for outputting a clock signal, a selected reception channel number, and It is provided with an input / output port 1f with the memory 3 for storing data of the frequency (or frequency division ratio).

At the time of shipment of the receiver 100, as shown in FIG. 3, the memory 3 has a channel number 3a existing in each channel, a center frequency or a frequency division ratio 3b of the channel, and a second number described later. The fourth sampling frequencies 3c to 3e are stored as initial values. When the receiver 100 first starts using, the preset value is updated by updating the initial value of the memory 3. With this preset, no number is recorded on an empty channel without a broadcasting station, and that number is recorded on a channel with a broadcast signal, and the frequency when tuning in the preset operation is updated as the center frequency 3b and the initial value is updated. To be done. Therefore, when the receiver 100 after presetting is used, the CPU 1 reads the center frequency of the corresponding channel from the memory 3 to the PLL tuner section 2 based on the channel selected by the user from the key input section. Given this center frequency, the phase synchronization can be started with the starting frequency.

The preset operation will be described below with reference to FIG. Also in the preset work, it is necessary to tune each channel in sequence and determine the presence or absence of a broadcast signal and, if there is a broadcast signal, the tuning frequency and store it in memory. FIG. 2 shows the process of this preset operation. In the figure, the tuning method in the preset operation is that the center frequency data (initial value) of the first channel is first read out, and the PLL circuit 322 of the PLL tuner unit 2 operates based on this, and the first sampling 10 Do. That is, the synchronization at the center frequency is executed in about 200 milliseconds. When the synchronization is established at this frequency and the synchronization signal input from the video processing circuit 37 to the synchronization detection port 1a of the CPU 1 is detected, the channel number 3a and the frequency at the time of synchronization are set as the center frequency 3b in the memory 3 immediately. Record the update. Therefore, the second to fourth sampling frequencies are also updated. If the synchronization is not established at this frequency, the synchronization signal is not detected at this frequency and the second sampling 11 is started. In detail, the synchronization detection in 200 milliseconds in the first sampling is performed by dividing into 20 times for 10 milliseconds. In this case, the CPU 1 repeats 10 milliseconds 20 times until the synchronization detection is detected by turning on / off the enable signal at a predetermined clock for the PLL circuit 322 with a predetermined clock. These signals are sent from the output ports 1c, 1d, 1e of the CPU 1 to the PLL tuner unit 2 and the input ports 2c, 2d, 2e. The synchronization detection in 100 milliseconds in the second, third, and fourth samplings described later repeats 10 milliseconds for 10 times. In addition, a wait time is provided between each time.

In the second sampling 11, the CPU 1 executes synchronization by the PLL circuit 322 from a frequency 1.31 MHz lower than the center frequency read from the memory 3 in about 100 milliseconds. When synchronization is established at this frequency and a synchronization signal is detected, the CPU 1 immediately updates and records in the memory 3 the channel number 3a and the frequency at the time of tuning as the central frequency 3b. Therefore, the second to fourth sampling frequencies are also updated. If the synchronization is not established at this frequency, the synchronization signal is not detected at this frequency and the third sampling 23 is performed.

In the third sampling 12, the center frequency 2. The synchronization by the PLL circuit 322 is executed from the frequency as low as 06 MHz. When the synchronization is established at this frequency and the synchronization signal is detected, the CPU 1 immediately updates and records the channel number 3a and the frequency at the time of tuning as the center frequency 3b in the memory 3. Therefore, the second to fourth sampling frequencies are also updated. If the synchronization is not established at this frequency, the synchronization signal is not detected at this frequency and the process proceeds to the fourth sampling 13.

If the synchronization is not established in the first to third samplings, the process proceeds to the fourth sampling 13 and 1.31MHz higher than the central frequency read from the memory 3 by the CPU 1 in about 100 milliseconds. The PLL circuit 322 executes synchronization from the frequency. When the synchronization is established at this frequency and the synchronization signal is detected, the CPU 1 immediately updates the memory 3 with the channel number 3a and the frequency at the time of synchronization as the center frequency 3b. Therefore, the second to fourth sampling frequencies are also updated. If the synchronization is not established at this frequency, the synchronization is not established on this channel, the channel number 3a is updated to blank, and the sampling of the next channel is started. As described above, the television signal tuning / selecting device of the present invention can immediately update the memory 3 and start the operation of updating the next channel when the phase locked loop formation in the PLL circuit 322 is detected. The double action of detecting and confirming the synchronization lock by the AFC detecting means is not necessary. As a result, the tuning time can be shortened and the preset operation can be completed quickly.

Although the memory update in the preset at the start of use of the receiver 100 is described above, the memory may be automatically updated as needed during the subsequent use.

[0022]

[Effect of device]

 As described above, the television signal tuning / tuning device according to the present invention is provided with a memory for storing the sync signal detection scanning start frequency data for each channel or its frequency division ratio, and a control means for preset operation for each channel. Starts the detection scan for each channel stored in the memory with respect to the phase locked loop circuit, and sequentially starts phase synchronization for each channel based on each of the center frequency data or its frequency division ratio, If there is synchronization detection by the synchronization detection means for detecting synchronization in the video processing circuit, the channel number and its tuning data are immediately updated in the memory without performing AFC detection, so the time required for the preset operation for each channel can be reduced. It will be possible to shorten it significantly. In addition, even if the usage area changes, the memory is rewritten immediately in real time according to the reception status of the selected station in a detailed area, so the usability is significantly improved.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of a television signal tuning / tuning device according to the present invention.

FIG. 2 is a process explanatory diagram of a preset operation of the television signal tuning / tuning device according to the present invention.

FIG. 3 is an explanatory diagram of data stored in a memory of the television signal tuning / tuning device according to the present invention.

FIG. 4 is a block configuration diagram of a conventional television signal tuning station.

FIG. 5 is a process explanatory diagram of a preset operation in the conventional television signal tuning / selecting device.

[Explanation of symbols]

1 CPU (system control unit) 1a Sync detection port 1c Data input / output port 1d Enable output port 1e Clock output port 2 Phase locked loop tuner unit (PLL tuner unit) 3 Memory 322 PLL circuit 321 Tuner / IF unit 34 TV antenna 37 Video Processing circuit 100 Receiver equipped with the television signal tuning and tuning device of the present invention

Claims (3)

[Scope of utility model registration request] 1. A television signal tuning / tuning apparatus having a phase-locked loop circuit and a tuner / IF section, and at least a tuning means for receiving and tuning a television broadcasting channel, wherein each television broadcasting channel is set. A memory that stores and stores a data table of start center frequency data of a plurality of sync signal detection scans or a frequency division ratio thereof, and a sync detection unit that detects a sync signal from a television video signal that detects and amplifies the tuner / IF section signal output. When the channel is selected, the phase-locked loop circuit is caused to sequentially start phase-locking for each of the frequency data or each division ratio thereof based on the data table stored in the memory, and during each phase-locking operation. If the synchronization detecting means detects a synchronization signal, the television signal is provided with a control means for storing the channel and its tuning data. Tuning station equipment. 2. The television signal tuning selection according to claim 1, wherein a plurality of start center frequency data set for each of said channels or a frequency division ratio thereof comprises four data including a center frequency of said channel. Station equipment. 3. The four starting center frequency data or frequency division ratios thereof are respectively a center frequency of the channel, a frequency lower than the center frequency by 1.31 Mhz, and a frequency lower than the center frequency by 2.06 Mhz. 3. The television signal tuning / tuning device according to claim 1, comprising four frequencies which are higher by 1.31 Mhz from the center frequency.