JP3013458B2 - Semiconductor storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device,
In particular, the present invention relates to the shape and arrangement of charge storage electrodes of a charge storage capacitor in a DRAM having a memory cell including one transistor and one stacked type charge storage capacitor.

[0002]

2. Description of the Related Art A DRAM stores information as charges in a charge storage capacitor. From the viewpoint of the stable operation of the DRAM and the storage time, it is desirable that the capacitance of the charge storage capacitor be as large as possible. On the other hand, DR
In order to highly integrate the AM, the memory cell is downsized. Along with this, the plane projection area allowed for the charge storage capacitor also becomes smaller. The plane projection area is smaller than the cell size of the memory cell. To resolve this contradiction,
The structure of a charge storage capacitor in a DRAM having one transistor and one charge storage capacitor is as follows:
The trench type has been adopted from the planar type, and the stacked type has been adopted. In the trench type charge storage capacitor, the area of the side surface of the charge storage capacitor is increased by increasing the depth of the trench, and the capacitance of the charge storage capacitor is increased. On the other hand, in the case of a stacked type charge storage capacitor, the height of the charge storage electrode of the stacked type charge storage capacitor increases, so that the area of the side surface of the charge storage capacitor increases, and the capacitance of the charge storage capacitor increases. Has become.
In the latest stacked type charge storage capacitor, the capacity is further increased by adopting a charge storage electrode having a fin structure (it was impossible to use the trench type). If a specific structure such as a fin structure is neglected, the capacitance of the charge storage capacitor is determined by the surface area of the top and side surfaces of the charge storage electrode.

The densest example of a recent stacked type DRAM is described in IEDM Technical Digest, 1988, pp. 596-599 (IEDM Tech. Digest pp 596-5).
99, 1988). This report will be described with reference to FIGS. FIG. 20 is a schematic plan view, and FIG. 21 is a schematic sectional view taken along the line AB in FIG. In this report, the dimensions, shape, and arrangement of transistors, active regions, bit lines, word lines, bit contact holes, and node contact holes are shown, but the dimensions of the charge storage electrodes of a stacked type charge storage capacitor are shown. , Shape and arrangement are not specified.

On the surface of a P-type silicon substrate 112, bit lines 105a, 105b, 105c, 105d and word lines 104a, 104b, 104c, 104d are formed.
Word lines 104a, 104 having a direction parallel to the X axis
b, 104c, 104d, and bit lines 105a, 105b, 10 having a direction orthogonal to the X axis and parallel to the Y axis.
5c and 105d form a matrix shape. In such a DRAM, an area occupied by one memory cell is, for example, the memory cell 101. In this case, the cell size is twice the word line pitch width P _W (word line width + word line interval) and the bit line pitch width P _B (bit line width + bit line interval). Product 2P _W
- the P _B.

[0005] An active region is formed on the surface of the P-type silicon substrate 112. A thin insulating film 113 is formed on the surface of the silicon substrate 112 where the active region exists, and a thick insulating film 113 is formed on the surface of the silicon substrate 112 where the active region does not exist. The surfaces of the word lines and the bit lines are covered with an insulating film 113.

For example, the active region 109bbc includes a region surrounded by a bit line 105a, a bit line 105b, a word line 104c and a word line 104d,
b bit line 105c, word line 104a, and word line 10
4b, and a region connecting between the regions. The active region 109bbc is provided with an N ⁺ type diffusion region which is self-aligned with the word line 104b and the word line 104c. Active area 109
The N ⁺ type diffusion region of bbc surrounded by the bit line 105a, the bit line 105b, the word line 104c, and the word line 104d becomes the (b, c) bit node diffusion region 107bc. Further, N ⁺ between word line 104b and word line 104c in active region 109bbc is used.
The diffusion region of the type is a bit diffusion region 106bbc for (b, b) bits and (b, c) bits. In addition, bit line 105b bit line 1 in active region 109bbc
The N ⁺ type diffusion region surrounded by the region 05c, the word line 104a, and the word line 104b becomes a node diffusion region 107bb for (b, b) bits.

[0007] From the node diffusion region 107bc, bit diffusion region 106bbc, and word line 104c, (b,
c) A bit transistor is formed. Similarly, node diffusion region 107bb and bit diffusion region 106
The bbc and the word line 104b constitute a transistor for (b, b) bits. Active area 109
dbc is (d, c) like the active region 109 bbc.
This is a diffusion region for transistors for the bit and for the (d, b) bit.

The bit diffusion region 106bbc has a bit contact hole 108bbc connected to the bit line 105b.
Is provided. Similarly, a bit contact hole 108dbc connected to the bit line 105d is provided in the bit diffusion region in the active region 109dbc. The node diffusion regions 107bc and 107bb have (b,
Node contact holes 102bc, 102bb connected to the charge storage electrodes 103bc, 103bb of the capacitor for storing the (c), (b, b) bit charges are provided. Similarly, in the node diffusion region of the active region 109dbc, node contact holes 102db and 102dc connected to the charge storage electrodes 103db and 103dc of the (d, b) and (d, c) bit charge storage capacitors are provided. I have. Charge storage electrodes 103aa, 103ca, 103
cd and 103ed are also connected to the respective node diffusion regions via the respective node contact holes.

The above-mentioned report does not specify the shape of the charge storage electrode. The discussion will proceed assuming the shape shown in the figure by inference from a conventional DRAM.
The projection shape of the upper surface of the charge storage electrode of these charge storage capacitors onto the silicon substrate surface is rectangular, with the long side parallel to the bit line (Y axis) and the short side parallel to the word line (X axis).
Is parallel to

The capacitance of a charge storage capacitor in a stacked DRAM is constituted by a charge storage electrode, a cell plate electrode 111, and a capacitance insulating film 110 interposed therebetween. Further, the capacitance value of the charge storage capacitor is determined by the dielectric constant and the film thickness of the capacitance insulating film 110 and the facing area of the two electrodes. Once the capacitance insulating film to be used and its film thickness are determined, the increase in the capacitance value of this capacitor depends on how large the facing area of these two electrodes is. This facing area is equal to the surface area of the charge storage electrode.

[0011]

The surface area A _T0 of the charge storage electrode is the sum of the area A _t0 of the upper surface of the charge storage electrode and the area A _{s0 of the} side surface. Although the upper surface is strictly a curved surface, the projected area of the upper surface on the silicon substrate surface is smaller than the cell size 2P _W × P _B. When the minimum processing dimension F in the lithography technology for producing this DRAM is adopted as the distance between two charge storage electrodes, the value of A _T0 becomes maximum. At this time, the projected area A _t0 of the upper surface onto the silicon substrate surface is (2P _W −F) × (P _B −F).
In this case, the projected shape of the upper surface onto the silicon substrate surface is a rectangle having a long side parallel to the bit line. Also,
The perimeter L _{P0 of the} rectangle is 2 × (2P _W + P _B -2F). If the film thickness (height) of the charge storage electrode is d, the area A _s0 of the side surface is 2 × (2P _W + P _B −2F) × d. In order to make the following discussion clear, P _W = P _B
= P. Thus, cell size of the DRAM shown is the 2P ^2. In such a case, _At0 = (2P-F) x
(P−F), L _P0 = 2 × (3P−2F), _{As 0} = 2 ×
(3P-2F) × d.

In the conventional method of increasing the surface area A _T0 of the charge storage electrode, generally, a method of decreasing F and particularly increasing d is common. In order to further increase the thickness, irregularities are formed on the upper and side surfaces. However, the methods for increasing the surface area A _TO of these charge storage electrodes all depend on the manufacturing method. In other words, as long as the conventional shape and arrangement method of the charge storage electrode is adopted, the increase in the surface area A _T0 is restricted by the manufacturing technology of the era. In other words, increasing the perimeter of the charge storage electrode and increasing the surface area A _T0 of the charge storage electrode without depending on the manufacturing technology,
Can not.

[0013]

A first aspect of the semiconductor memory device of the present invention comprises one transistor and one charge storage capacitor formed on the surface of a silicon substrate.
In a DRAM having a word line having a direction parallel to the X axis and a bit line having a direction perpendicular to the X axis and parallel to the Y axis on the surface of the silicon substrate, 1/1 / the minimum processing size
It has a charge storage electrode of a charge storage capacitor having a thickness (height) greater than 2 and has a rectangular shape projected onto the surface of the silicon substrate and has a long side not parallel to the X-axis and the Y-axis. It has a charge storage electrode.

The long side of the shape of the charge storage electrode projected onto the silicon substrate is preferably the i-th bit line, the i + 1-th bit line.
Bit line, j-th word line, and j + 2
One of the diagonals of the rectangle formed by the word line
Or it is parallel to the other.

Alternatively, the long side of the shape of the charge storage electrode projected onto the silicon substrate is preferably the i-th bit line, the (i + 1) -th bit line, the j-th word line, and the (j + 4) -th word. It is parallel to one or the other of the diagonal lines of the rectangle formed by the lines.

Alternatively, the long side of the shape of the charge storage electrode projected onto the silicon substrate is preferably the i-th bit line, the (i + 2) -th bit line, the j-th word line, and the (j + 2) -th word. It is parallel to one or the other of the diagonal lines of the rectangle formed by the lines.

Alternatively, the long side of the shape of the charge storage electrode projected onto the silicon substrate is preferably the i-th bit line, the (i + 3) -th bit line, the j-th word line, and the (j + 2) -th word. It is parallel to one or the other of the diagonal lines of the rectangle formed by the lines.

Alternatively, the long side of the shape of the charge storage electrode projected onto the silicon substrate is preferably the i-th bit line, the (i + 3) -th bit line, the j-th word line, and the (j + 4) -th word. It is parallel to one or the other of the diagonal lines of the rectangle formed by the lines.

[0019]

[0020]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Prior to the description of the embodiments, the configuration of the first embodiment of the semiconductor memory device of the present invention will be described with reference to FIGS. Prior to the discussion, a second hypothesis is established. The upper surface is assumed to be substantially parallel to the surface of the silicon substrate. Even if the conventional upper surface is constituted by a curved surface, the upper surface in the present invention can be constituted by the same curved surface as the conventional one. In recent DRAM memory cells, the surface area A _T0
Depends more on the side surface area _As0 than on the upper surface area _At0 . From these, this hypothesis was established.

Word lines parallel to the X axis, bit lines parallel to the Y axis
Parallel, the pitch width of the word lines and bit lines is P
Therefore, as shown in FIG. 1, the node contact hole is
A lattice point (m, 2n) is formed with P as a unit. The rectangle
The long side of the charge storage electrode to be formed is a grid from the grid point (0,0).
The case where they are arranged parallel to the direction to the point (m, 2n)
Think. Here, m and n are relatively prime integers. this
In this case, the pitch widths of the long side and the short side of the charge storage electrode are represented by L and S.
I do. At this time, L = [(mP)^Two+ (2nP)^Two]^1/2... (1) and the size of one cell is 2P^TwoS = 2P^Two/ L (2) Width of charge storage electrode (length of short side), charge storage
The minimum gap between both poles is the minimum processing dimension (minimum processing dimension)
Since F cannot be smaller than F, F ≦ S / 2 = P^Two/ [(MP)^Two+ (2nP)^Two]^1/2... (3) On the other hand, the circumference L of the charge storage electrode_PIs L_P= 2 (L + S-2F) = 2 ｛P [(m^Two+ 4n^Two+2) / (m^Two+ 4n^Two)^1/2] −2F｝ (4) From grid point (0,0) to grid point (m, 2n)
The surface area of the charge storage electrode arranged in parallel to the
_TAssuming that (m, 2n), the surface area of the conventional charge storage electrode
A_T0Is A_T0= A_T(0,2) = A_t0+ A_s0  = (P−F) (S−F) +2 (3P−2F) d (5) On the other hand, A_T(M, 2n) is A_T(M, 2n) = (LF) (SF) +2 (L + S-2F) d (6) A_T0= A_T(0,2) <A_TIf (m, 2n) (7), the present invention is effective. Substituting Equations (5) and (6) into Equation (7) and arranging d
By doing so, d ≧ F / 2 (8) is obtained.

Here, for example, P = 1.0 μm, F = 0.
In the case of 2 μm, the lattice points satisfying the expression (3) are (1,
2), (1,4), (2,2), (3,2), (3,
4) and the conventional (0, 2). FIG. 2 shows the surface area of a conventional charge storage electrode having a rectangular shape having a direction defined by lattice points (1, 4) and (3, 2) with the thickness d of the charge storage electrode as a variable. It is a graph which compared and showed _AT (m, 2n).

Next, for some lattice points, the P of F
And the relationship between F and L _P. When (m, 2n) = (1, 2), F ≦ P / 5 ^1/2 , L _P = 2 [(7P / 5 ^1/2 ) −2F]
Becomes When (m, 2n) = (2, 2), F ≦ P / 8 ^1/2 , L _P = 2 [(10P / 8 ^1/2 ) −2
F]. When (m, 2n) = (3, 2), F ≦ P / 13 ^1/2 , L _P = 2 [(15P / 13 ^1/2 ) −
2F]. When (m, 2n) = (1, 4), F ≦ P / 17 ^1/2 , L _P = 2 [(19P / 17 ^1/2 ) −
2F]. In the case of (m, 2n) = (3, 2), F ≦ P / 5, L _P = 2 [(27P / 5) −2F]. When (m, 2n) = (1, 6), F ≦ P / 37 ^1/2 , L _P = 2 [(39P / 37 ^1/2 ) −
2F]. When (m, 2n) = (2, 6), F ≦ P / 40 ^1/2 , L _P = 2 [(42P / 40 ^1/2 ) −
2F]. FIG. 3 is a graph showing these results collectively. In the figure, the range shown by the solid line is the first range of the present invention.
Is an effective range of the embodiment.

The relationship between P and F is not independent. F
Is smaller, P is also linked to it and becomes smaller due to the demand for high-density elements. That is, a smaller cell size can be realized. Experience shows that F is 1/5 of P
Has been changing to about 1/4. This leaves a question about the realization of the lattice points (1, 6) and (2, 6).

The above results are summarized as follows. The long side of the rectangle formed by projecting the charge storage electrode onto the silicon substrate surface according to the first aspect of the semiconductor memory device of the present invention is the long side of the rectangle formed by projecting the conventional charge storage electrode onto the silicon substrate surface. It is longer than. Further, if the thickness of the charge storage electrode of the charge storage capacitor is larger than １ ／ of the minimum processing dimension, the increase in the area of the side surface of the charge storage electrode according to the first embodiment of the semiconductor memory device of the present invention is as follows.
More than this reduction in the area of the upper surface. For this reason, the surface area of the charge storage electrode according to the first aspect of the semiconductor memory device of the present invention is larger than the surface area of the conventional charge storage electrode. As a result, a charge storage capacitor having a larger capacitance value than before can be obtained without newly adding a manufacturing method.

Next, a first embodiment of the present invention will be described with reference to FIG.
This will be described with reference to FIG. 4 and 5 are schematic plan views for explaining the present embodiment. 6 to 10 are schematic sectional views in the order of steps for explaining the method of manufacturing the DRAM according to the present embodiment, and are schematic sectional views taken along the broken line AB in FIGS. FIGS. 11 to 13 are schematic cross-sectional views in the order of steps for explaining another method of manufacturing the semiconductor memory device according to the present embodiment, and are schematic cross-sectional views along the broken line AB in FIGS. . The charge storage electrode in this embodiment has a rectangular shape. The long sides are arranged in parallel to the line connecting the lattice point (0, 0) and the lattice point (1, 4) described in FIGS.

First, referring to FIG. 4 and FIG.
The configuration of the RAM will be described. FIG. 4 shows a word line 204, a bit line 205, an active region 209, a node contact hole 2
2 shows a positional relationship between the bit contact hole 02 and the bit contact hole 208. FIG. 5 shows the word line 204 and the bit line 20.
5, the node contact hole 202 and the charge storage electrode 2
3 shows the positional relationship between the two.

The bit line 20 is formed on the surface of the P-type silicon substrate.
5a, 205b, 205c, 205d, word line 204
a, 204b, 204c, 204d, 204e, 204
f is formed, and the word line 20 has a direction parallel to the X axis.
4a, 204b, 204c, 204d, 204e, 20
4f and bit lines 205a, 205b, 205c, 205d having a direction orthogonal to the X axis and parallel to the Y axis form a matrix. In such a DRAM, the area occupied by one memory cell is, for example, the memory cell 201. In this case, the cell size is a product 2P of twice the word line pitch width P (word line width + word line interval) and the bit line pitch width P (bit line width + bit line interval). It becomes ² .

An active region 209 is formed on the surface of the P-type silicon substrate.
aab, 209aef, 209bcd, 209bgh,
209cab, 209cef, 209dcd, 209d
gh etc. are formed. For example, the active region 209bc
d is the word lines 204d and 204e and the bit line 20
5a, 205b, word line 204
b, 204c and a region surrounded by the bit lines 205b, 205c, and a region connecting these two regions.

An N ⁺ type diffusion region is formed in a region other than immediately below the word line 204 in the active region 209.
For example, the N ⁺ type diffusion regions formed in the region between two adjacent word lines 204 d and 204 e in the active region 209 bcd and in the region between two adjacent word lines 204 b and 204 c are each a node diffusion region. Area. The bit line 20 in the active region 209bcd
The N ⁺ type diffusion region formed just below 5b becomes a bit diffusion region. By this bit diffusion region, these node diffusion regions, and word lines 204c and 204d, (b,
Transistors for c) bits and (b, d) bits are configured.

On the surface of the bit diffusion region where the active region 209 and the bit line 205 intersect, a bit contact hole 208 for connecting the bit line 205 is provided. For example, the bit line 205c and the active region 209c
Bit contact holes 208cab and 208cef are provided on the surface of the bit diffusion region that intersects ab and 209cef. Similarly, active regions 209aab, 20
9aef, 209dcd, etc.
08aab, 208aef, 208dcd, etc. are provided.

A node contact hole 202 for connecting the active region 209 to the charge storage electrode 203 is formed on the surface of the node diffusion region. For example,
Word lines 204d, 20 in active region 209bcd
A node contact hole 202bd is provided on the surface of the node diffusion region sandwiched by 4e, and a node contact hole 202bc is provided on the surface of the node diffusion region between the word lines 204b and 204c in the active region 209bcd. Similarly, a node contact hole 202ab and the like are provided in the active region 209aab, and the active region 209caab is provided.
b is provided with a node contact hole 202cb and the like, and the active region 209dcd is provided with a node contact hole 202cb.
c, 202dd are provided, the active region 209cef is provided with node contact holes 202ce, 202cf, and the active region 209aef is provided with the node contact hole 20ce.
2af and the like are provided, and a node contact hole 202bg and the like are provided in the active region 209bgh.
The dgf is provided with a node contact hole 202dg and the like.

For example, the charge storage electrode 2 connected to the node diffusion region via a node contact hole 202ce provided in the node diffusion region of the active region 209cef.
03ce is a charge storage electrode for the (c, e) bit. Similarly, node contact holes 202ab, 202b
c, 202ee, 202bg, charge storage electrode 203 connected to each node diffusion region through 202cf, etc.
ab, 203bc, 203ee, 203bg, 203c
f etc. are provided.

In this embodiment, P = 1.0 μm, F = P
/5=0.2 μm, d = 0.5 μm
If AM is formed, the length of the long side of the charge storage electrode 203
The length is 3.8 μm and the length of the short side is 0.275 μm.
Thereby, the surface of the upper surface of the charge storage electrode 203 of the present embodiment
Product A_t1Is A_t1= 3.8 µm x 0.275 µm = 1.045 µm^Two  Becomes Area A of the side of this_s1Is A_s1= 2 × (3.8 μm + 0.275 μm) × 0.5 μ
m^Two= 4.075 μm^TwoBecomes Therefore, its surface area
A_T1Is A_T1= A_t1+ A_s1= 5.12 μm^Two  Becomes On the other hand, the DRAM shown in FIGS.
If it is formed under the condition, the length of the long side and the short side is
1.8 μm and 0.8 μm. In this case, the charge storage
Area A of top surface of pole 103 (see FIG. 20)_t0, And sides
Area A of_s0Is A_t0= 1.8 μm × 0.8 μm = 1.44 μm^Two, A_s0= 2 × (1.8 μm + 0.8 μm) × 0.5 μm^Two
= 2.6 μm^Two  Becomes Thus, the surface area A of the charge storage electrode 103
_T0Is A_T0= A_t0+ A_s0= 4.04 μm^Two Becomes Thus, in the present embodiment, about 25% of the
The charge storage electrode 203 having a large area can be obtained.

Next, a method of manufacturing the first DRAM according to this embodiment will be described with reference to FIGS. FIG.
FIG. 10 is a schematic cross-sectional view in the order of processes along the broken line AB in FIGS. 4 and 5. In the description of the manufacturing method according to the present embodiment, the gate insulating film, the field oxide film, the interlayer insulating film, and the like are not important constituent elements.
Expressed as 3.

First, as shown in FIG. 6, an active region 209cef (see FIG. 4) and an insulating film 213 are formed on the surface of the P-type silicon substrate 212. The insulating film 213 where the active region is formed is thin, and the insulating film 213 where the active region is not formed is thick. Next, a word line 204 having a width of 0.8 μm and made of, for example, an N ⁺ type polycrystalline silicon film is used.
d, 204e and 204f are formed. Subsequently, word lines 204d and 204e are implanted by ion implantation of N-type impurities.
For example, three N ⁺ -type diffusion regions that are self-aligned are formed in the active region 209cef. Word lines 204e, 204
The central N ⁺ -type diffusion region sandwiched by f becomes a bit diffusion region 206cef, and the two N ⁺ -type diffusion regions at both ends become node diffusion regions 207ce and 207cf. The word line 204e, the bit diffusion region 206cef, and the node diffusion region 207ce form a transistor for (c, e) bits. Similarly, word lines 204f,
Bit diffusion area 206cef and node diffusion area 2
07cf forms a transistor for the (c, f) bit.

Next, as shown in FIG.
After d, 204e, 204f and the like are covered with the insulating film 213, the insulating film 213 on the surface of the bit diffusion region 206cef is removed by etching, and the bit contact hole 208ce is formed.
f is provided. Next, a bit line 205c having a width of about 1 μm made of a tungsten silicide film is provided.
The bit line 205c is connected to the bit contact hole 208cef.
Is connected to the bit diffusion region 206cef.

Next, as shown in FIG.
After c and the like are covered with the insulating film 213, the node diffusion region 20
The insulating films 213 on the surfaces of the 7ce and 207cf are removed by etching, and the node contact holes 202ce and 202cf are removed.
Is provided.

Next, as shown in FIG.
A 5 μm polycrystalline silicon film is deposited, phosphorus ions are implanted, and this is patterned to form a charge storage electrode 2.
03ce, 203cf, etc. are formed. These charge storage electrodes 203ce and 203cf are (c, e) bits,
It becomes a charge storage electrode for (c, f) bits.

Next, as shown in FIG.
After the formation of 10, the cell plate electrode 211 is formed. The charge storage electrode 203ce, the capacitor insulating film 210, and the cell plate electrode 211 constitute a stacked capacitor for (c, e) bits. Similarly, the charge storage electrode 203cf, the capacitor insulating film 210, and the cell plate electrode 211 constitute a stacked capacitor for (f, e) bits. Thus, the manufacture of the basic structure of the DRAM of this embodiment is completed. Subsequent steps are the same as those of a normal DRAM manufacturing method.

Next, another second method of manufacturing the DRAM according to this embodiment will be described with reference to FIGS.
11 to 13 are schematic cross-sectional views in the order of the processes along the broken line AB in FIGS. 4 and 5. This manufacturing method is similar to the first manufacturing method described above until the step shown in FIG.
Is the same as the manufacturing method.

After an active region and an insulating film 213 are formed on the surface of the P-type silicon substrate 212, a word line 204, a bit diffusion region 206, and a node diffusion region 207 are formed. A bit contact hole 208 is provided in the insulating film 213 on the surface of the bit diffusion region 206, and a bit line 205 connected to the bit diffusion region 206 is formed through this.
Thereafter, as shown in FIG.
After the film is deposited on the entire surface, a heat treatment is performed in a nitrogen atmosphere at 850 ° C. to form a reflowed BPSG film 214.

Next, as shown in FIG. 12, the BPSG film 214 and the insulating film 213 on the surface of the node diffusion region 207 are sequentially etched away to form a node contact hole 202. Next, a silicon oxide film having a thickness of about 0.1 μm is deposited on the entire surface. Subsequently, etch back by anisotropic etching is performed to form a spacer 215 made of a silicon oxide film on the side wall of the node contact hole 202.

Next, as shown in FIG.
m of polycrystalline silicon film is deposited on the entire surface. After phosphorus is ion-implanted into this, a charge storage electrode 203 is formed by a usual lithography technique and etching technique.
Subsequent steps are the same as in the first manufacturing method.

The second manufacturing method is different from the first manufacturing method described above.
The advantages of the manufacturing method of the present invention are as follows. Since the underlayer of the charge storage electrode is completely flattened, the patterning thereof is easy. In the first manufacturing method, in particular, the patterning of the charge storage electrode is performed obliquely on the uneven surface formed by the bit line, so that the influence of multiple reflection cannot be ignored in lithography.

Next, a second embodiment of the present invention will be described with reference to FIGS. The difference between this embodiment and the first embodiment lies in the shape of the active region. The charge storage electrode in this embodiment has a rectangular shape. Its long side is
If the expression method described with reference to FIG. 3 is used, they are arranged in parallel to a line connecting the grid point (0, 0) and the grid point (-1, 4).

FIG. 14 shows word lines 304 and bit lines 30.
5, a positional relationship among the active region 309, the node contact hole 302, and the bit contact hole 308 is shown. FIG. 15 shows a positional relationship among the word line 304, the bit line 305, the node contact hole 302, and the charge storage electrode 303.

The bit line 30 is formed on the surface of the P-type silicon substrate.
5a, 305b, 305c, 305d, word line 304
a, 304b, 304c, 304d, 304e, 304
f formed and having a direction parallel to the X-axis.
4a, 304b, 304c, 304d, 304e, 30
4f and bit lines 305a, 305b, 305c, 305d having a direction orthogonal to the X axis and parallel to the Y axis form a matrix. In such a DRAM, an area occupied by one memory cell is, for example, a memory cell 301. In this case, the cell size is twice the word line pitch width P = 1.0 μm (word line width + word line interval) and the bit line pitch width P = 2 μm.
The product of 1.0 μm (bit line width + bit line interval) is 2.0 μm ² .

An active region 309 is formed on the surface of the P-type silicon substrate.
aab, 309aef, 309bcd, 309bgh,
309cab, 309cef, 309dcd, 309d
gh etc. are formed. For example, the active region 309bc
d denotes the word lines 304a and 304e and the bit lines 30
5a, 305b, and word line 3
It is formed in a region immediately below the bit line 305b sandwiched between 04b and 304c.

An N ⁺ -type diffusion region is formed in a region other than immediately below word line 304 in active region 309.
For example, the N ⁺ -type diffusion regions formed in the region between two adjacent word lines 304d and 304e and in the region between two adjacent word lines 304b and 304c in the active region 309bcd are each a node diffusion region. Area. The bit line 30 in the active region 309bcd
The N ⁺ type diffusion region formed just below 5b becomes a bit diffusion region. By this bit diffusion region, these node diffusion regions and word lines 304c and 304d, (b,
Transistors for c) bits and (b, d) bits are configured.

A bit contact hole 308 for connecting the bit line 305 is provided on the surface of the bit diffusion region where the active region 309 and the bit line 305 intersect. For example, the bit line 305c and the active region 309c
The bit contact holes 308cab and 308cef are provided on the surface of the bit diffusion region that intersects the ab and 309cef. Similarly, active regions 309aab, 30
9aef, 309dcd, etc.
08aab, 308aef, 308dcd, etc. are provided.

A node contact hole 302 for connecting the active region 309 to the charge storage electrode 303 is provided on the surface of the node diffusion region. For example,
Word lines 304d and 30 in active region 309bcd
A node contact hole 302bd is provided on the surface of the node diffusion region sandwiched by 4e, and a node contact hole 302bc is provided on the surface of the node diffusion region sandwiched between the word lines 304b and 304c in the active region 309bcd. Similarly, a node contact hole 302ab and the like are provided in the active region 309aab, and the active region 309caab is provided.
b is provided with a node contact hole 302cb and the like, and an active region 309dcd is provided with a node contact hole 302d
c, 302dd are provided, the active region 309cef is provided with node contact holes 302ce, 302cf, and the active region 309aef is provided with the node contact holes 30ce.
2ae and 302af are provided, and the active region 309bgh
Are provided with a node contact hole 302bg and the like, and the active region 309dgf is provided with a node contact hole 302dg and the like.

For example, via a node contact hole 302bd provided in the node diffusion region of the active region 309bcd, the charge storage electrode 3 connected to the node diffusion region is formed.
03bd is a charge storage electrode for (b, d) bits. Similarly, node contact holes 302bc and 302c
b, 302af, 302bg, etc., charge storage electrodes 303bc, 303 connected to the respective node diffusion regions.
cb, 303af, 303bg, etc. are provided.

The surface area A of the charge storage electrode in this embodiment
_T2 is the surface area A _T1 of the charge storage electrode in the first embodiment.
The same effects as those of the first embodiment are obtained. That is, even if the arrangement shape of the active region is changed, it is independent of the change in the surface area of the charge storage electrode.

Next, a third embodiment of the present invention will be described with reference to FIG.
6 will be described. The charge storage electrode in this embodiment has a rectangular shape. The long sides are arranged in parallel to the line connecting the grid point (0, 0) and the grid point (3, 2) described in FIGS.

The bit line 40 is provided on the surface of the P-type silicon substrate.
5a, 405b, 405c, 405d, 405e, 40
5f, word lines 404a, 404b, 404c, 404
d, 404e, etc. are formed, and the word lines 404a, 404b, 404c, 404d, 4 have a direction parallel to the X axis.
04e, and bit lines 405a, 405b, 405c, 405d having a direction orthogonal to the X axis and parallel to the Y axis.
405e and 405f form a matrix. In such a DRAM, an area occupied by one memory cell is, for example, a memory cell 401. The cell size in this case is a word line pitch width P = 1.0 μm.
The product is 2.0 μm ² , which is twice as large as m (line width of word line + interval between word lines) and pitch width P of bit line = 1.0 μm (line width of bit line + interval of bit line).

The shape of the active region (not shown) in this embodiment is the same as in the first embodiment or the second embodiment. For example, a node contact hole 402 is provided on the surface of an active region (node diffusion region) sandwiched between two adjacent bit lines between a word line 404b and a word line 404c. The charge storage electrode 403 is connected to the node diffusion region via the node contact hole 402.

The length of the charge storage electrode 403 in this embodiment
The length of the side is 3.4 μm and the length of the short side is 0.35 μm.
You. Thereby, the upper surface of the charge storage electrode 403 of this embodiment
Area A of_t3Is A_t3= 3.4 μm × 0.35 μm = 1.19 μm^Two  Becomes Area A of the side of this_s3■ is A_s3(1) = 2 × (3.4 μm + 0.35 μm) × 0.5 μ
m^Two= 3.75 μm^Two  Becomes Therefore, its surface area A_T3Is A_T3= A_t3+ A_s3= 4.94 μm^Two  Becomes Thus, in the present embodiment, about 22% of the
The charge storage electrode 403 having a large area can be obtained.

Next, the configuration of the second embodiment of the semiconductor memory device of the present invention will be described with reference to FIG. The charge storage electrodes are densely arranged in the memory cell array while maintaining an interval of the minimum processing dimension F from each other. If the cell size of the memory cell and the A _C, in the charge storage electrode of any shape,
Area of the upper surface of the charge storage electrode area, including the spacing between adjacent charge storage electrode is equal to A _C. As in the second aspect of the present invention, in a case where the shape of the charge storage electrode has a shape which is a combination of at least two rectangular, the perimeter of the charge storage electrode and L _P. This interval is determined by the area (F
/ 2) ² and four square becomes the short side is composed of the six rectangular F / 2. Total six rectangular long side is L _P. Accordingly, the area of this interval is L _P × F / 2 + 4 × (F / 2) ² = L _P × F / 2 + F ² (9) Therefore, the area of the upper surface of the charge storage electrode, the _{A C -L P × F / 2} -F 2 ... (10). Since the thickness (height) of the charge storage electrode is d, the surface area _AT of the charge storage electrode is given by: A _T = A _C −L _P × F / 2−F ² + L _P × d (11) Become. The surface area when the area is maximized with a charge storage electrode having a normal shape is A _T0 , and the circumference is L _P0 . A _T0 is represented by A _T0 = A _C −L _P0 × F / 2−F ² + L _P0 × d (12) In the surface area A _T of the charge storage electrodes of the two types of shapes combining rectangles is more than A _{T0 is, A T -A T0 = (L} P -L P0) (d-F / 2) ≧ 0 ... (13) Since L _P ≧ L _P0 , d ≧ F / 2. That is, when d is F / 2 or more, it is sufficient that L _P is longer than L _P0 . This result is the same as the result of the first embodiment of the present invention.

The above results are summarized as follows. The peripheral length of the charge storage electrode according to the second aspect of the semiconductor memory device of the present invention is longer than the peripheral length of the conventional charge storage electrode. Further, if the thickness of the charge storage electrode of the charge storage capacitor is larger than １ ／ of the minimum processing dimension,
The increase in the area of the side surface of the charge storage electrode according to the second aspect of the semiconductor memory device of the present invention is greater than the decrease in the area of the upper surface. For this reason, the surface area of the charge storage electrode according to the second aspect of the semiconductor memory device of the present invention is larger than the surface area of the conventional charge storage electrode. As a result, a charge storage capacitor having a larger capacitance value than before can be obtained without newly adding a manufacturing method.

Next, a fourth embodiment of the present invention based on the second embodiment will be described with reference to FIG. The memory cells 501 are arranged with a pitch width of P in the horizontal direction parallel to the word lines and 2P in the vertical direction parallel to the bit lines. At the center of the memory cell 501, a node contact hole 502 is provided.

If the shape of the charge storage electrode is a combination of at least two types of rectangles, the shape is L
There are many types such as a letter shape, a T shape, an S shape, and an m shape, but basically a combination of L shapes. A typical example in which the charge storage electrode extends between adjacent memory cells in the vertical direction is the charge storage electrode 503B. In such a case, two or three charge storage electrodes 503B are provided.
It extends vertically between two memory cells. A typical example of the case where the charge storage electrode extends between adjacent horizontal memory cells is the charge storage electrode 503C. Again, in this case,
The charge storage electrode 503C extends horizontally between two or three memory cells. Note that the charge storage electrode 503
A is a charge storage electrode having the maximum surface area of the conventional shape.

Next, for these two types, the allowable range of F for _P and the relationship between F and L _P are shown. In the case of a vertically long shape typified by the charge storage electrode 503B, F ≦ P / 4, L _P = 2 × (5P−4F). In the case of a horizontally long shape represented by the charge storage electrode 503C, F ≦ P / 3, L _P = 8 × (P−F). A graphical representation of these relationships is shown in FIG. In the figure, the range shown by the solid line is the effective range.

[0064]

A word line parallel to the X axis and a bit line parallel to the Y axis have one transistor and one stacked type.
In a DRAM including one charge storage capacitor, a charge storage electrode of the charge storage capacitor is formed by a rectangle whose long side is oblique to the X axis and the Y axis. Alternatively, a charge storage electrode of a charge storage capacitor is formed by combining two or more types of rectangles each having sides parallel to the X axis and the Y axis. Accordingly, the peripheral length of the charge storage electrode becomes longer than the conventional peripheral length of the charge storage electrode. As a result, under the same manufacturing conditions, a charge storage capacitor having a larger capacitance value than the conventional DRAM can be obtained. In particular, the effect is remarkable when the thickness of the charge storage electrode is larger than 1/2 of the minimum processing size and the interval between adjacent charge storage electrodes is equal to the minimum processing size.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a configuration of a first embodiment of a semiconductor memory device of the present invention.

FIG. 2 is a diagram for explaining the configuration of the first embodiment of the semiconductor memory device of the present invention, and is a graph showing the relationship between the film thickness and the surface area of the charge storage electrode.

FIG. 3 is a diagram for explaining the configuration of the first embodiment of the semiconductor memory device of the present invention, and is a graph showing a relationship between a minimum processing dimension and a peripheral length of a charge storage electrode.

FIG. 4 is a schematic plan view for explaining the first embodiment of the present invention.

FIG. 5 is a schematic plan view for explaining the first embodiment of the present invention.

FIG. 6 is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor memory device according to the first embodiment of the present invention, which is a schematic cross-sectional view taken along broken line AB in FIGS.

FIG. 7 is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor memory device according to the first embodiment of the present invention, which is a schematic cross-sectional view taken along broken line AB in FIGS.

FIG. 8 is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor memory device according to the first embodiment of the present invention, and is a schematic cross-sectional view in the order of the process along the broken line AB in FIGS.

FIG. 9 is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor memory device according to the first embodiment of the present invention, which is a schematic cross-sectional view taken along broken line AB in FIGS.

FIG. 10 is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor memory device according to the first embodiment of the present invention;
FIG. 6 is a schematic cross-sectional view taken along a folding line AB in FIG.

FIG. 11 is a schematic cross-sectional view for explaining another method of manufacturing the semiconductor memory device according to the first embodiment of the present invention, and is a schematic cross-sectional view in the order of the process along the broken line AB in FIGS. is there.

FIG. 12 is a schematic cross-sectional view for explaining another method for manufacturing the semiconductor memory device according to the first embodiment of the present invention, and is a schematic cross-sectional view in the order of the process along the broken line AB in FIGS. is there.

FIG. 13 is a schematic cross-sectional view for explaining another method of manufacturing the semiconductor memory device according to the first embodiment of the present invention, and is a schematic cross-sectional view in the order of the process along the broken line AB in FIGS. is there.

FIG. 14 is a schematic plan view for explaining a second embodiment of the present invention.

FIG. 15 is a schematic plan view for explaining a second embodiment of the present invention.

FIG. 16 is a schematic plan view for explaining a third embodiment of the present invention.

FIG. 17 is a diagram illustrating a configuration of a second aspect of the semiconductor memory device of the present invention.

FIG. 18 is a view for explaining a shape of a charge storage electrode according to a fourth embodiment of the present invention.

FIG. 19 is a diagram for explaining the fourth embodiment of the present invention, and is a graph showing the relationship between the minimum processing size and the peripheral length of the charge storage electrode.

FIG. 20 is a schematic plan view for explaining a conventional semiconductor memory device.

21 is a schematic cross-sectional view for explaining a conventional semiconductor memory device, and is a schematic cross-sectional view taken along a broken line AB in FIG.

[Explanation of symbols]

101, 201, 301, 401, 501 Memory cells 102, 202, 302, 402, 502 Node contact holes 103, 203, 303, 403, 503A, 503
B, 503C Charge storage electrode 104, 204, 304, 404 Word line 105, 205, 305, 405 Bit line 106, 206 Bit diffusion region 107, 207 Node diffusion region 108, 208, 308 Bit contact hole 109, 209, 309 Activity Area 110, 210 Capacitance insulating film 111, 211 Cell plate electrode 112, 212 P-type silicon substrate 113, 213 Insulating film 214 BPSG film 215 Spacer

Claims (14)

(57) [Claims] 1. A memory cell comprising one transistor formed on the surface of a silicon substrate and one charge storage capacitor of a stacked type, and a word line formed on the surface of the silicon substrate and having a direction parallel to the X axis. And a bit line having a direction parallel to the Y-axis perpendicular to the X-axis, wherein the charge storage electrode of the charge storage capacitor has a thickness greater than の of a minimum processing dimension in lithography technology. Wherein the shape of the charge storage electrode projected onto the surface of the silicon substrate has a rectangular shape, and has a long side of the rectangle obliquely intersecting an X-axis and a Y-axis. apparatus. 2. The semiconductor memory device according to claim 1, wherein an interval between the adjacent charge storage electrodes is the minimum processing dimension. 3. The wiring pitch of the word line is equal to the wiring pitch of the bit line.
13. The semiconductor memory device according to claim 1. 4. The wiring pitch width of the word line is equal to the wiring pitch width of the bit line.
13. The semiconductor memory device according to claim 1. 5. The rectangle in which the long side of the rectangle is constituted by the ith bit line, the (i + 1) th bit line, the jth word line, and the (j + 2) th word line. 3. The semiconductor memory device according to claim 2, wherein the semiconductor memory device is parallel to one or the other of the diagonal lines. 6. The rectangle in which the long side of the rectangle is constituted by the ith bit line, the (i + 1) th bit line, the jth word line, and the (j + 2) th word line. 5. The semiconductor memory device according to claim 4, wherein said semiconductor memory device is parallel to one or the other of said diagonal lines. 7. The rectangle in which the long side of the rectangle is constituted by the i-th bit line, the (i + 1) -th bit line, the j-th word line, and the (j + 4) -th word line. 3. The semiconductor memory device according to claim 2, wherein said semiconductor memory device is parallel to one or the other of said diagonal lines. 8. The rectangle in which the long sides of the rectangle are constituted by the i-th bit line, the (i + 1) -th bit line, the j-th word line, and the (j + 4) -th word line. 5. The semiconductor memory device according to claim 4, wherein said semiconductor memory device is parallel to one or the other of said diagonal lines. 9. The rectangle in which the long side of the rectangle is constituted by the i-th bit line, the (i + 2) -th bit line, the j-th word line, and the (j + 2) -th word line. 3. The semiconductor memory device according to claim 2, wherein said semiconductor memory device is parallel to one or the other of said diagonal lines. 10. The rectangle in which the long side of the rectangle is constituted by the ith bit line, the (i + 2) th bit line, the jth word line, and the (j + 2) th word line. 5. The semiconductor memory device according to claim 4, wherein said semiconductor memory device is parallel to one or the other of said diagonal lines. 11. The rectangle in which the long side of the rectangle is constituted by the ith bit line, the (i + 3) th bit line, the jth word line, and the (j + 2) th word line. 3. The semiconductor memory device according to claim 2, wherein said semiconductor memory device is parallel to one or the other of said diagonal lines. 12. The rectangle in which the long side of the rectangle is constituted by the ith bit line, the (i + 3) th bit line, the jth word line, and the (j + 2) th word line. 5. The semiconductor memory device according to claim 4, wherein said semiconductor memory device is parallel to one or the other of said diagonal lines. 13. The rectangle in which the long sides of the rectangle are constituted by the ith bit line, the (i + 3) th bit line, the jth word line, and the (j + 4) th word line. 3. The semiconductor memory device according to claim 2, wherein said semiconductor memory device is parallel to one or the other of said diagonal lines. 14. The rectangle in which the long sides of the rectangle are constituted by the ith bit line, the (i + 3) th bit line, the jth word line, and the (j + 4) th word line. 5. The semiconductor memory device according to claim 4, wherein said semiconductor memory device is parallel to one or the other of said diagonal lines.