JP3009230B2 - Correlation processing device, correlation processing method, and image processing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[Contents] Industrial application field Conventional technology (FIGS. 10 and 11) Problems to be Solved by the Invention Means for Solving the Problems (FIGS. 1, 2 and 3) Action Embodiment (1) Book Description of a correlation processing apparatus according to an embodiment of the present invention (FIG. 4)
To FIG. 6) (2) Description of a correlation processing method according to an embodiment of the present invention (FIG. 7)
(FIG. 9) FIG. 8 (3) Description of an image processing apparatus according to an embodiment of the present invention (FIG. 9)

[0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a correlation processing apparatus, a correlation processing method, and an image processing apparatus, and more particularly, to the function of a correlation processing apparatus between a binarized pattern to be correlated and a reference pattern. The present invention relates to an improvement, a method thereof, and an application device thereof.

In recent years, an image processing apparatus has been used which binarizes a video signal obtained from an imaging device such as a camera to create a two-dimensional binary image pattern and compares the pattern with a reference pattern. I have.

According to the correlation processing device built in this device, the comparison processing between the frame pattern and the reference pattern is performed by hundreds of pixels of frame pattern data and hundreds of reference pattern data cut out from the binary image pattern to be acquired. Pixels are performed for each pixel unit (one-to-one).

For this reason, if one side of the correlation processing pattern size is doubled in order to cope with the demand for miniaturization of an object to be inspected such as a semiconductor integrated circuit device, the amount of information required for comparison processing of both patterns is quadrupled. To increase. Thus, the method of checking the frame pattern data and the reference pattern data for each pixel has a problem that a comparison time proportional to the square of one side of the cut-out pattern size is required.

Therefore, a comparison process between the data-compressed correlated pattern and the reference pattern is performed, and even if the number of comparison pixels increases, the amount of data to be handled is reduced, and the correlation processing and pattern inspection are performed at high speed. Equipment that can do
There is a need for a method and its application.

[0007]

2. Description of the Related Art FIGS. 10 and 11 are explanatory views according to a conventional example.

FIG. 10 is a block diagram of a conventional correlation processing apparatus. In the figure, for example, a correlation processing device that performs a shape comparison process between a binary image pattern of an image acquisition target captured by a camera or the like and a reference pattern thereof includes a comparison target area (correlation pattern) of the image acquisition target. Start point setting register 1A, X start point setting register 1B for setting the cutout position of Y, and Y start point setting register 1C, X start point setting register 1 for setting the cutout position of the reference pattern
D and Y counters 2A, 2 which generate those addresses
C, X counters 2B, 2D and correlated pattern data D
And a reference pattern memory 3B for storing reference pattern data D22.
8--1 selector 4A for selecting correlated pattern data D12 and 8-1-selector for selecting reference pattern data D22.
1 selector 4B and the selected correlated pattern data D
It comprises a comparison processing circuit 5 for comparing 12 with the reference pattern data D22, and an output circuit 6 for outputting the comparison result data.

FIGS. 11A and 11B are explanatory diagrams of a correlation processing method according to a conventional example, and FIG. 11A shows a relationship diagram between a frame pattern PA and a reference pattern PB. I have.

In FIG. 1A, a binary image pattern of an image acquisition target such as a semiconductor integrated circuit device imaged by a camera or the like is matched with a reference pattern such as characters and symbols drawn in the one area. When performing (shape comparison) processing, for example, X from the contents of the memory 3A of 512 × 512 pixels is used.
Cut out the frame pattern PA of × Y size,
X × Y size reference pattern PB from the contents of memory 3B
Is read out. At this time, the cutout position of the comparison target area (correlated pattern) of the image acquisition target is set by the Y start point setting register 1A and the X start point setting register 1B, and the cutout position of the reference pattern is set by the Y start point setting register. 1C and X are set by the initial point setting register 1D.

The addresses for reading these pattern data are stored in Y counters 2A, 2C, X counter 2
B and 2D, and the correlated pattern data D12 is read from the correlated pattern memory 3A. In addition,
The reference pattern data D22 is read from the reference pattern memory 3B. The correlated pattern data D12 is 8
-1 selector 4A, and reference pattern data D22 is selected by 8-1 selector 4B.

FIG. 2B is a conceptual diagram showing a comparison process between the frame pattern PA and the reference pattern PB.

In FIG. 1B, both patterns PA, P
The pattern matching process of B is performed by, for example, pattern PA
Is compared with the comparison pixel number of 8 × 10 pixels and the comparison pixel number of the pattern PB = 8 × 10 pixels for each pixel unit (one-to-one). At this time, the comparison processing circuit 5 compares the correlated (hereinafter also referred to as frame) pattern data D12 selected by the 8-1 selectors 4A and 4B with the reference pattern data D22. That is, the comparator of the comparison processing circuit 5 performs an individual comparison operation on 800 pixels to 800 pixels of both data D12 and D22. The comparison result data is output from the output circuit 6. Thereafter, for example, the number of pixels in which the patterns PA and PB do not match is counted, and the cumulative number of mismatches is compared with a determination criterion.

Thus, a pattern matching process between the binary image pattern to be acquired and the reference pattern can be performed.

[0015]

According to the prior art, the comparison process between the frame pattern PA and the reference pattern PB is performed as shown in FIGS. 11 (a) and 11 (b). Frame pattern data D12 = 8 × 10 pixels cut out from the image pattern and reference pattern data D22
= 8 × 10 pixels are compared for each pixel unit (one-to-one).

For this reason, if one side of the pattern size X × Y to be correlated is doubled in order to cope with the demand for miniaturization of the object to be inspected such as a semiconductor integrated circuit device, both patterns P
The amount of information for comparison processing of A and PB is quadrupled. Therefore, in the method of checking the frame pattern data 12 and the reference pattern data D22 for each pixel, a comparison time proportional to the square of one side of the cutout pattern size X × Y is required. Also, in order to improve the evaluation determination accuracy, it is essential to increase the resolution of the optical system of the image processing apparatus.

As a result, there is a problem that as the size of the semiconductor integrated circuit device becomes finer and more highly integrated, the amount of information to be subjected to correlation processing increases, and the correlation processing time also increases. Further, in an image processing apparatus incorporating the correlation processing apparatus, there is a problem that the speed of pattern inspection is hindered.

The present invention has been made in view of the above-described problems of the prior art, and does not compare the correlated pattern and the reference pattern on a pixel-by-pixel basis. And compare it with
It is an object of the present invention to provide a correlation processing apparatus and an image processing apparatus that can reduce the amount of handled data and perform high-speed correlation processing and pattern inspection even when the number of comparison pixels increases.

[0019]

FIG. 1 is a diagram showing the principle of a correlation processing apparatus according to the present invention, FIGS. 2A and 2B are diagrams showing the principle of a correlation processing method according to the present invention, and FIG. 1 shows principle diagrams of an image processing apparatus according to the present invention.

As shown in FIG. 1, the correlation processing apparatus according to the present invention provides the binary image pattern data D1
And a second data compression unit 12 for compressing the reference pattern data D2 of the correlation target 19 and outputting the reference compressed data D21. And a compressed data correlation processing unit 13 for performing a correlation process between the correlated compressed data D11 and the reference compressed data D21, and the compressed data correlation processing unit 13 performs the correlation processing based on a first control signal S1. Correlated compressed data output means 13 for outputting correlated compressed data D11
A, a reference compressed data output means 13B for outputting the reference compressed data D21 based on the second control signal S2, and a data operation for outputting a difference between the correlated compressed data D11 and the reference compressed data D21 as update data DR. Output means 13C
A data comparison output unit 13D for performing a correlation process based on the update data DR, the correlated compressed data D11 and the reference compressed data D21, and the first and second control signals S1, And a data input / output control means 13E for outputting S2.

The correlation processing method of the present invention is shown in FIG.
As shown in (b), first, in step P1, the binary image pattern data D1 of the correlated processing target 19 is compressed, and then in step P2, the compressed correlated compressed data D11 and the correlated compressed data D11 are processed. In a correlation processing method for performing comparison and detection processing with reference compressed data D21 obtained by compressing the reference pattern data D2 of the processing target 19, the comparison and detection processing includes n-bit correlated compressed data D11 and n-bit reference data for each row. The binary image logical value 0/1 of the most significant bit and the same logical value 0 / of the lower n-1 bits of each of the compressed data D21
1 is characterized by performing a comparison update process.

As shown in FIGS. 3 and 1, the image processing apparatus according to the present invention comprises: an image input / output unit 14 for inputting / outputting image acquisition data DIN of an image acquisition target 20; Signal processing means 15 for performing binarization processing and outputting binary image pattern data D1;
Storage means 16 for storing reference pattern data D2 of 0
A correlation processing unit 17 that performs a correlation process between the binary image pattern data D1 and the reference pattern data D2 and outputs correlation result data D3; and a determination based on the correlation result data D3 and the determination reference data D4. Result data Dout
The correlation processing means 17 compresses the binary image pattern data D1 of the correlated processing target 19 and outputs correlated compressed data D11. And compresses the reference pattern data D2 of the correlated processing target 19 to generate the reference compressed data D21.
And compressed data correlation processing means 13 for performing a correlation process between the correlated compressed data D11 and the reference compressed data D21, and the compressed data correlation processing means 13 A correlated compressed data output means 13A for outputting the correlated compressed data D11 based on the first control signal S1, and a reference compressed data output means for outputting the reference compressed data D21 based on the second control signal S2. 13B, a data calculation output unit 13C that outputs the difference between the correlated compressed data D11 and the reference compressed data D21 as update data DR, and based on the update data DR, the correlated compressed data D11 and the reference compressed data D21. A data comparison / output unit 13D for performing a correlation process, and a data input / output control unit 13 for outputting the first and second control signals S1 and S2 based on a reference signal CLK. E.

[0023]

According to the correlation processing apparatus of the present invention, as shown in FIG. 1, a first data compression means 11, a second data compression means 12, and a compressed data correlation processing means 13 are provided.
The compressed data correlation processing means 13 comprises correlated compressed data output means 13A, reference compressed data output means 13B, data operation output means 13C, data comparison output means 13D, and data input / output control means 13E.

For this reason, when the binary image pattern data D1 of the correlated processing target 19 is compressed by the first data compression means 11, the data is processed based on the first control signal S1 from the data input / output control means 13E. The correlation compressed data D11 is supplied to the data operation output means 13 via the correlated compressed data output means 13A.
C, output to the data comparison output means 13D. On the other hand, when the reference pattern data D2 of the correlated processing target 19 is compressed by the second data compression unit 11, the second control signal S2
2, the reference compressed data D21 is output to the data calculation output means 13C and the data comparison output means 13D via the reference compressed data output means 13B. As a result, in the data calculation output means 13C, the difference between the correlated compressed data D11 and the reference compressed data D21 is output to the data comparison output means 13D as update data DR. In the data comparing means 13D,
Correlation processing is performed based on the correlated compressed data D11, the reference compressed data D21, and the update data DR, and as a result, it is possible to output correlation result data D3.

As a result, even if the amount of information for performing the correlation processing with the miniaturization and high integration of the semiconductor integrated circuit device is increased, the frame pattern data D12 and the reference pattern data D22 are not changed as in the conventional example. There is no need to check for each pixel unit, and the correlation processing time can be reduced.

Further, according to the correlation processing method of the present invention, as shown in FIGS. 2A and 2B, following the compression processing of the binary image pattern data D1 at step P1, step P
In step 2, a comparison detection process is performed between the correlated compressed data D11 and the reference compressed data D21 obtained by compressing the reference pattern data D2.

For example, in step P1, the correlated compressed data D11 obtained by compressing the binary image pattern data D1 and the reference pattern data D2 on a line basis based on the number of consecutive identical binary image logical values 0/1; The reference compressed data D21 obtained by compressing the pattern data D2 is combined with the n-bit correlated compressed data D11 and the n-bit reference compressed data D21 each of the most significant bit of the binary image logical value 0 / at step P2.
The comparison and update processing is performed based on the same logical value 0/1 of 1, 1 and lower n-1 bits.

For this reason, it is possible to compare both patterns for each compressed data unit without comparing the correlated pattern and the reference pattern for each pixel unit as in the conventional example. This makes it possible to reduce the amount of handled data even if the number of comparison pixels increases.

Thus, the correlation processing can be performed in a hardware manner, and the speed of pattern inspection and the like of an image processing apparatus incorporating the correlation processing apparatus can be increased.

According to the image processing apparatus of the present invention, as shown in FIG. 3, an image input / output unit 14, a signal processing unit 15, a storage unit 16, a correlation processing unit 17 and a judgment output unit 18 are provided. Means 17 comprises the above-mentioned correlation processing device.

For this reason, when the analog image acquisition signal DIN of the image acquisition target 20 is input to the image input / output means 14, the acquisition signal DIN is binarized by the signal processing means 15, and the binary image pattern The data D1 is output to the correlation processing unit 17. Further, the reference pattern data D2 of the image acquisition target 20 stored in the storage unit 16 is read out and output to the correlation processing unit 17. As a result, the binary image pattern data D1 and the reference pattern data D2 are correlated by the correlation processing unit 17, and the correlation result data D3 is output to the determination output unit 18. The judgment output means 18 outputs the correlation result data D
3 and the determination result data D based on the determination reference data D4.
out can be output by the judgment output means 18.

As a result, even when the amount of information for performing the correlation processing accompanying the miniaturization and high integration of the semiconductor integrated circuit device increases, the image compression / correlation processing is performed, so that the image processing time can be reduced. It is possible to improve the resolution of the optical system of the image processing apparatus. Further, it is possible to improve the evaluation determination accuracy and the performance of the image processing apparatus.

In the image processing apparatus, the second data compression unit 12 can be omitted by storing the compressed reference pattern data D21 of the image processing target 20 in the storage unit 16 in advance. Becomes

This makes it possible to reduce the size and cost of the image processing apparatus.

[0035]

Next, an embodiment of the present invention will be described with reference to the drawings.

FIGS. 4 to 9 are diagrams for explaining a correlation processing apparatus, a correlation processing method, and an image processing apparatus according to an embodiment of the present invention.

(1) Description of the Correlation Processing Apparatus According to the Embodiment of the Present Invention (FIGS. 4 to 6) FIGS. 4A and 4B are explanatory diagrams of the correlation processing apparatus according to the embodiment of the present invention. FIG. 1A shows a configuration diagram of the same.

In FIG. 1A, a correlation processing device incorporated in a pattern inspection device or the like includes a frame data compression circuit 21, a reference data compression circuit 22, and a compressed data correlation processing circuit 23.

That is, the frame data compression circuit 21 is an embodiment of the first data compression means 11, and is a target for correlation processing (for example, a Roman character "A") 1 as shown in FIG.
9 to compress the binary image pattern data D1 and output correlated compressed data (hereinafter, sometimes simply referred to as frame data FM) D11 to the frame data memory 30A.

The reference data compression circuit 22 is an embodiment of the second data compression means 12, and compresses the reference pattern data D2 of the target 19 to be correlated to generate reference compressed data (hereinafter sometimes simply referred to as reference data JM). ) D21 is output to the reference data memory 30B. The compression function of each of the compression circuits 21 and 22 will be described with reference to FIG.

The compressed data correlation processing circuit 23 is an embodiment of the compressed data correlation processing means 13 and performs a correlation process between the correlated compressed data D11 and the reference compressed data D21. Note that the compressed data correlation processing circuit 23 is shown in FIG.
In the following, the frame data memory 30A and the reference data memory 30B will be described in detail using a data supply source.

FIG. 6B shows a data structure handled in the correlation processing apparatus according to the embodiment of the present invention.

In FIG. 6B, DF is a data format, and the compressed data D11 and the reference pattern data D21 are used in the correlation processor according to the embodiment of the present invention.
3 shows a data structure of the data. For example, in the case of an 8-bit compressed data structure, the 0th to 6th bits indicate binary image logical length (maximum 128 pixels) data, and the 7th bit indicates the binary image logical value (1/0). ) Shows the data.

FIG. 5 is a functional explanatory diagram of each data compression circuit according to the embodiment of the present invention. In the figure, for example, when the correlated processing target 19 is a Roman character “A” and its binary image pattern (all pixels = 14 columns × 14 rows =
196 pixels) to create a compressed image pattern,
The compression process is performed by counting logical values (1/0) that are continuous in each row direction. At this time, a compression process is performed based on the data format DF.

For example, if attention is paid to the columns X1 to X14 in the Y6th row of the binary image pattern, the logical value "0" is obtained.
, Followed by two “1”, three “0”, two “1”, and four “0”.

When this is compressed, first, for three consecutive logical values "0", "000" is displayed in binary notation.
00011 "(" 03 "in hexadecimal notation). Then, for two consecutive logical values" 1 "," 10 "
000010 "[similarly," 12 "]. For three consecutive logical values "0", "000000011"
[“03”], and for two consecutive logical values “1”, similarly, “10000010” [similarly, “12”]. Note that, for four consecutive logical values “0”, “0”
0001111 "[" 04 "].

As a result, the binary image pattern of the Roman character “A” of 14 columns × 14 rows = 196 pixels is obtained from the Y1 row = 0E,
00, Y2 line = 06, 11, 07, 00,... Y6 line = 03, 12, 03, 12, 04, 00,.
The data can be compressed to 64 data of 0E and 00 (both in hexadecimal) (the number of comparison processing data is 48).
“00” of each compressed data indicates an end flag.

FIG. 6 is a configuration diagram of a compressed data correlation processing circuit according to an embodiment of the present invention. In the figure, a compressed data correlation processing circuit 23 as one embodiment of the compressed data correlation processing means 13 includes a frame data output circuit 23A, a reference data output circuit 23B, a data operation output circuit 23C, a data comparison output circuit 23C, and a data input / output. It comprises a control circuit 23E.

That is, the frame data output circuit 23A is an embodiment of the correlated compressed data output means 13A, and includes an address update circuit 31, a frame data memory 30A, a tristate buffer 32, and a frame data holding circuit (hereinafter referred to as an FM data holding circuit). 33). The function of the frame data output circuit 23A is to convert the frame data FM from the frame data memory 30A based on the inverted data (X) update pulse SP2, the coincidence detection pulse SP4, the Y update pulse SP5, etc., which are examples of the first control signal S1. When the read processing is performed, the data FM is input to the FM data holding circuit 33 together with the difference data (absolute value) between the frame data FM and the reference data JM via the tristate buffer 32 for avoiding data collision. In the data holding circuit 33, based on the non-inverted data (X) update pulse SP1, the logic value (1/0) data of the seventh bit of the frame data FM and the logic length data of the 0th to 6th bits Are output held.

The reference data output circuit 23B is an embodiment of the reference compressed data output means 13B.
4, reference data memory 30B, tristate buffer 3
5, a reference data holding circuit (hereinafter referred to as a JM data holding circuit) 36 and an X data end check circuit 37. The function of the reference data output circuit 23B is that the reference data memory 30B outputs the reference data JM from the reference data memory 30B based on the non-inverted data (X) update pulse SP1, the coincidence detection pulse SP4, the Y update pulse SP5, etc., which are examples of the second control signal S2. Is read out, the data JM passes through a tristate buffer 35 for avoiding data collision, and a reference data holding circuit (hereinafter referred to as JM) together with the difference (update) data (absolute value) between the frame data FM and the reference data JM. (Referred to as a data holding circuit) 36. In the data holding circuit 36, based on the inverted data (X) update pulse SP2, the logic value (1/0) data of the seventh bit of the reference data JM and the logic length data of the 0th to 6th bits are added. Is held as output.

The data operation output circuit 23C is an embodiment of the data operation output means 13C, and includes a subtractor (AB) 42, an absolute value circuit 43, a holding circuit 44, and a tristate buffer 4.
5, a first inverter IN1 and a selection circuit 46.

The function of the data operation output circuit 23C is to update the difference data (remainder) between the binary image logical length data A and B of the frame data FM and the reference data JM.

That is, when the binary image logical length data A and B of the 0th to 6th bits of the frame data FM and the reference data JM are calculated by the subtractor (AB), the result is obtained. Polarity +/- [1/0] instruction pulse SP5 is the second
To the inverters IN2 and AND3 and the selection circuit 46.

Further, the difference data AB is input to the absolute value circuit 4.
3, and the holding circuit 44 holds the absolute value AB. Further, the tristate buffer 45 supplies the difference data AB to the FM data holding circuit 33 and the JM data holding circuit 36 in the same manner as the outputs of the tristate buffers 32 and 35 based on the selection control signal SS from the selection circuit 46. Is done. At this time, the selection control signal SS
Is the binary image logical value of the seventh bit of the frame data FM and the reference data JM and the polarity +/- [1/0] instruction pulse SP5
Is output from the selection circuit 46 to the tristate buffer 45 based on the signal obtained by inverting the signal by the first inverter IN1.

The data comparison output circuit 23D is an embodiment of the data comparison output means 13D, and includes a comparator 38, a selector 3
9, an adder (cumulative mismatch) 40, an addition holding circuit 41, an OR circuit (hereinafter referred to as OR1), an exclusive OR circuit (hereinafter referred to as NOR1), and a first AND circuit (hereinafter referred to as AND1).
).

The function of the data comparison output circuit 23D is to perform a correlation process with the frame data FM, the reference data JM and the update data DR based on the mismatch addition instruction pulse SP3. At this time, first, the non-coincidence of the binary image logical value of the seventh bit between the frame data FM and the reference data JM is calculated by NOR1. For example, when the binary image logical values do not match, “1” is output. Also, AN
D1 mismatch = "1" and mismatch addition instruction pulse SP3
Are subjected to a logical product operation. The result is output to the adder 40.

The comparator 38 compares the binary image logical length data of the 0th to 6th bits between the frame data FM and the reference data JM. Here, A is the binary image logical length data of the frame data FM, and indicates the binary image logical length data of the 0th to sixth bits of the frame data FM. B is the binary image logical length data of the reference data JM, and indicates the binary image logical length data of the 0th to sixth bits of the reference data JM.

That is, in the case of such data, the function of the comparator 38 is to calculate the magnitude relationship between the two data A and B. For example, when both data A> B, the first function is used. Is output to the selector 39, and if both data are A <B, the second comparison control pulse CP2 is output to OR1. When both data are A = B, the coincidence detection pulse SP4 is output to the address update circuits 31, 34 and OR1.

Further, OR1 is the second comparison control pulse C
The logical sum operation of P2 and the coincidence detection pulse SP4 is performed, and the result signal SA is output to the selector 39.

The selector 39 outputs the first comparison control pulse C
The two data A and B are selectively output based on P1 and the result signal SA. In the embodiment of the present invention, the result signal SA
Is activated, data A is selected, and when the first comparison control pulse CP1 is activated, data B is selected.

An adder (cumulative non-coincidence) 40 provides a discrepancy between the binary image logical values of the frame data FM and the reference data JM =
Cumulative addition of "1" and mismatch of binary image logic value based on update process of binary image logical length data from bit 0 to bit 6 of both data FM and JM = "1" It is. The addition and holding circuit 41 holds and outputs the number of inconsistencies accumulated and added.

The data input / output control circuit 23E is an embodiment of the data input / output control means 13E, and includes a second inverter IN.
2, a second AND circuit (hereinafter referred to as AND2) and a third AND circuit
(Hereinafter referred to as AND3).

The functions of the data input / output control circuit 23E are as follows: the inverted data (X) update pulse SP1, the non-inverted data (X)
It outputs the update pulse SP2 and the like.

That is, the inverted data (X) update pulse S
P1 is output from AND2 based on a data update pulse as one embodiment of the reference signal CLK and a signal obtained by inverting the polarity +/- [1/0] instruction pulse SP5 by the second inverter IN2.

The non-inverted data (X) update pulse SP2
Is output from the AND3 based on the data update pulse and the polarity +/- [1/0] instruction pulse SP5.

As described above, according to the correlation processing apparatus according to the embodiment of the present invention, as shown in FIGS. 4 to 6, the frame data compression circuit 21, the reference data compression circuit 22, and the compressed data correlation processing circuit 23 The compressed data correlation processing circuit 23 comprises a frame data output circuit 23A, a reference data output circuit 23B, a data operation output circuit 23C, a data comparison output circuit 23D, and a data input / output control circuit 23E.

Therefore, when the binary image pattern data D1 of the correlated processing target 19 is compressed by the frame data compression circuit 21, the frame is generated based on the inverted data (X) update pulse SP2 from the data input / output control circuit 23E. The data FM is output to the data operation output circuit 23C and the data comparison output circuit 23D via the frame data output circuit 23A.
On the other hand, when the reference pattern data D2 of the correlated processing target 19 is compressed by the reference data compression circuit 22, the reference data JM is subjected to data calculation via the reference data output circuit 23B based on the non-inverted data (X) update pulse SP1. Output circuit 23
C, output to the data comparison output circuit 23D. This allows the data operation output circuit 23C to output the frame data F
The updated data DR is output to the data comparison output means 13D based on M and the reference data JM. The data comparison and output means 13D performs a correlation process based on the frame data FM, the reference data JM, and the update data DR.
It becomes possible to output the correlation result data D3.

As a result, even when the amount of information for performing the correlation processing with the miniaturization and high integration of the semiconductor integrated circuit device is increased, the frame pattern data D12 and the reference pattern data D22 are set to one as in the conventional example. There is no need to check for each pixel unit, and the correlation processing time can be reduced. For example, the comparison processing time [approximately 1/4] based on the data obtained by compressing the binary image pattern of Roman character "A" of 14 columns × 14 rows = 196 pixels into 64 (the number of comparison processing data is 48) is reduced. It is possible to do.

Next, the correlation processing method according to the embodiment of the present invention will be described while supplementing the operation of the apparatus.

(2) Description of the Correlation Processing Method According to the Embodiment of the Present Invention FIG. 7 is a flowchart of the correlation processing method according to the embodiment of the present invention, and FIGS. 8A and 8B are supplementary explanations. FIG.

In FIG. 7, first, in step P1, FIG.
The compression processing of the binary image pattern data D1 of the correlated processing target 19 as shown in FIG. The compression process at this time is
14 columns × 14 rows = 196 pixels of Roman image “A” binary image pattern data D1 and reference pattern data D2 are compressed by measuring the continuous number of identical binary image logical values 0/1 in row units. (See FIG. 5).

Next, a method for comparing and detecting coincidence and non-coincidence between the frame data FM compressed in any one of the steps P2 to P17 and the reference data JM obtained by compressing the reference pattern data D2 of the correlated processing target 19 And For example, a case will be described in which the correlation processing on the Y6th line is performed.

Here, as shown in FIG. 8B, the frame data FM in the Y6th row is 03, 12, 03, 12, 0
4,000, and the reference data JM is 02, 14, 0
2, 13, 03, 00 (all displayed in hexadecimal).
Further, Table 1 supplements the correlation processing method in the Y6th row. Steps P to P in the table correspond to any one of Steps P2 to 17 according to the embodiment of the present invention in hardware.
It shows that it repeats times.

[0074]

[Table 1]

That is, in the step P2, the seventh
A determination process is performed to determine whether or not the binary image logical values of the bit do not match. At this time, if the binary image logics do not match (YES), the program shifts to Step P3. If the binary image logical values match (NO), the program shifts to Step P4. In the embodiment of the present invention, since the binary image logical value “0” of the frame data FM = 03 and the reference data JM = 02 matches, the process shifts to Step P4, and the binary image logical length data “3” and “2” Does not match, the process also proceeds to Step P3.

Therefore, in step P4, a process for determining whether or not the subtraction result has a positive polarity is performed. At this time, if the subtraction result has a positive polarity (YES), the flow shifts to Step P6. If the subtraction result is not positive (NO), the program shifts to Step P13. In the embodiment of the present invention, the process proceeds to Step P6 because the case corresponds to the case where the subtraction result has positive polarity (YES).

Next, in step P3, the frame data F
A determination is made as to whether M is greater than the reference data JM. At this time, if the data FM is larger than the reference data JM (YES), the program shifts to Step P5. Also,
When the data FM is smaller than the reference data JM (NO)
The process proceeds to Step P6. In the embodiment of the present invention, since the relationship between the two data FM and JM is FM = 03> JM = 02, the process shifts to Step P5.

Therefore, in step P5, a process of adding the total of mismatches + the reference data JM → the total of mismatches is performed. At this time,
In the embodiment of the present invention, the binary image logical values of both data FM and JM are both "0" and coincide. As a result, since the mismatch total is “0”, no addition processing is required.

Next, in step P6, the frame data FM
And the reference data JM are subtracted. At this time, the subtraction result (difference) between the two data FM and JM becomes “1”. As a result, the updated data DR = 1 is stored in the FM data holding circuit 33.

Thereafter, in step P7, the reference data JM is updated. At this time, the reference data JM = 14 is read out based on the inverted data (X) update pulse SP2 from the AND2 of the data operation output circuit 23D.

Thus, the process of step P in Table 1 ends. Next, the process proceeds to the process of step P in Table 1.

That is, in step P2, it is determined whether or not the binary image logical values of the frame data FM = 01 based on the updating process and the reference data JM = 14 based on the step P do not match. At this time, the binary drawing logic is “0”,
Since it is "1", it is determined that there is no match (YES). Therefore, the process proceeds to steps P3 and P4. Step P3
Then, the frame data FM = 01 becomes the reference data JM = 14.
A determination is made as to whether or not the value is greater than the value. At this time, when the data FM is smaller than the reference data JM (NO), the process shifts to Step P8.

Therefore, in step P4, a process for determining whether or not the subtraction result has a positive polarity is performed. At this time, if the subtraction result has a positive polarity (YES), the flow shifts to Step P6. If the subtraction result is not positive (NO), the program shifts to Step P13. In the embodiment of the present invention, the process proceeds to Step P13 because the subtraction result has the negative polarity (YES), and then proceeds to Step P10.

In step P8, the frame data F
It is determined whether M = 01 is smaller than or equal to the reference data JM = 14. At this time, when the data FM is smaller than the reference data JM (NO), the process shifts to Step P9.

In step P9, as in step P5, the process of adding the total of mismatches + the reference data JM → the total of mismatches is performed. At this time, in the embodiment of the present invention, both data FM = 0
The binary image logical values of 1, JM = 14 do not match between "0" and "1". As a result, the mismatch “1” is added, and the total becomes “1”.

Thereafter, in step P10, the frame data F
The absolute value of the subtraction result between M and the reference data JM is calculated. At this time, the subtraction result (difference) between the two data FM and JM is “3”, and as a result, the update data DR = 3
Is stored in the JM data holding circuit 36.

Next, at step P11, the frame data FM
Update process. At this time, the data operation output circuit 23D
The frame data FM = 12 is read out based on the non-inverted data (X) update pulse SP1 from AND3.

Thus, the processing of step P in Table 1 ends. Further, the processing shifts to the processing of step P in Table 1.

That is, in step P2, it is determined whether or not the binary image logical values of the frame data FM = 12 based on the step P and the reference data JM = 13 based on the update processing do not match. At this time, if the binary image logics match (NO), the process proceeds to steps P3 and P4.

At step P3, the frame data FM = 1
It is determined whether or not 2 is larger than the reference data JM = 13. At this time, when the data FM is smaller than the reference data JM (NO), the process shifts to Step P8.

Therefore, in step P8, it is determined whether or not the frame data FM = 12 is smaller than or equal to the reference data JM = 13. At this time, when the data FM is smaller than the reference data JM (NO), the process shifts to Step P9.

In step P9, as in step P5, an addition process is performed for the sum of mismatches + the reference data JM → the sum of mismatches. At this time, in the embodiment of the present invention, both data FM = 1
The binary image logical values of 2, JM = 13 match "1" and "1". As a result, the addition process of the mismatch “1” is not required, and the total is still “1”.

Then, in step P10, the frame data F
The absolute value of the subtraction result between M and the reference data JM is calculated. At this time, the subtraction result (difference) between the two data FM and JM is “1”. As a result, JM = 1 is stored in the JM data holding circuit 36 as the update data DR.

Next, at step P11, the frame data FM
Update process. At this time, the data operation output circuit 23D
The frame data FM = 03 is read out based on the inverted data (X) update pulse SP2 from AND2.

Thus, the process of step P in Table 1 is completed. Further, the processing shifts to the processing of step P in Table 1.

That is, in step P2, it is determined whether or not the binary image logical values of the frame data FM = 03 based on the step P and the reference data JM = 11 based on the update processing do not match. At this time, if the binary image logics do not match (YES), the process proceeds to Step P3.

In step P3, the frame data FM = 0
A determination process is performed to determine whether or not 3 is larger than the reference data JM = 11. At this time, when the data FM is smaller than the reference data JM (NO), the process shifts to Step P8.

Therefore, in step P8, it is determined whether the frame data FM = 03 is smaller than or equal to the reference data JM = 11. At this time, when the data FM is smaller than the reference data JM (NO), the process shifts to Step P9.

In step P9, as in step P5, the processing of adding the total of the mismatches + the reference data JM → the total of the mismatches is performed. At this time, in the embodiment of the present invention, both data FM = 0
3, the binary image logical values of JM = 11 do not match between “0” and “1”. As a result, the mismatching “1” is added,
The total is “2”.

Thereafter, in step P10, the frame data F
The absolute value of the subtraction result between M and the reference data JM is calculated. At this time, the subtraction result (difference) between the two data FM and JM is “2”. As a result, FM = 2 is stored in the FM data holding circuit 33 as the update data DR.

Next, at step P11, the frame data FM
Update process. At this time, the data operation output circuit 23D
The reference data JM = 02 is read out based on the inverted data (X) update pulse SP2 from AND2.

Thus, the process of step P in Table 1 ends. Further, the processing shifts to the processing of step P in Table 1.

That is, in step P2, it is determined whether or not the binary image logical values of the frame data FM = 02 based on the update processing and the reference data JM = 02 based on step P do not match. At this time, if the binary image logics match (NO), the process proceeds to step P4 only.

Therefore, in step P4, a process for determining whether or not the subtraction result has a positive polarity is performed. At this time, if the subtraction result has a positive polarity (YES), the flow shifts to Step P6. If the subtraction result is not positive (NO), the program shifts to Step P13. In the embodiment of the present invention, since the subtraction result is “0”, that is, the case where the frame data FM = 02 is equal to the reference data JM = 02 (NO), the process shifts from step P13 to step P14.

At step P14, it is determined whether or not the X data is completed. At this time, if the end of X data (YES)
Then, the process shifts to Step P15. If the X data is not completed (NO), the process shifts to Step P16. In the embodiment of the present invention, when X data is not completed (NO)
In step P16, the frame data FM and the reference data JM are updated. Here, the reference data J based on the inverted and non-inverted data (X) update pulses SP2 and SP1 from AND2 and AND3 of the data operation output circuit 23D.
M = 13 and frame data FM = 12 are read out.

Thus, the process of step P in Table 1 ends. Further, the processing shifts to the processing of step P in Table 1.

That is, in step P2, it is determined whether or not the binary image logical values of the frame data FM = 12 based on the step P and the reference data JM = 13 based on the update processing do not match. At this time, if the binary image logics match (NO), the process proceeds to steps P3 and P4.

In step P3, the frame data FM = 1
It is determined whether or not 2 is larger than the reference data JM = 13. At this time, when the data FM is smaller than the reference data JM (NO), the process shifts to Step P8.

Therefore, in step P8, it is determined whether or not the frame data FM = 12 is smaller than or equal to the reference data JM = 13. At this time, when the data FM is smaller than the reference data JM (NO), the process shifts to Step P9.

In step P9, as in step P5, the process of adding the total of mismatches + the reference data JM → the total of mismatches is performed. At this time, in the embodiment of the present invention, both data FM = 0
The binary image logical values of 1, JM = 13 coincide with “1” and “1”. As a result, the adding process of the mismatch “1” is not required, and the total thereof remains “2”.

Thereafter, in step P10, the frame data F
The absolute value of the subtraction result between M and the reference data JM is calculated. At this time, the subtraction result (difference) between the two data FM and JM is “1”. As a result, JM = 1 is stored in the JM data holding circuit 36 as the update data DR.

Next, at step P11, the frame data FM
Update process. At this time, the data operation output circuit 23D
The frame data FM = 04 is read out based on the inverted data (X) update pulse SP2 from AND2.

Thus, the processing of step P in Table 1 ends. Further, the processing shifts to the processing of step P in Table 1.

That is, in step P2, it is determined whether or not the binary image logical values of the frame data FM = 04 based on step P and the reference data JM = 11 based on the update processing do not match. At this time, if the binary image logics do not match (YES), the process proceeds to steps P3 and P4.

Therefore, in step P4, a process of determining whether or not the subtraction result has a positive polarity is performed. At this time, if the subtraction result has a positive polarity (YES), the flow shifts to Step P6. If the subtraction result is not positive (NO), the program shifts to Step P13. In the embodiment of the present invention, the process proceeds to Step P6 because the case corresponds to the case where the subtraction result has positive polarity (YES).

In step P3, the frame data FM = 0
A determination process is performed to determine whether or not 4 is larger than the reference data JM = 11. At this time, when the data FM is larger than the reference data JM (YES), the process proceeds to Step P5.

Therefore, in step P5, the process of adding the total of mismatches + the reference data JM → the total of mismatches is performed. At this time, in the embodiment of the present invention, both data FM = 04, JM = 1
The binary image logical value of 1 does not match between "0" and "1". As a result, the mismatch “1” is added, and the total is “3”.

In step P6, the frame data FM
And the reference data JM are subtracted. At this time, the subtraction result (difference) between the two data FM and JM is “3”. As a result, the updated data DR = 3 is stored in the FM data holding circuit 33.

Thereafter, in step P7, the reference data JM is updated. At this time, the reference data JM = 03 is read out based on the inverted data (X) update pulse SP2 from AND2 of the data operation output circuit 23D.

Thus, the processing of step P in Table 1 ends. Further, the processing shifts to the processing of step P in Table 1.

That is, in step P2, it is determined whether or not the binary image logical values of the frame data FM = 03 based on the step P and the reference data JM = 03 based on the update processing do not match. At this time, if the binary image logics match (NO), the process proceeds to step P4 only.

Accordingly, in step P4, a process for determining whether or not the subtraction result has a positive polarity is performed. At this time, if the subtraction result has a positive polarity (YES), the flow shifts to Step P6. If the subtraction result is not positive (NO), the program shifts to Step P13. In the embodiment of the present invention, since the subtraction result is “0”, that is, the case where the frame data FM = 03 is equal to the reference data JM = 03 (NO), the process shifts from step P13 to step P14.

At step P14, it is determined whether or not X data has been completed. At this time, if the end of X data (YES)
Then, the process shifts to Step P15. If the X data is not completed (NO), the process shifts to Step P16. In the embodiment of the present invention, this corresponds to the case where the X data ends (YES), so that the routine shifts to Step P15.

Accordingly, in step P15, a process for determining whether or not the end of the Y data is performed. At this time, if the end of the Y data (YES), the correlation processing ends. If the Y data has not been completed (NO), the program shifts to Step P17.

As a result, the processing in step P in Table 1 is completed, and the correlation processing in the Y6th row is completed by the end flag in step P. Thus, the mismatch number “3” in the Y6th row can be detected.

As described above, according to the correlation processing method according to the embodiment of the present invention, as shown in the flowchart of FIG. And the frame data FM
And the reference data JM.

For example, in step P1, the binary image pattern data D1 and the reference pattern data D2 are compressed on a line-by-line basis on the basis of the number of consecutive identical binary image logical values 0/1.
8-bit frame data FM and reference pattern data D
In step P2 to P17, the 8-bit reference data JM obtained by compressing 2 is converted into a 7-bit binary image logical value 0/1 and a 0-th to 6-bit identical logical value 0/1 in units of rows. Based on the comparison update process.

For this reason, it is possible to perform a comparison process for each of the compressed data units without having to compare the correlated pattern and the reference pattern for each pixel as in the conventional example. This makes it possible to reduce the amount of handled data even if the number of comparison pixels increases.

As a result, the correlation processing can be performed in a hardware manner, and the speed of pattern inspection and the like of an image processing apparatus incorporating the correlation processing apparatus can be increased.

(3) Description of Image Processing Apparatus According to Embodiment of the Present Invention FIG. 9 is a configuration diagram of an image processing apparatus according to an embodiment of the present invention.

In the figure, an image processing device such as an LSI device for performing pattern inspection or the like includes a camera 29, a signal input / output circuit 24, an A / D converter 25, a ROM 26, a correlation processing circuit 2
7 and a judgment output circuit 28.

That is, the camera 29 is the object 2
0, and outputs an analog image acquisition signal as an example of image acquisition data DIN. The signal input / output circuit 24 is an embodiment of the image input / output unit 14, and is an I / O interface circuit for inputting / outputting image acquisition data DIN of the image acquisition target 20 or the like.

The A / D converter 25 is a signal processing means 1
5 is an embodiment in which image acquisition data DIN is binarized and binary image pattern data D1 is output. The ROM (read only memory) 26 is an embodiment of the storage means 16 and stores the reference pattern data D2 of the image acquisition target 20. In the embodiment of the present invention, uncompressed reference pattern data D2 is stored. Further, the storage means 16 may be a RAM (memory that can be written and read at any time).

The correlation processing circuit 27 is an embodiment of the correlation processing means 17, and performs a correlation process between the binary image pattern data D1 and the reference pattern data D2 to obtain correlation result data D3.
Is output. Here, the correlation processing circuit 27 is characterized by comprising the correlation processing device according to the embodiment of the present invention shown in FIGS. Therefore, the description of the operation function and the like is omitted (see FIGS. 7 and 8).

The comparison output circuit 28 is provided with the judgment output means 1
8 is an example of outputting the judgment result data Dout based on the correlation result data D3 and the judgment reference data D4.

As described above, according to the image processing apparatus according to the embodiment of the present invention, as shown in FIG. 9, the signal input / output circuit 24, the A / D converter 25, the ROM 26, the correlation processing circuit 2
7 and a judgment output circuit 28, and the correlation processing circuit 2
Reference numeral 7 denotes a correlation processing device according to the embodiment of the present invention.

Therefore, when the analog image acquisition signal DIN of the image acquisition target 20 is input to the signal input / output circuit 24, the acquisition signal DIN is binarized by the A / D converter 25, and the binary The image pattern data D1 is output to the correlation processing circuit 27. Further, the reference pattern data D2 of the image acquisition target 20 stored in the ROM 26 is read out and output to the correlation processing circuit 27. As a result, the binary image pattern data D1 and the reference pattern data D2 are correlated by the correlation processing circuit 27, and the correlation result data D3 is output to the judgment output means 18.
The judgment output circuit 28 judges the judgment result data Dout based on the correlation result data D3 and the judgment reference data D4.
Can be output.

As a result, even when the amount of information for performing the correlation processing accompanying the miniaturization and high integration of the semiconductor integrated circuit device increases, the image compression / correlation processing is performed, so that the image processing time can be reduced. It is possible to improve the resolution of the optical system of the image processing apparatus. Further, it is possible to improve the evaluation determination accuracy and the performance of the image processing apparatus.

In the image processing apparatus, the reference data compression circuit 22 can be omitted by storing the compressed reference pattern data D21 of the image processing target 20 in the ROM 26 or the like in advance.

As a result, it is possible to reduce the size and cost of the image processing apparatus.

[0141]

As described above, according to the correlation processing apparatus of the present invention, the first and second data compression means, the correlated compressed data output means, the reference compressed data output means, the data calculation output means, and the data A compressed data correlation processing means 13 comprising a comparison output means and a data input / output control means 13E is provided.

For this reason, the correlated compressed data and the reference compressed data compressed by the first and second data compression means are supplied to the data calculation output means and the data comparison means via the correlated compressed data output means and the reference compressed data output means. Output to output means. As a result, the updated data is output from the data calculation output means to the data comparison output means, and the data comparison output means performs correlation processing based on the correlated compressed data, the reference compressed data, and the update data. Data is output. This makes it possible to reduce the correlation processing time even when the amount of information for performing the correlation processing accompanying the miniaturization and high integration of the semiconductor integrated circuit device increases.

Further, according to the correlation processing method of the present invention, following the compression processing of the binary image pattern data, the comparison detection processing of the correlated compressed data and the reference compressed data is performed.

Therefore, it is possible to compare both patterns for each compressed data unit without comparing the correlated pattern and the reference pattern for each pixel as in the conventional example. This makes it possible to reduce the amount of handled data even if the number of comparison pixels increases.

Further, according to the image processing apparatus of the present invention, there are provided an image input / output means, a signal processing means, a storage means, a correlation processing means and a judgment output means, wherein the correlation processing means comprises the above-mentioned correlation processing according to the present invention. Made of equipment.

Therefore, the analog image acquisition signal to be acquired is binarized by the signal processing means, and the binary image pattern data is output to the correlation processing means. Further, the reference pattern data or the reference compressed data stored in the storage means is read out and output to the correlation processing means. Thus, the correlated compressed data and the reference compressed data are correlated by the correlation processing means, and the judgment output means can perform the judgment processing based on the correlation result data and the judgment reference data.

As a result, the correlation processing can be performed in a hardware manner, so that the speed of pattern inspection of the semiconductor integrated circuit device can be increased, and the resolution of the optical system of the image processing device can be increased. In addition, it greatly contributes to improvement of evaluation determination accuracy and improvement of performance of the image processing apparatus.

[Brief description of the drawings]

FIG. 1 is a principle diagram of a correlation processing apparatus according to the present invention.

FIG. 2 is a principle diagram of a correlation processing method according to the present invention.

FIG. 3 is a principle diagram of an image processing apparatus according to the present invention.

FIG. 4 is a configuration diagram of a correlation processing device according to an embodiment of the present invention.

FIG. 5 is an explanatory diagram of functions of each data compression circuit according to the embodiment of the present invention.

FIG. 6 is a configuration diagram of a compressed data correlation circuit according to an embodiment of the present invention.

FIG. 7 is a flowchart of a correlation processing method according to an embodiment of the present invention.

FIG. 8 is a supplementary explanatory diagram of the flowchart according to the embodiment of the present invention.

FIG. 9 is a configuration diagram of an image processing apparatus according to an embodiment of the present invention.

FIG. 10 is a configuration diagram of a correlation processing circuit according to a conventional example.

FIG. 11 is an explanatory diagram of a correlation processing method according to a conventional example.

[Explanation of symbols]

11: first data compression means, 12: second data compression means, 13: compressed data correlation processing means, 13A: correlated compressed data output means, 13B: reference compressed data output means, 13
C: data calculation output means, 13D: data comparison output means,
13E: data input / output control means, 14: image input / output means,
15: Signal processing means, 16: Storage means, 17: Correlation processing means, 18: Judgment output means, D1: Binary image pattern data, D2: Reference pattern data, D3: Correlation result data, DR: Update data, D11 ... Correlated compressed data, D21
... Reference compressed data, S1, S2, first and second control signals, DIN, image acquisition data, Dout, determination result data.

Continuation of the front page (56) References JP-A-62-249292 (JP, A) JP-A-62-249293 (JP, A) JP-A-58-161022 (JP, A) JP-A-64-61881 (JP) , A) JP-A-57-137978 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G06T 7/00

Claims (4)

(57) [Claims] The binary image pattern data (D1) of an object (19) to be correlated is compressed to generate compressed data (D1).
A first data compression means (11) for outputting 1) and reference pattern data (D2) for the correlated processing object (19)
A second data compression means (12) for compressing the compressed compressed data and outputting the reference compressed data (D21);
1) and a compressed data correlation processing unit (13) for performing a correlation process between the reference compressed data (D21) and the compressed data correlation processing unit (13) based on the first control signal (S1). The correlated compressed data output means (13A) for outputting the correlated compressed data (D11), and the reference compressed data (D2) based on a second control signal (S2).
1), a reference compressed data output means (13B), the correlated compressed data (D11) and the reference compressed data (D2).
A data operation output means (13C) for outputting the difference 1) as update data (DR); the update data (DR), the correlated compressed data (D11) and the reference compressed data (D
Data comparison and output means (13) for performing correlation processing based on (21)
D) and the first and second signals based on the reference signal (CLK).
And a data input / output control means (13E) for outputting the control signals (S1, S2). 2. A compression process is performed on the binary image pattern data (D1) of the correlated processing object (19), and the compressed correlated compressed data (D11) and the correlated processing object (1) are compressed.
9) In the correlation processing method for comparing and detecting the reference pattern data (D2) obtained by compressing the reference pattern data (D2) with the reference compressed data (D21), the comparison and detection processing includes n bits of correlated compressed data (D11) for each row. And n-bit reference compressed data (D21), the binary image logical value (0/1) of the most significant bit and the lower n-
A correlation processing method, wherein comparison and update processing is performed based on the same logical value (0/1) of one bit. 3. An image input / output means (14) for inputting / outputting image acquisition data (DIN) of an image acquisition target (20), and a binary image obtained by performing a binarization process on the image acquisition data (DIN). Signal processing means (1) for outputting pattern data (D1)
5), storage means (16) for storing the reference pattern data (D2) of the image acquisition target (20), the binary image pattern data (D1) and the reference pattern data (D
A correlation processing means (17) for performing correlation processing with 2) and outputting correlation result data (D3); and determination result data (Dout) based on the correlation result data (D3) and determination reference data (D4). And a correlation output means (18) for outputting the binary image pattern data (D) of the correlated processing target (19).
(1) a first data compression means (11) for outputting correlated compressed data (D11); and a reference pattern data (D2) for compressing the reference pattern data (D2) of the correlated processing target (19). D21), and compressed data correlation processing means (13) for performing correlation processing between the correlated compressed data (D11) and reference compressed data (D21). The compressed data correlation processing means (13) outputs the correlated compressed data (D11) based on the first control signal (S1).
A), reference compressed data output means (13B) for outputting the reference compressed data (D21) based on the second control signal (S2), the correlated compressed data (D11) and the reference compressed data (D21). And a correlation operation based on the data calculation output means (13C) for outputting the difference as the update data (DR) and the update data (DR), the correlated compressed data (D11) and the reference compressed data (D21). Data comparison and output means (13D) and data input / output control means (13E) for outputting the first and second control signals (S1, S2) based on a reference signal (CLK). Image processing device. 4. The image processing apparatus according to claim 3, wherein the storage means (16) stores the image processing target (2
An image processing apparatus which stores the compressed reference pattern data (D2) of (0).