JPH02156395A - Paper money discrimination device - Google Patents

Abstract

PURPOSE:To highly speedily discriminate a paper money with simple composition by executing picture processing using hardware composed of a RAM, a counter, a CPU, and a timing controller. CONSTITUTION:Data obtained by binarizing a picture signal to be obtained through an image pickup device with an arbitrary threshold are stored in a 1-bit RAM 1, the data are successively read out by a counter 2, and picture elements to indicate '1' are counted by the counter 2. The paper money can be discriminated according to the number of the picture elements to indicate '1'. A RAM 3 stores the arithmetic output of the counter 2, and a CPU 4 compares the output of the RAM 3 with various set levels and discriminates the classification of the paper money. A timing controller 5 generates a read out address for the 1-bit RAM, a clock for the counter 2, an a write signal and a write address for the RAM 3. The CPU 4 sets read out start addresses XS and YS and length W and L for the 1-bit RAM to the controller 5 and designates a range for calculating the number of the picture elements.

Description

[Detailed description of the invention] [Industrial application field] TECHNICAL FIELD This invention relates to a banknote validating device, and particularly to an improvement thereof.

[Conventional technology]

Conventional banknote discrimination often involves placing magnetic heads, optical sensors, etc. discretely at necessary locations, and utilizing their outputs.

[Problem to be solved by the invention]

In recent years, bill validators have been required to be more accurate, so conventional methods are no longer suitable, and highly accurate discrimination using two-dimensional images from image sensors or the like is now required.

By the way, processing a huge amount of two-dimensional data is not only a big burden in terms of cost, but also requires expensive elements such as digital signal processors (DSP) in the method of software processing analog data. Therefore, the reality is that inexpensive systems cannot adequately handle this problem.

On the other hand, converting images to 2fii data is easy enough to perform software processing, but this requires a large amount of processing time, so in fields where high speed is required, such as banknote identification, this is still a problem. That's enough.

Therefore, it is possible to consider a method of compressing the image data from the beginning, but it may be necessary to have the flexibility to change the view depending on the situation, such as roughly covering the parts that need to be used for banknote identification and looking more closely at the parts that do not. Therefore, it is not preferable to throw away data from the beginning, but rather to somehow retain the original data and compress the data at high speed using an appropriate method as needed.

Therefore, an object of the present invention is to provide a bill validating device that is inexpensive and capable of high-speed processing.

[Means to solve the problem]

a first storage means for storing a binarized image signal of a banknote imaged and converted into 2@; a counting means for counting #prime numbers of @1" sequentially read from the first storage means;
a second storage means for storing the count results; a discrimination means for performing discrimination based on the stored count results; and a discrimination means for specifying a readout area of the first memory means; A control means is provided for generating a read address for the first storage means, a clock signal for the counting means, a write signal for the second storage means, and a write address.

[Effect]

1st. By using the second storage means, counting means, discrimination means, and control means to form an I/D configuration, high-speed processing can be performed even in software processing.

〔Example〕

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is an explanatory diagram for explaining the calculation range of image data.

In FIG. 1, 1 is a RAM (random access memory), 2 is a counter, and 6 is a RAM.

4 is a data processing device (CPU), and 5 is a timing control device. The timing control device 5 includes address generation circuits 51 and 55, a counter clock generation circuit 52, an operation result write signal generation circuit 53, a timing generation circuit 55, and the like.

1) RAMIK stores data obtained by converting an image signal obtained through an imaging device into a binary signal at an appropriate threshold level. The counter 2 counts the number of pixels indicating "1" among the pixel data sequentially read out from the RAM 1. This is based on the fact that the type of banknote to be read can be identified (identified) by the number of pixels of ``1'' in the binarized image. The RAM 3 stores the cumulative output from the counter 2, and the CPU 4 compares the output of the RAM 5 with various set levels to discriminate the type of banknote. The timing control device 5 generates successive (read) addresses for RAM1, generates a counter clock for counter 2, and writes for RAM3.
Generates signals and write addresses, etc. In addition, C.P.
U4 is one pin) RA for this timing control device 5.
M1 origin address (successive start address) X8. It is possible to specify the pixel count range (calculation range) by setting Ys and the length (W, L) in the X and Y directions. This situation is shown in FIG. Here, the shaded area indicates the calculation range, and it is also possible to specify the entire range.

FIG. 3 is a circuit diagram showing a specific example of the timing control device. In the figure, 1 is 1 bit) RAM.

2A, 2B, 12A, 12B are counters, 11A to 11
g is an input/output device i (ilo), 13A to 13C are delay circuits, and 14A and 14B are comparators.

The X-direction read operation in FIG. 3 will be explained with reference to FIG. 4A.

The origin address (X8°Ys
) is loaded into the presettable counters 12A and 12B by the load signal generated by the calculation start signal received from the CPU 4, and this is connected to the address line of the RAM 1 set to read mode. Therefore, the address (X
8. The data of Y8) is output (see point ■).

In addition, two clocks (address clock, counter clock) with the same period but different phases and duties cause the "1#" bit output from the 1-bit RAM 1 to be counted up by the counter 2A, and immediately after that, the KX address is incremented by one. By repeating this operation,
The number of pixels in the direction @1″ bit will be counted.

FIG. 4B is a time chart for explaining the X-direction read operation of FIG. 3.

In other words, the address in the X direction is updated.

+W, the comparator 14A outputs the signal X(A
-B) is output, and after one bit of (X + W, Y8) is counted, the KX address is reset to X8, while
Address Y8 is updated to Ys11, (X, Y8
+1), counting starts again using the same time chart as in FIG. 3A.

FIG. 4C is a time chart for explaining the write operation of FIG. 6.

The operations in Figures 4A and 4B are repeated and the Y address is also Ys.
When the signal Y (A-B
) is output. And the address is (X8+W, Y8
+L), the comparators 14A and 14B output signals X(A-B) respectively.

Y(A-B) is output. This timing (see ■)
When the write address is advanced by one, the delay circuit 13
A write signal is issued via C to write the calculation result to the RAM 3, and a calculation end signal is output to end the series of calculations.

In the above, RAM1.3 and counter 2 are each set to 1.
However, by providing a plurality of these as shown in Figure 5, multiple binarized data can be processed at the same time, making it possible to process Okawa's image data at high speed. Become.

〔Effect of the invention〕

According to the present invention, since image data is processed using hardware consisting of a RAM, a counter, a CPU, and a timing control device, there is an advantage that high-speed processing is possible with a relatively simple configuration.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is an explanatory diagram for explaining the calculation range of image data, FIG. 6 is a circuit diagram showing a specific example of a timing control device, and FIG. 4A is a diagram showing a specific example of the timing control device. FIG. 4B is a time chart for explaining the X-direction read operation in FIG. 3, FIG. 4C is a time chart for explaining the X-direction read operation in FIG. 3, and FIG. 4C is for explaining the write operation in FIG. 3. FIG. 5 is a schematic diagram showing another embodiment of the present invention. Code explanation 1...1 bit RAM, 2, 2A, 2B, 12
A, 12B...Counter, 3...RA
M, 4... CPU, 5... Timing control device, 11A to 11E... Input/output device (i
lo), 1! IA ~13C...MtlLol
L 14A, 14B...Comparator, 51.
53...Address generation circuit, 52...
Counter clock generation circuit, 54...Arithmetic result write signal generation circuit, 55...Timing generation circuit. Agent Patent attorney Akio Namiki Agent Patent attorney Kiyoshi Matsuzaki wE I Figure 1f2 Zugashiki 8 Kau Toraguchi Shuu 5 Figure @JCIII+ waA Figure O ΔB Illustration IIn double 222 ==] =:== ===r==: Lotus 5 Figure

Claims (1)

[Claims] A first storage means for storing a binarized image signal of a banknote that has been imaged and binarized, and a counter for counting the number of "1" pixels sequentially read from the first storage means. a second storage means for storing the count result; a discrimination means for performing discrimination based on the stored count result and specifying a reading area of the first memory means; Based on at least the first
A bill validating device comprising: control means for generating a read address for a storage means, a clock signal for the counting means, a write signal for the second storage means, and a write address.