JP3008597B2 - Step-up DC-DC converter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a switched-capacitor DC-DC converter for converting an input voltage to a required output voltage by turning on and off a switch, and more particularly, to a boost type in which the input voltage is lower than the drive voltage of a MOS transistor. The present invention relates to a switched capacitor DC-DC converter.

[0002]

2. Description of the Related Art A switched capacitor DC-DC in which an output capacitor and a MOS transistor for controlling the terminal voltage of the output capacitor are connected in series to a DC power supply.
The converter is divided into two types, a step-down type and a step-up type.

FIG. 2 is a circuit diagram showing a basic configuration of a boost type switched capacitor DC-DC converter disclosed in Japanese Patent Application No. 2-167801 filed by the applicant of the present invention. In FIG. 1, a series circuit of a _first switch S ₁ , a capacitor C _1, and a second reactor L ₂ is connected in parallel to a DC power supply E, and a second switch S ₂ is connected to the first switch S 1.
Is connection in parallel with the series circuit of the switch S ₁ and the capacitor C _1. A series circuit of the first reactor L ₁ and the output capacitor C _O is connected in parallel to a series circuit of the capacitor C ₁ and the second reactor L _2, and a load R _L is connected in parallel with the output capacitor C _O. Is connected.

In this circuit, when the first switch S ₁ and the second switch S ₂ are turned on and off in an anti-phase relationship,
That is, the first switch S ₁ is a second switch S ₂ is turned off when on, first when the first switch S ₁ is off 2
When the first and second switches S ₁ and S ₂ are operated such that the switch S ₂ is turned on, the ratio between the output voltage D _out and the input voltage D _in of the DC-DC converter becomes the time ratio d. ,
That is, it is expressed as follows using the ratio of the off period T _OFF to the on / off period T of the switch S ₂ .

[0005] _{D out / D in = T OFF} / T = / (1-d) Therefore, by the set to any value from 0 to 1 when the ratio d, D _out a D _in more arbitrary value Can be increased.

The actual step-up type switched capacitor type DC-DC converter further includes a control circuit SC for stabilizing the output voltage, and has, for example, a circuit configuration shown in FIG. In the figure, a diode D ₁ is used as a _first switch S ₁ , and a P-channel MOS transistor TR is used as a _second switch S ₂ . In the control circuit SC, the output voltage V _out is _divided by two series resistors r ₁ and r ₂ , and the divided voltage V is compared with a reference voltage V _R by a comparator CP. the voltage V _D of the difference between the reference voltage V _R is made, is input to one input terminal T ₁ of the pulse width modulation circuit PM. The pulse modulation circuit another input terminal T ₂ of the PM, the input voltage V _in is supplied. Thus, the pulse modulation circuit PM includes a series of positive pulse voltage (Fig. 3 see B) output terminals T ₃ and having a height corresponding to the input voltage V _in has a width corresponding to the differential voltage V _D outputs from and added to the gate of the MOS transistor TR this through protective resistor r _3. Thus, a period in which a positive pulse is applied to the gate of the MOS transistor TR, MOS transistor TR is turned off, the diode D ₁ is turned on.

Accordingly, by appropriately selecting the ratio between the resistance r ₁ and the resistance r ₂ and controlling the gate voltage of the MOS transistor TR with the difference voltage V _D according to the selection to maintain the duty ratio at a predetermined value, The voltage V _out can be held at a required value. Also, by changing the ratio of the resistors r ₁ and r ₂ or the reference voltage V _R , and thus the difference voltage V _D , the output voltage V _out can be changed.

[0008] In FIG. 4, the driving voltage V _GS of the P-channel MOS transistor TR is substantially equal to the input voltage V _in, also decreases the driving voltage V _GS of the MOS transistor when the input voltage V _in is decreased, P-channel MOS The ON resistance between the drain and the source of the transistor TR increases, and the MOS transistor TR generates heat. In other words, when the input voltage V _in is decreased, MOS transistors T
R generates heat, which causes a reduction in the efficiency of the entire DC-DC converter. Indeed, 2V in the circuit of FIG. 3, the output voltage V _out and 12V, the input voltage V _in
Was varied from 7V from, the drive voltage V _GS of the MOS transistor TR and V _in is smaller than 4V is not sufficient, MOS transistor TR has been confirmed that the heat.

[0009]

Therefore, in such a boosted switched capacitor DC-DC converter, the gate of the P-channel MOS transistor is
It was desired to elucidate how to provide a controlled voltage.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problem. Even when the voltage supplied from the DC power supply is low, the efficiency of the step-up type DC-DC converter is stable without decreasing the efficiency.
An object is to provide a DC converter.

[0011]

In order to achieve the above object, a boost DC-DC converter according to the present invention comprises:
Means for connecting at least one switch with a MOS transistor and connecting to a DC power supply, at least one reactor for storing energy from the DC power supply during a period in which the MOS transistor is on, and a DC power supply via the reactor and the MOS transistor; An output capacitor that is connected and supplies a current to a load, and a pulse width modulation circuit that receives a voltage corresponding to the output voltage of the output capacitor and applies a pulse of a required time ratio to the gate of the MOS transistor. Have. This step-up DC-
The DC converter further includes ground potential lowering means for lowering the ground potential of the pulse width modulation circuit by using a negative potential generated in the reactor while the MOS transistor is off. Thus, the pulse width modulation circuit generates a potential difference larger than the output potential difference of the DC power supply, and applies a pulse having a height corresponding to the potential difference to the gate of the MOS transistor.

In one embodiment of the present invention, a boost type D
The C-DC converter comprises a means for connecting to a DC power supply and a first
And a circuit in which a switch, a second reactor, and an output capacitor are connected in series in this order, and a circuit in which a first capacitor and a first reactor are connected in series.
A circuit connected in parallel to a series circuit of the reactor and the output capacitor, a load connected in parallel to the output capacitor, and a circuit connected in parallel to a series circuit of the first switch and the first capacitor A second switch, and a pulse width modulation circuit to which a voltage corresponding to the output voltage of the output capacitor is input and for applying a pulse of a required duty ratio to the second switch, using a MOS transistor as the second switch Then, energy is stored in the first reactor while the MOS transistor is on.

The DC-DC converter according to this embodiment has an M
Ground potential lowering means is provided for receiving and utilizing energy stored in the first reactor while the OS transistor is off to lower the ground potential of the pulse width modulation circuit by a predetermined voltage. The pulse width modulation circuit outputs a pulse having a height corresponding to the sum of the predetermined voltage and the output voltage of the DC power supply to the MOS.
It can be added to the gate of a transistor.

The ground potential lowering means connects a series circuit of an additional capacitor and a rectifier diode in parallel to the first reactor, and connects a connection point between the additional capacitor and the rectifier diode to a ground terminal of the pulse modulation circuit. It may be constituted by the following.

[0015]

In the step-up DC-DC converter according to the present invention, while the MOS transistor is off, the ground potential of the pulse width modulation circuit is reduced equivalently by utilizing energy accumulated in the first reactor, As a result, the pulse width modulation circuit generates a voltage higher than the voltage of the DC power supply, and a pulse having a height corresponding to this voltage is applied to the MOS transistor. Therefore, even if the input voltage decreases, the MOS transistor does not generate heat and the step-up DC-DC
The converter operates with high efficiency and stability.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, an embodiment of a boost type switched capacitor DC-DC converter according to the present invention will be described in detail with reference to FIG. As is clear from FIG. 1A, this step-up DC-DC converter is the DC-DC converter of FIG.
Further with respect to the converter, as well as connecting the additional capacitor C ₂ between the ground terminal G of the negative terminal (ground level) and pulse width modulation circuit PM of the DC power source E, a first reactor L ₁ and the capacitor C ₁ and connecting the cathode of the rectifier diode D ₂ to the connection point, it is obtained so as to connect the anode to the ground terminal G of the pulse width modulation circuit PM.

Next, the operation of the step-up DC-DC converter shown in FIG. 1 will be described. P-channel MOS transistor T
When R is turned on, the first reactor L ₁ is connected to the DC power supply E
Accumulates energy. On the other hand, the capacitor C ₁ is connected to the DC power supply E through the turned-on MOS transistor TR.
And connected in series to discharge. The energy by energy and discharge of the capacitor C ₁ of the DC power source E is supplied to the second reactor L ₂ and the output capacitor C _0, charging the output capacitor C _0.

On the other hand, a P-channel MOS transistor T
When R is turned off, the diode D ₁ is turned on, and the first reactor L ₁ is connected in series with the DC power supply E, so that the energy stored there is discharged through the diode D _1. It has been to charge the capacitor C _1. The second reactor L ₂ is connected in series with the DC power source E via the diode D _1, charging the output capacitor C _0.

[0019] MOS transistor TR is the period of off, since the first reactor L ₁ is the counter electromotive force generated, the connection point between the first reactor L ₁ and capacitor C ₁ becomes a negative potential. Therefore, MOS transistor TR
There the first energy stored in the reactor L ₁ during the period of the on, additional capacitor C ₂ MOS transistors TR is charged via the rectifier diode D2 to the period off. As a result, the potential of the ground terminal G of the pulse width modulation circuit PM becomes lower than the ground potential by the voltage V _C2 across the capacitor C ₂ . That is, the capacitor C ₂ and the diode D ₂ constitute the ground potential lowering means EP.

Thus, when the P-channel MOS transistor TR is on, part of the energy stored in the first reactor L ₁ is transferred to the additional capacitor C via the rectifying diode D ₂ when the MOS transistor TR is off. by accumulating in _2, the pulse width modulation circuit PM is enabled to utilize a voltage of the sum of the input voltage V _in and the voltage V _C2 across the additional capacitor C _2. Therefore, the pulse width modulation circuit PM adds a pulse of height corresponding to the voltage of the sum (see B in FIG. 1) as the drive voltage V _GS at the gate of the MOS transistor TR.

[0021] Therefore, the input voltage V _in is also reduced,
The gate of the MOS transistor TR is the height of the pulses corresponding to the voltage of the sum of the voltage V _C2 of the additional capacitor and the input voltage V _in is supplied, the step-up in this embodiment DC-
In the DC converter, an increase in the on-resistance of the MOS transistor TR is prevented, and the DC converter is less likely to generate heat and can operate stably with high efficiency as compared with the conventional one.

[0022] In fact, in the step-up DC-DC converter of FIG. 1, where the output voltage V _out is set to 12V, and the input voltage is changed from 2V to 7V, the input voltage V _in
Was reduced to 2 V, no heat was generated in the MOS transistor TR. This indicates that the boost DC-DC converter according to the present invention maintains stable and efficient operation even when the input voltage decreases.

[0023]

As described above, the means for lowering the ground potential of the pulse generation modulation circuit using the reverse electromotive force generated by the first reactor during the period when the MOS transistor is off is provided. The circuit can generate a voltage higher than the voltage of the DC power supply, and a pulse having a height corresponding to this voltage can be used as a drive voltage of the MOS transistor. Therefore, even when the input voltage decreases, heat generation of the MOS transistor can be avoided, and the step-up DC-DC converter can be operated stably and with high efficiency.

[Brief description of the drawings]

FIG. 1A is a diagram showing a configuration of an embodiment of a step-up switched capacitor DC-DC converter according to the present invention, and FIG. 1B is a diagram showing a waveform of a pulse applied to a gate of a MOS transistor; .

FIG. 2 is a diagram for explaining the operation principle of the boosted switched capacitor DC-DC converter according to the earlier application.

FIG. 3A shows the boosted switched capacitor D of FIG. 2;
It is a figure which shows the example of a circuit which actualized the C-DC converter, and B is a figure which shows the waveform of the pulse applied to the gate of a MOS transistor.

[Explanation of symbols]

L ₁ : first reactor L ₂ : second reactor C ₀ : output capacitor C ₂ : additional capacitor D ₁ : diode (first switch) D ₂ : rectifying diode PM: pulse width modulation circuit SC: control Circuit TR: MOS transistor (second switch) EP: means for lowering ground potential

Claims (3)

(57) [Claims] A means for connecting at least one switch with a MOS transistor to a DC power supply;
At least one reactor for storing energy from the DC power supply during an ON period of an OS transistor; an output capacitor connected to the DC power supply via the reactor and the MOS transistor to supply current to a load; A voltage corresponding to the output voltage of the output capacitor is input, and a pulse having a required duty ratio is generated by the MOS.
A step-up DC-DC converter including at least a pulse width modulation circuit added to a gate of a transistor, wherein the pulse width modulation circuit is grounded by utilizing a negative potential generated in the reactor while the MOS transistor is off. Ground potential lowering means for lowering the potential, the ground potential lowering means enables the pulse width modulation circuit to make a potential difference larger than the potential difference of the DC power supply equivalently, and a height corresponding to this potential difference A step-up DC-DC converter, wherein a pulse is applied to the MOS transistor. 2. A means for connecting to a DC power supply, a series circuit in which a first switch, a second reactor and an output capacitor are connected in this order, and a first capacitor and a first reactor connected in series. A circuit connected in parallel to a series circuit of the second reactor and the output capacitor; a load connected in parallel to the output capacitor; the first switch and the first switch; A second switch connected in parallel to a series circuit with a capacitor, and a voltage corresponding to an output voltage of the output capacitor, and a pulse width modulation for applying a pulse of a required time ratio to the second switch. A MOS transistor is used as the second switch, such that the MOS transistor stores energy in the first reactor during an ON period. In the step-up DC-DC converter, while the MOS transistor is turned off, receiving and utilizing energy accumulated in the first reactor, the ground potential lowering means for lowering the ground potential of the pulse width modulation circuit by a predetermined voltage. Wherein the pulse width modulation circuit applies a pulse having a height corresponding to the sum of the predetermined voltage and the output voltage of the DC power supply to the gate of the MOS transistor. DC converter. 3. The ground potential lowering means includes a series circuit of an additional capacitor and a rectifying diode, the series circuit being connected in parallel to the first reactor, and connecting the additional capacitor and the rectifying diode. 2. A point is connected to a ground terminal of said pulse modulation circuit.
Or the step-up DC-DC converter according to 2.