JP3006302B2 - High-speed playback device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high-speed reproducing apparatus used for digital magnetic recording of PCM signals.

[0002]

2. Description of the Related Art In recent years, devices for performing high-density digital magnetic recording such as a DAT (Digital Audio Tape Recorder) have appeared on the world. When such digital data is recorded, additional information such as a heading and position information synchronized with the recorded data is recorded, and advanced cueing is performed at the time of reproduction using the additional information. The method has been put to practical use. Since the amount of the additional information is smaller than that of normal data, the additional information may be recorded in a specific small area or may be recorded at a low frequency with a reduced recording density. A high-speed reproducing apparatus has been devised in which only the additional information is reproduced to find a necessary data portion at a higher speed than normal reproduction.

[0003] A conventional high-speed reproducing apparatus will be described below. FIG. 5 is a block diagram of a conventional high-speed reproducing apparatus.
5, 1 is a recording medium, 2 is a reproduction amplifier, 3 is main data, 4 is additional data, 5 is an equalizing filter for signal main data, 6 is an equalizing filter for additional data, 7 is a signal processing unit, 8 Is an output terminal, and 9 is a speed setting circuit.

The operation will be described below with reference to FIG. On the recording medium 1, main data and additional data are recorded in different areas in a time-division manner or on separate recording tracks. These signals are amplified by the reproduction amplifier 2 and output separately from the main data signal 3 and the additional data signal 4. The main data signal 3 is input to the equalization filter 5 corresponding to the main data, compensates for waveform distortion generated by the recording characteristics of the recording medium 1, and is output to the signal processing unit 7. Similarly, the additional data signal 4 is input to the equalization filter 6 corresponding to the additional data, and undergoes compensation for waveform distortion. This output is output to the signal processing unit 7. The signal processing unit 7 performs demodulation processing of the input data,
The data or additional information is reproduced, and is output from the output terminal 8 to the outside.

At the time of high-speed reproduction, the moving speed of the recording medium, the characteristics of the equalizing filter 6, the signal processing unit 7
By outputting a switching signal to the recording medium 1 and moving the recording medium 1 at a high speed, data can be read at a high speed. In this case, only the additional information recorded at a relatively low frequency is reproduced. The high-speed additional data output from the reproducing amplifier 2 is compensated for waveform distortion by an equalizing filter 6 that is switched according to the moving speed of the recording medium 1, and then output to the signal processing unit 7. The signal processing unit 7 reproduces the additional information data, detects a cue signal, for example, and uses it for high-speed access to main data.

FIG. 6A is a block diagram of the equalizing filter 5 or 6, and FIG. 6B is an operation explanatory diagram. FIG.
1A, reference numeral 10 denotes an input terminal, 11 to 16 denote delay elements, 20 to 26 denote multiplication circuits, 30 denotes an addition circuit,
1 is an output terminal. Here, the order of the filter is set to 7. Hereinafter, the operation of the equalization filter will be described with reference to FIG.

The signal input to the input terminal 10 is input to a first delay element 11 and a first coefficient circuit 20, and the output of the first delay element 11 is output to a second delay element 12 and a second coefficient circuit. Input to the circuit 21. Similarly, the third, fourth, fifth,
The signal is input to the sixth delay element and the coefficient circuit, and is finally input to the seventh coefficient circuit 26. Each coefficient circuit multiplies the coefficient by an appropriate coefficient that determines the characteristics of the filter and outputs the result. The sum is simultaneously input to the addition circuit 30, and the sum of a total of seven signals is output to the output terminal 31.

FIG. 6B is an explanatory timing chart when the filter of FIG. 6A is constituted by a digital filter. In FIG. 6B, 41 is an input timing signal of input data, 42 is an output of the adder circuit 30, and 43 is an output signal of the filter. In the processing, multiplication and addition are considered as one unit, and this operation is repeated a plurality of times to finally realize the filter processing. By adopting this method, the number of multiplication circuits having a large circuit scale is reduced.

At the rising edge of the input timing signal 41,
When the input data and the output of each delay element are determined, first, the input data is multiplied by the first coefficient in the first coefficient circuit 20 and output to the adding circuit 30. This output result is represented by 1 in the drawing of the signal 42. Next, the output of the first delay element 11 is multiplied by a second coefficient by a second coefficient circuit 21 and the output is sent to an addition circuit 30. The addition circuit 30 compares the output of the first coefficient circuit 20 with the second coefficient. Are added and the result is held. This result is represented by 2 in the figure of the signal 42. Similarly, the output of the third coefficient circuit 22 and the output of the addition circuit 30 held last time are further added. If this process is repeated several times in the order of the filter, that is, seven times in this case, the output of the adder circuit 30 is the output of the filter. The signal holding this output becomes 43 and is output to the output terminal 31.

[0010]

However, in the above-described conventional circuit configuration, there is no problem when reproducing at a normal speed, but in a high-speed reproducing state, the frequency of the reproduced signal is proportional to the tape speed. As a result, the operation speed of the filter unit cannot be kept in time, which causes a problem in increasing the reproduction speed.

In view of the above problems, it is an object of the present invention to provide a high-speed reproducing apparatus capable of reading data almost accurately even when the reproducing speed is increased.

[0012]

In order to achieve the above object, a high-speed reproducing apparatus according to the present invention comprises: means for sampling a reproduced signal from a recording medium; a digital filter for processing sampled data; And control means for setting the speed, and at the time of high-speed reproduction, the sampling period is changed in accordance with the reproduction speed, and the signal is reproduced by reducing the order of the digital filter.

[0013] Further, with respect to a reproduction signal composed of a plurality of channels, the number of channels to be sampled during high-speed reproduction is reduced.

[0014]

[0015]

According to the present invention, the number of times of the product-sum calculation of the digital filter is reduced and the calculation time is shortened by reducing the order of the filter by the above configuration.

In addition, the required number of calculations is reduced by reducing the number of channels to be calculated, and the calculation time can be shortened.

As a result, even if the frequency of the input signal is increased, the operation of the filter can be performed in time, and high-speed data reproduction becomes possible.

[0018]

[0019]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a high-speed reproducing apparatus according to a first embodiment of the present invention. In FIG. 1, a sampling circuit 101 samples an output of the reproduction amplifier 2 by a sampling clock 105 from a signal processing unit 103 and outputs the sampled signal to a digital filter 102. The digital filter 102 filters the characteristic specified by the order setting circuit 104 and outputs a signal whose distortion has been corrected to the signal processing unit 103. Order setting circuit 10
4 selects the order corresponding to the command from the speed setting circuit 9 to determine the characteristics of the digital filter 102.

The operation of the high-speed reproducing apparatus of the present embodiment configured as described above will be described below. The same parts as those in the conventional example are denoted by the same reference numerals, and description thereof will be omitted.

First, consider the case where normal reproduction is performed. When the recording medium 1 is moved at the speed determined by the speed setting circuit 9, the recorded signal is reproduced at a normal reproduction frequency, and the signal amplified to an appropriate amplitude by the reproduction amplifier 2 is input to the sampling circuit 101. Is done. The sampling frequency corresponds to a command from the speed setting circuit 9, and the signal processing unit 103 supplies a sampling clock 105 for normal reproduction to the sampling circuit 101. Sampling circuit 1
At 01, the input signal is sampled at a given sampling clock and output to the digital filter 102.
At this time, even when the input signal includes signals of a plurality of channels such as a main signal and additional information, it is possible to collectively sample these signals in a time-division manner. The sampling circuit 101 has a general A /
It can be easily configured with a D converter.

The digital filter 102 filters a reproduced signal in synchronization with the sampling clock 105. Since the setting signal from the order setting circuit 104 has the same seventh order as that of the conventional example at the time of normal reproduction, the same configuration as that of FIG.
03 is output. The main part and additional information are processed in a time-division manner.

The signal processor 103 separates the output of the digital filter 102 into a main part and additional information, performs processing, reproduces each data, and outputs the data to the output terminal 8.

In the case of the high-speed reproduction mode, a speed setting command is issued from the speed setting circuit 9 to increase the moving speed of the recording medium 1, and the sampling clock 105 output from the signal processing unit 103 corresponding thereto. The frequency is also set higher.

FIG. 2 is an explanatory diagram for explaining the operation of the digital filter 102 in the high-speed mode. In FIG. 2A, 10 is an input terminal, 111 and 112 are delay elements,
120 to 123 are counting circuits, 130 is an adding circuit, and 31 is an output terminal. In FIG. 2B, 141 is an input data timing signal, 142 is a coefficient circuit output,
Reference numeral 42 denotes a filter output. Hereinafter, the operation of the digital filter 102 will be described with reference to FIG.

In accordance with the speed setting command, the order setting circuit 104 sets the order of the filter by limiting the order to a range where the operation speed of the digital filter 102 can be in time.
For example, when the speed is four times the normal speed, the sampling clock 105 is also set to four times the normal speed. In response, the order setting circuit 104 sets the order of the filter to 3 as shown in FIG. In this case, the input signal and the calculation of the coefficient circuit 120, the output of the delay element 111 and the calculation of the coefficient circuit 121, and the calculation of the addition circuit 130, the output of the delay element 112 and the calculation of the coefficient circuit 123, and the addition circuit 13
Three steps of calculation of 0 are required. Each of the above is represented by 1, 2, and 3 in the waveform 142 of FIG. Considering the total calculation time, since the input data timing 141 has a frequency that is four times the normal frequency,
The calculation time of this filter is 1/4 * 7/3 =, where 1 is the normal time.
7/12, which is about 1 / 1.7 times the calculation time. Therefore, if the operation speed of the filter circuit is designed to move at a speed of 1.7 times, a signal can be reproduced at a speed of 4 times. By reducing the order of the filter, the characteristics of the filter may slightly deviate from the required characteristics. However, in the worst case, the error check circuit included in the signal processing circuit 103 can perform correction or correction processing. No major problems arise.

As described above, according to the present embodiment, by providing the order setting circuit for controlling the order of the filter in accordance with the reproduction speed, it is possible to operate the filter normally at the time of high-speed reproduction. Data can be reproduced at high speed.

FIG. 3 is a block diagram of a high-speed reproducing apparatus according to a second embodiment of the present invention. In the figure, reference numeral 201 denotes a recording medium on which signals of a plurality of channels are recorded;
Represents a reproduction amplifier circuit corresponding to the plurality of channels;
3 is a sampling circuit, 204 is an equalization filter, 205
Is an order setting circuit of the equalization filter 204, 206 is a signal processing unit, 207 is a sampling clock, 8 is an output terminal,
Reference numeral 9 denotes a speed setting circuit, which differs from FIG. 1 in that the sampling circuit 203 is provided with a function of receiving a command from the speed setting circuit 9 and limiting the sampling channel.

The operation of the high-speed reproducing apparatus of the present embodiment configured as described above will be described below.

In the high-speed reproduction mode, it is often not necessary to reproduce all information recorded on the recording medium.
For example, as long as a signal necessary for cueing can be read, it is only necessary to switch to a normal reproduction mode from that point and reproduce all information.

In the high-speed reproduction mode, signals of a plurality of channels reproduced from the recording medium 201 are supplied to the reproduction amplifier circuit 20.
2 and is input to the sampling circuit 203.
When the speed is eight times the normal speed, the sampling circuit 203 performs sampling by selecting two of the four input channels according to a command from the speed setting circuit 9. If a channel is selected so that the cue signal is included in these two channels, necessary information can be reproduced only by the selected channel. The signal sampled in this manner has a data amount that is half of that when all the channels are sampled, and is output to the equalization filter 204 in the same data cycle as in the first embodiment. As in the first embodiment, the equalization filter 204 filters the input signal in accordance with a command from the order setting circuit 205 and performs signal filtering on the signal.
Output to The signal processing unit 206 generates a necessary sampling clock 207 according to a command from the speed setting circuit 9, reproduces a necessary cue signal or data from an output signal of the equalization filter 204, and outputs the reproduced signal to the output terminal 8.

As described above, according to the present embodiment, by providing the sampling circuit 203 for reducing the number of channels to be sampled at the time of high-speed reproduction with respect to the reproduction signal composed of a plurality of channels, in this case, it is increased by eight times. Thus, data can be reproduced at a higher speed. In addition,
In the second embodiment, the order setting circuit 205 is provided in combination with the first embodiment. However, in a simple manner, the same configuration as that in the normal reproduction without changing the order of the equalization filter 204 is adopted. Can also.

FIG. 4 is a block diagram showing a high-speed reproducing apparatus according to a third embodiment of the present invention. In the figure, 301 is a recording medium on which a signal is recorded, 302 is a reproduction amplifier circuit,
303 is a sampling circuit, 304 is a storage circuit, 305
1 is an equalization filter, 306 is a signal processing unit, 307 is a sampling clock, 308 is a permission signal, 309 is an order setting circuit of the equalization filter 305, 8 is an output terminal, and 9 is a speed setting circuit. The storage circuit 304 is provided at the subsequent stage of the sampling circuit 303, and a function of controlling reading / writing of the storage circuit 304 by a permission signal 308 from the signal processing unit 306 is provided.

The operation of the high-speed reproducing apparatus of the present embodiment configured as described above will be described below.

When data is recorded on a recording medium,
A method of dividing recorded data into an appropriate size and treating the divided data as one block is often used. Therefore, even in the case of high-speed reproduction, there may be a case where it is sufficient if a specific block can be read in units of this one block. For example, if the table of contents information is written once in each block, the current position can be recognized by reading this information, and the data can be read out by reading the recording medium at the required position by normal reproduction.

In the high-speed reproduction mode, the signal reproduced from the recording medium 301 is amplified by the reproduction amplification circuit 302 and input to the sampling circuit 303. In the sampling circuit 303, the signal is sampled by the sampling clock 307 and output to the storage circuit 304. The storage circuit 304 has a capacity larger than one block of the recorded signal, and stores the input data according to the write enable signal 308 from the signal processing unit 306. The signal once stored can be read out relatively freely, so that the stored signal can be read out at the same speed as during normal reproduction, for example.
In this case, the order setting circuit 309 does not affect the operation of the system, but if it is desired to further shorten the cycle of writing data to the storage circuit 304, the order can be reduced to perform high-speed data reproduction.

The reproduced data read at a relatively low frequency in this manner is compensated for waveform distortion by the equalizing filter 305 in the same manner as in normal reproduction, and output to the signal processing unit 306. The signal processing unit 306 generates an appropriate sampling clock in accordance with a command from the speed setting circuit 9, performs processing in units of one block of input data, and reproduces necessary table of contents information and main recording data. , To the output terminal 8. At this time, at the stage where the data required by the signal processing unit 306 has been read, a permission signal 308 giving permission to write the next reproduced data to the storage circuit 304 is output to the storage circuit 304.

In general, the moving speed of the storage medium at the time of high-speed reproduction is not so accurate.
It is desirable that the capacity of 04 is about 2 blocks + α.

As described above, according to this embodiment, data is stored in the storage circuit at a high speed at the operation speed of the storage circuit capable of operating at a relatively high speed, and the stored signal is stored at a relatively low speed. Processing can be performed by the signal processing unit, and intermittent but extremely high-speed data reproduction becomes possible.
Further, the reading speed from the storage circuit 304 can be increased to the lower limit of the maximum operation speed of the signal processing unit 306 and the equalization filter 305, and the order of the filter is operated by operating the order selection circuit 309 of the filter. Increasing the operating speed of the filter 305 by lowering it means increasing the frequency of reproducing the intermittent data, thereby improving the reliability of the reproduced data.

[0041]

As described above, the present invention comprises means for sampling a reproduction signal from a recording medium, a digital filter for processing sampled data, and control means for setting a reproduction speed. Since the signal is reproduced by changing the sampling period in accordance with the reproduction speed and reducing the order of the digital filter, the reproduction signal comprising a plurality of channels is further sampled during high-speed reproduction. Since the configuration is such that the number of channels is reduced, the operation speed of the filter unit can be increased, and high-speed data reproduction becomes possible.

[0042]

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a high-speed playback device according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing an internal configuration of an equalization filter unit according to the first embodiment, and waveform diagrams for explaining the operation thereof;

FIG. 3 is a block diagram showing a configuration of a high-speed playback device according to a second embodiment of the present invention.

FIG. 4 is a block diagram showing a configuration of a high-speed playback device according to a third embodiment of the present invention.

FIG. 5 is a block diagram showing a configuration of a conventional high-speed playback device.

FIG. 6 is a block diagram showing an internal configuration of an equalization filter unit in the conventional example and a waveform diagram for explaining the operation thereof;

[Explanation of symbols]

 1, 201, 301 Recording medium 2, 202, 302 Reproduction amplification circuit 103, 206, 306 Signal processing unit 8 Output terminal 9 Speed setting circuit 10 Input terminal of filter 111, 112 Delay element 120-122 Coefficient circuit 130 Addition circuit 31 Filter Output terminals 101, 203, 303 Sampling circuits 102, 204, 305 Digital filters 104, 205, 309 Order setting circuit 304 Storage circuit

Claims (2)

(57) [Claims] 1. A system comprising: means for sampling a reproduction signal from a recording medium; a digital filter for processing sampled data; and control means for setting a reproduction speed. A high-speed reproducing apparatus that reproduces a reproduced signal by reducing the order of the digital filter. 2. The high-speed reproducing apparatus according to claim 1, wherein the number of channels to be sampled at the time of high-speed reproduction is reduced for a reproduction signal including a plurality of channels.