JP3006133B2 - Inrush current prevention circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an inrush current prevention circuit, and more particularly to an inrush current prevention circuit for preventing a sudden change in current of a CMOS circuit when an input clock is cut off.

[0002]

2. Description of the Related Art A conventional C which operates by an input clock.
In an electric circuit having a MOS circuit, as shown in FIG.
The input clock signal 101 is directly input to the CMOS circuit 5, and the clock disconnection detection circuit 6 detects the clock disconnection, and prevents a sudden current fluctuation in the CMOS circuit 5 when the clock disconnection is restored. Do not have.

[0003]

As described above, in a conventional electric circuit having a CMOS circuit operated by an input clock, the current consumption of the CMOS circuit 5 is proportional to the frequency of the input clock (the frequency of a change point). There is a problem that a sudden current fluctuation occurs at the time of recovery from the input clock interruption and the power supply voltage drops instantaneously. This problem is particularly remarkable when used for high-speed clock input, and it is necessary to increase the load fluctuation tolerance of the output of the power supply circuit as the clock speed increases.

[0004]

The inrush current prevention circuit according to the present invention is inserted in a path for leading an input clock to a CMOS circuit, and outputs a pseudo clock whose frequency increases with time after input clock recovery from a cut. A clock generation circuit, a timing circuit that outputs a timing signal controlled by input clock disconnection information and controls a selection time of the pseudo clock, and selects the input clock and the pseudo clock in response to the timing signal Said C
And a clock selection circuit for outputting to the MOS circuit.

[0005]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention. In FIG. 1, reference numeral 1 denotes an inrush current prevention circuit, which comprises a pseudo clock generation circuit 2, a timing circuit 3, and a clock selection circuit (SEL) 4. When the clock (CLK) input signal 101 is cut off, the clock cutoff detection circuit 6 detects the clock cutoff, and the input clock cutoff signal 102 is input to the pseudo clock generation circuit 2 and the timing circuit 3. As shown in FIG. 2, the pseudo clock generation circuit 2 outputs the input clock cutoff signal 1
A pseudo clock signal 104 whose frequency changes from the frequency 0 to the frequency f _{0 of the} input clock during the elapse of the time T3 in synchronization with the rise of the pulse 02. The timing circuit 3 outputs a timing signal 103 that is longer than the clock disconnection time T1 by a time T2 in synchronization with the rising of the pulse of the input clock disconnection signal 102 in order to control the selection time of the pseudo clock signal 104. In the SEL4, the output selection of the input clock signal 101 and the pseudo clock signal 104 is performed by the timing signal 103, and the pseudo clock signal 104 is output to the CMOS circuit 5 at the time (T1 + T2) immediately after the input clock is cut off. Then, the input clock is output to the CMOS circuit 5. Here, the times T2 and T3 are calculated by the equations (1)

T2> T3... (1), and the pseudo clock signal 104 returns to the “L” level state again after the time of (T1 + T3 + α) (α> 0).

[0008]

As described above, according to the present invention, C
In a MOS circuit, when a sudden current fluctuation occurs at the time of recovery from an input clock interruption, the instantaneous drop in voltage is caused by CM
Rather than suddenly adding a clock input to the OS circuit,
This can be prevented by gradually increasing the frequency. As a result, the load fluctuation tolerance of the output of the power supply circuit can be reduced, and an inexpensive and simplified power supply circuit can be used.

[Brief description of the drawings]

FIG. 1 is a block diagram of one embodiment of the present invention.

FIG. 2 is a time chart of the embodiment of the present invention.

FIG. 3 is a block diagram of a conventional circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Inrush current prevention circuit 2 Pseudo clock generation circuit 3 Timing circuit 4 Clock selection circuit (SEL) 5 CMOS circuit 6 Clock disconnection detection circuit

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-60-182818 (JP, A) JP-A-61-202524 (JP, A) JP-A-2-192218 (JP, A) JP-A 62-182218 67619 (JP, A) JP-A-60-229530 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H03K 19/003 H03K 19/00 H03K 19/096

Claims (1)

(57) [Claims] 1. A pseudo clock generating circuit which is inserted in a path for guiding an input clock to a CMOS circuit and outputs a pseudo clock whose frequency increases with time after input clock disconnection recovery, and is controlled by input clock disconnection information. A timing circuit that outputs a timing signal and controls a selection time of the pseudo clock; and a clock selection circuit that selects the input clock and the pseudo clock in response to the timing signal and outputs the selected clock to the CMOS circuit. A rush current prevention circuit characterized by the following.