JP2998684B2 - Numerically controlled oscillator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a numerically controlled oscillator for digitally generating a sine wave and a cosine wave by reading a function value stored in a ROM.

[0002]

2. Description of the Related Art As a numerically controlled oscillator (direct digital synthesizer, DDS) for digitally generating a sine wave and a cosine wave, a numerically controlled oscillator as shown in FIG. 3 is conventionally known. 3, the phase accumulator 14 arbitrarily outputs a phase at a time as L-bit data by giving a phase change amount ΔPHASE per unit time given by the reference signal MCLK. The L-bit phase data is used as an address of a lookup table 15 configured using a ROM, and a function value corresponding to the address is output from the lookup table 15 as M-bit data.

[0003] To retain all the function values of one period in the look-up table 15 which is constructed by using the ROM, the input of the ROM is L bits, because the output is M bits, 2 ^L × a capacity of ROM ^M bits are required. In the above method, the trigonometric function generated by the numerically controlled oscillator is 2π
Although only the fact that it is a periodic function with a period of is used, sine waves and cosine waves have symmetry with respect to amplitude and phase. Done.

That is, since the sine wave is symmetrical about the amplitude around π in the range of 0 to 2π, the amplitude data to be held in the POM is reduced to １ ／ by using a simple inverting / non-inverting circuit. In addition, the phase data can be set to 0 to π. In the phase interval 0 to π, since the phase is symmetric about π / 2, the phase data to be held in the ROM is also 0 to π / π by using a simple inversion / non-inversion circuit. It can be 2. The same applies to cosine waves.

As described above, the ROM input is reduced by 2 bits and the output is reduced by 1 bit as compared with the case where all the function values for one cycle are held. Therefore, the amount of data to be stored in the ROM of the numerically controlled oscillator is 2 ^{(L-2) (M-1)} bits.

Usually, the number of ROM output bits is reduced to M-4 bits by using the method shown in FIG.
The data to be stored in the ROM is reduced.

In FIG. 4, a waveform generated by the sawtooth wave A generator 16 is func1 and a sawtooth wave B generator 17 is shown.
The waveform generated by the function is defined as func2, and the waveform generated by the difference waveform generator 18 is defined as func3. func1, fu
nc2 and func3 are obtained by separating the cosine wave into three terms within the range of 0 ≦ θ ≦ π / 2 as follows.

[0008]

## EQU1 ## func1 is a linear approximation, and func2 is a triangular wave approximation, both of which can be realized by simple logic circuits. func3 is an approximation error of func1 and func2, which is not more than 1/8. By performing the same for the cosine wave, if the magnitude of the quantization is the same, all the function values in the interval 0 ≦ θ ≦ π / 2 are set to RO
The ROM output can be reduced by 3 bits as compared with the method of storing the data in M.

[0009]

In a numerically controlled oscillator used in a digital modulation / demodulation circuit or the like which requires a characteristic that an output frequency can be freely set within a certain range and no harmonics exist in a certain band, a fine control oscillator is used. Since a phase step is required, the required ROM capacity becomes very large even if the above-mentioned conventional technique is used, and the ROM area occupies the largest area in the numerically controlled oscillator circuit.

An object of the present invention is to reduce the circuit scale by adopting a configuration in which the capacity of a ROM occupying a large area in a numerically controlled oscillator can be further reduced.

[0011]

According to the present invention, a function value for a large phase is calculated from a function value for a small phase by using a recurrence formula, data to be stored in a ROM is reduced, and a ROM capacity is reduced. It is intended to reduce the cost.

That is, the addition theorem cos (α + β) = cosαcosβ−sinαsin
β sin (α + β) = cos α sin β + sin α cos
If α = θ and β = (m−1) θ by β, the following recurrence formula is obtained.

Cosθ = cosθcos (m−1) θ
−sin θ sin (m−1) θ sinm θ = cos θ sin (m−1) θ + sin θc
os (m−1) θ Using the above recurrence formula, cos θ, si with respect to phase θ
A function value cos (mθ) corresponding to a phase that is m times as large as nθ,
sin (mθ) can be calculated. Therefore, the phase 0 ≦ θ ≦ π / 2m is stored in the ROM which is a lookup table.
Holds the function values cos θ and sin θ corresponding to 0 ≦ θ ≦ π / 2, the function values cos (mθ) and
sin (mθ) can be output, and the ROM capacity can be reduced to 1 / m of the conventional value. Especially in the case of m = 2, it is possible to ^{cos2θ = 2cos 2 θ-1 sin2θ} = 2sinθcosθ next, 1/2 of the prior art shown in FIG. 4 the ROM capacity is.

[0014]

FIG. 1 is an overall block diagram showing an embodiment of the present invention.
M2 and a phase-m multiplication circuit 3. Address generation circuit 1
Is the phase mθ (0 ≦ θ ≦ θmax, θmax = π / 2m)
Is multiplied by 1 / m and the ROM address θ is output. This circuit can be configured using, for example, a divider. In particular, when m is a power of 2, it can be simply configured by bit shifting. The ROM 2 stores the phase θ (0 ≦ θ ≦ θma
This is a lookup table that holds function values cos θ and sin θ corresponding to x) and outputs function values cos θ and sin θ according to the input θ. The phase m multiplication circuit 3 is RO
It outputs cos (mθ) and sin (mθ) obtained by multiplying the phase of cos θ and sin θ, which are the outputs of M2, by m.

FIG. 2 shows the phase m used in the present invention.
FIG. 3 is a detailed block diagram illustrating an example of a doubler circuit, and includes multipliers 4 to
7, a feedback loop including adders 8 and 9 and delay units 10 and 11, an m-ary counter 12, and a latch circuit 13.

Cos θ, s which are the inputs of the phase m multiplication circuit 3
Of in θ, cos θ is input to multipliers 4 and 5, and sin θ is input to multipliers 6 and 7. The outputs of the phase m multiplication circuit are input to the delay units 10 and 11, and the output of the phase m multiplication circuit is output from each delay unit with a delay of one time slot.

In the multiplier 4, the input cos θ of the phase m times circuit is
Is multiplied by the output of the delay unit 10, and the multiplier 5 multiplies the input cos θ of the phase m times circuit by the output of the delay unit 11.
In the multiplier 6, the input sin θ of the phase m multiplication circuit and the delay device 10
Is multiplied by the output of the multiplier 7, and the input s of the phase m-times circuit is input to the multiplier 7.
In θ is multiplied by the output of the delay unit 11. In the adder 8, the outputs of the multipliers 4 and 7 are added, and in the adder 9, the outputs of the multipliers 5 and 6 are added.

The m-ary counter 12 outputs a latch signal every m time slots. The latch signal is input to the latch circuit 13, and the outputs of the adders 8 and 9 are latched by the latch circuit 13. The latch circuit is constituted by, for example, a flip-flop.

Next, the operation of the embodiment of the present invention will be described with reference to FIGS. When the phase θ _in is inputted by the external circuit, the address generator 1 makes θ = θ _in /
m is obtained and input to the ROM 2 as address data. From the ROM 2, function values cos (θ _in / m) and sin (θ _in / m) corresponding to the address data are read and output. This function value is input to the phase m multiplication circuit 3, where the addition theorem of the trigonometric function cosmθ = cosθcos (m−1) θ−sinθs
in (m-1) θ sinmθ = cos θsin (m-1) θ + sin θc
Using os (m−1) θ, a function value cosθ _in , si corresponding to a phase of m times
nθ _in is determined.

The phase m multiplication circuit 3 has a feedback loop (see FIG. 2), and has a circuit configuration for obtaining a function value corresponding to m times the phase by rotating the loop m times.

The output phase of the m-th time slot in the m-th time slot is function values cos (m-1) θ and sin (m-1) θ corresponding to the phase (m-1) θ. Then, the output of the delay unit 10 in the m time slot is cos
(M−1) θ, the output of the delay unit 11 is sin (m−1) θ
Becomes Therefore, cos (m-1) θ is provided to multipliers 4 and 6.
Is fed back and the multipliers 5 and 7 receive sin (m−
1) θ is fed back. Since the input of the phase m multiplication circuit 3 is cos θ and sin θ, the outputs of the multipliers 4 to 7 are as follows.

The output of the multiplier 4 cosθcos (m−1) θ The output of the multiplier 5 cosθsin (m−1) θ The output of the multiplier 6 sinθcos (m−1) θ The output of the multiplier 7 sinθsin (m−1) The adder 8 adds the outputs of the multiplier 4 and the multiplier 7, and the adder 9 adds the outputs of the multiplier 5 and the multiplier 6. Therefore, the adder 8 and the adder 9 are added by the addition theorem of a trigonometric function. Are the outputs of cos θ cos (m-1) θ-sin θ
sin (m-1) θ = cos (mθ) cosθsin
(M−1) θ + sin θcos (m−1) θ = sin
(Mθ). That is, the output of the phase m multiplication circuit 3 at the time of m time slots is cos (mθ) and sin (mθ). The outputs of the delay units 10 and 11 during the first time slot are set to 1.

In the present invention, since the phase is incremented by θ by using the recurrence formula successively, the outputs of the adders 8 and 9 at the time slot i are cos (iθ) and sin (iθ). Since the outputs of the adders 8 and 9 at the time of the m-th time slot are latched by the m-ary counter 12 and the latch circuit 13, cos (mθ) and sin (m)
θ) is output.

[0024]

As described above, according to the present invention, 0 to θ
Since the function value of 0 to mθ can be obtained from the address data, the ROM capacity occupying the largest area of the numerically controlled oscillator can be reduced to 1 / m of the conventional ROM, and the circuit scale of the numerically controlled oscillator can be reduced. Can be reduced in size.

[0025]

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a numerically controlled oscillator of the present invention.

FIG. 2 is a block diagram showing an example of a phase-m multiplier circuit used in the numerically controlled oscillator of the present invention.

FIG. 3 is a block diagram showing a conventional embodiment.

FIG. 4 is a block diagram showing a conventional embodiment.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Address generation circuit 2 ROM 3 Phase m multiplication circuit 4-7 Multiplier 8,9 Adder 10,11 Delay device 12 M-ary counter 13 Latch circuit 14 Phase accumulator 15 Lookup table 16 Saw wave A generator 17 Saw wave B Generator 18 Difference waveform generator 19 Adder 20 Bit inverter

Claims (5)

(57) [Claims] 1. An address generating means for generating an address signal, means for inputting the address signal as a variable value, and outputting a corresponding function value, inputting the function value, and using a recurrence formula Means for outputting a function value corresponding to a variable value that is a predetermined multiple of the value. 2. The method according to claim 1, wherein the address signal is input as a variable value,
2. The numerically controlled oscillator according to claim 1, wherein the means for outputting the corresponding function value is constituted by a ROM functioning as a look-up table. 3. The numerically controlled oscillator according to claim 2, wherein said look-up table holds data in a predetermined range of a sine wave and a cosine wave. 4. The numerically controlled oscillator according to claim 1, wherein said recurrence formula is an addition theorem of a trigonometric function. 5. A circuit for realizing said recurrence formula includes a feedback loop.
Numerically controlled oscillator as described.