JP4520586B2 - Frequency synthesizer and Gaussian noise generator - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a frequency synthesizer having a wide frequency range and high frequency resolution, and a Gaussian noise generator using the same.
[0002]
[Prior art]
Conventionally, a DDS (Direct Digital Synthesizer) has been used as a frequency synthesizer capable of generating a periodic function signal having a stable frequency.
[0003]
FIG. 14 shows the configuration of the DDS 10. In the waveform memory 11, amplitude data of a periodic function (for example, a sine wave function) is stored for one period in a storage area that can be specified by an L-bit address signal. The amplitude data stored in the address specified by the address signal is sequentially output.
[0004]
The frequency setting unit 12 sets frequency data A for designating an address interval (phase interval) for reading amplitude data from the waveform memory 11.
[0005]
The adder 13 adds the frequency data A set by the frequency setting means 12 and the output of the latch circuit 14, and outputs the addition result to the latch circuit 14. The latch circuit 14 latches the output of the adder 13 every time the clock signal CK is received, and outputs the latch output to the adder 13 and the waveform memory 11 as data specifying the phase.
[0006]
The D / A converter 15 converts the amplitude data output from the waveform memory 11 into an analog signal and outputs the analog signal.
[0007]
In the DDS 10 configured as described above, the address signal for the waveform memory 11 increases in intervals of A such as A, 2A, 3A,... In synchronization with the clock signal CK, and the waveform memory 11 corresponds to each address. Amplitude data D (A), D (2A), D (3A),... To be read in order and converted into analog signals, and periodic function signals are continuously output.
[0008]
Here, if the bit number M of the frequency data A set from the frequency setting means 12 is equal to the bit number L of the address signal, the output frequency F is fc · A / 2.^LThe frequency that can be generated is fc · 1/2^L~ Fc ・ 2^L-1/ 2^LUntil 2^L-1It becomes street.
[0009]
However, this method has a problem that the setting resolution of the frequency that can be output is limited by the number of bits L of the address of the waveform memory 11.
[0010]
For this reason, in a DDS that requires a higher setting resolution, the M-bit frequency data A is composed of an L-bit integer part and an m-bit fractional part, and the adder 13 and the latch circuit 14 are added with L + m-bit addition and The latch circuit 14 is configured to be able to latch, and the upper L bits of the L + m-bit output of the latch circuit 14 are output as an address signal to the waveform memory 11, so that the signal with a frequency resolution not limited by the number L of address bits of the waveform memory 11 Was able to generate.
[0011]
[Problems to be solved by the invention]
However, using the DDS 10, for example, the frequency accuracy is 10^-15When generating an arbitrary frequency signal using the output (for example, 100 MHz) of the hydrogen maser oscillator as a reference clock signal CK, the DDS 10 is required to have a frequency resolution of 16 digits or more.
[0012]
In this case, log₂10¹⁶Is almost 2⁵⁴Therefore, it is necessary to use a 54-bit binary adder as the adder 13.
[0013]
However, when addition processing with a large number of bits is performed as described above, the delay time due to the carry processing of the adder 13 exceeds the cycle of the clock signal CK, which is not practical.
[0014]
That is, if the carry propagation delay time per bit of the adder 13 is Ta, the maximum delay time of the entire adder 13 is (L-1) Ta, and this maximum delay time is shorter than the cycle 1 / fc of the clock signal. However, with current adders, it is not possible to perform addition processing with such a large number of bits at a high clock frequency (100 MHz). Finally, the upper limit of the frequency that can be generated by lowering the clock frequency I had to lower it.
[0015]
An object of the present invention is to solve this problem and to provide a frequency synthesizer that can obtain a high frequency resolution in a wide band and a Gaussian noise generator using the same.
[0016]
[Means for Solving the Problems]
  In order to achieve the object, the frequency synthesizer of claim 1 of the present invention comprises:
  Amplitude data output means for receiving L-bit data and outputting amplitude data of a predetermined periodic function having a phase specified by the data;
  Frequency setting means for setting (K + L-1) -bit data obtained by dividing a desired output frequency by a predetermined clock signal frequency as frequency data;
  A K-bit counter for counting the clock signal;
  The frequency data of (K + L-1) bits from the frequency setting means is divided into L sets of K bit data whose leading bits are shifted by 1 bit, and the K bit count output of the counter and the logical product in units of bits are calculated. And L sets of product-sum calculation circuits for obtaining the total number of bits for which the calculation result is 1 for each set,
  Each total number data obtained by the L sets of product-sum operation circuitsVj (j = 0 to L-1) to the upper side by j bits eachShift and addYuiAnd a shift addition circuit for outputting the lower L bits of the result to the amplitude data output means.
[0017]
  The frequency synthesizer according to claim 2 of the present invention is
  Amplitude data output means for receiving L-bit data and outputting amplitude data of a predetermined periodic function having a phase specified by the data;
  Frequency setting means for setting (K + L-1) -bit data obtained by dividing a desired output frequency by a predetermined clock signal frequency as frequency data;
  A K-bit counter for counting the clock signal;
  The frequency data of (K + L-1) bits from the frequency setting means is divided into L sets of K bit data whose leading bits are shifted by 1 bit, and the K bit count output of the counter and the logical product in units of bits are calculated. And L sets of product-sum calculation circuits for obtaining the total number of bits for which the calculation result is 1 for each set,
  Each total number data obtained by the L sets of product-sum operation circuitsVj (j = 0 to L-1) to the upper side by j bits eachShift and addYuiA shift addition circuit for outputting the lower L bits of the result;
  A latch circuit that latches L-bit data input to the amplitude data output means each time a latch signal is received;
  An addition circuit for adding the output of the shift addition circuit and the output of the latch circuit, and outputting the lower L bits of the addition result to the amplitude data output means;
  Each time the frequency data set by the frequency setting means is changed, the counter is initialized to a value of 1 or a value close thereto, and L-bit data corresponding to the initialized value is received from the shift adder. A control circuit that outputs a latch signal to the latch circuit in accordance with the output timing, and makes the phase value immediately before the frequency change and the phase value immediately after the frequency change of the amplitude data output from the amplitude data output means substantially continuous And.
  A frequency synthesizer according to claim 3 of the present invention is the frequency synthesizer according to claim 1 or 2,
  The shift addition circuit includes:
  The total data is divided into a plurality of sets, and parallel processing for performing shift addition for each set in parallel and serial processing for performing serial shift addition processing for the parallel processing in combination are combined to generate the total data Vj (j = 0 to L-1) are shifted to the upper side by j bits, and the lower L bits are obtained as a result of addition.
[0018]
  Further, the claims of the present invention4The Gaussian noise generator of
  In a Gaussian noise generator that has a sine wave generator that generates a plurality of sine waves with different frequencies, and generates a Gaussian noise signal by adding and synthesizing a plurality of sine waves generated by the sine wave generator,
  The sine wave generator is
  Amplitude data output means for receiving L-bit data and outputting amplitude data of a sinusoidal function having a phase specified by the data;
  (K + L−1) bits obtained by dividing a frequency selected from a geometric series having a u-order algebraic integer as a common ratio for an integer u larger than the number of sine waves by the frequency of a predetermined clock signal. Frequency setting means for setting data as frequency data;
  A K-bit counter for counting the clock signal;
  The frequency data of (K + L-1) bits from the frequency setting means is divided into L sets of K bit data whose leading bits are shifted by 1 bit, and the K bit count output of the counter and the logical product in units of bits are calculated. And L sets of product-sum calculation circuits for obtaining the total number of bits for which the calculation result is 1 for each set,
  Each total number data obtained by the L sets of product-sum operation circuitsVj (j = 0 to L−1) is shifted by j bits to the upper side and added.A shift addition circuit for outputting the lower L bits of the result to the amplitude data output means,
  A sine wave of a plurality of frequencies selected without overlapping from the geometric series having the u-order algebraic integer as a common ratio is generated.
  The Gaussian noise generator according to claim 5 of the present invention is the Gaussian noise generator according to claim 4,
  The shift addition circuit includes:
  The total data is divided into a plurality of sets, and parallel processing for performing shift addition for each set in parallel and serial processing for performing serial shift addition processing for the parallel processing in combination are combined to generate the total data Vj (j = 0 to L-1) are shifted to the upper side by j bits, and the lower L bits are obtained as a result of addition.
[0019]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 shows the configuration of a frequency synthesizer 20 according to an embodiment of the present invention.
[0020]
In the waveform memory 21 serving as the amplitude data output means of the frequency synthesizer 20, amplitude data of an arbitrary periodic function, for example, a sine wave function, is stored in an area that can be specified by an L-bit address signal for one period in the order of addresses. The amplitude data stored in the address (phase) designated by the address signal is output.
[0021]
The D / A converter 22 sequentially converts the amplitude data output from the waveform memory 21 into an analog voltage signal and outputs the analog voltage signal. When an analog signal is not required for the synthesizer output, the D / A converter 22 may be omitted and the amplitude data from the waveform memory 21 may be used as it is as the synthesizer output.
[0022]
The frequency setting means 23 uses a multiplication quantum, which will be described later, as K + L−1 bit data (desired frequency data normalized by the clock frequency) obtained by dividing the desired output frequency F by the frequency fc of the clock signal CK as frequency data B. To the circuit 25.
[0023]
The counter 24 is a 2 for counting the clock signal CK.^KThis is a decimal counter and outputs a K-bit count output N to the multiplication quantization circuit 25.
[0024]
The multiplication quantization circuit 25 multiplies the K bit count output N of the counter 24 by the K + L-1 bit frequency data B set by the frequency setting means 23, and the multiplication result is converted into an L bit address signal. The data is quantized and output to the memory 21.
[0025]
Here, the principle of this multiplication quantization will be described.
When the K bit count output N of the counter 24 is represented by bit data,
N = [n₀, N₁, N₂, ..., n_K-2, N_K-1]_MSB
The value (sample number) is as follows.
[0026]
N =_{p = 0}Σ^K-1(N_p2^p)
However, the symbol_{X = C}Σ^DIndicates the total from X = C to X = D (the same applies hereinafter).
[0027]
Further, when the frequency data B normalized by the clock frequency is represented by bit data,
B = [b₁, B₂, B₃, ..., b_{K + L-3}, B_{K + L-2}, B_{K + L-1}]_LSB
The value can be expressed in binary decimal notation as follows.
B =_{i = 1}Σ^{K + L-1}(B_i2^-I)
[0028]
Therefore, the product Q of the frequency data B and the count output N is
Q =_{p = 0}Σ^K-1(N_p2^p) ・_{i = 1}Σ^{K + L-1}(B_i2^-I)
It becomes.
[0029]
Where 2 in the above equation^p・_{i = 1}Σ^{K + L-1}(B_i2^-I) Can be expressed as the sum of an integer part and a decimal part as follows.
_{i = 0}Σ^p-1(B_pi2ⁱ) +_{i = 1}Σ^{K + L-1}(B_{p + i}2^-I)
[0030]
Therefore, the product Q is
Q =_{p = 0}Σ^K-1n_p[_{i = 0}Σ^p-1(B_pi2ⁱ) +_{i = 1}Σ^{K + L-1}(B_{p + i}2^-I)]
= {_{i = 0}Σ^p-12ⁱ _{p = 0}Σ^K-1n_pb_pi}
+ {_{i = 1}Σ^{K + L-1}2^-I _{p = 0}Σ^K-1n_pb_{p + i}} …… (1)
It becomes.
[0031]
Here, the first term of the above formula (1) is an unnecessary integer term (overflow component), and the second term of the required decimal term is 2^LIs represented by an expression including an L-bit integer term as follows.
Q '=_{i = 1}Σ^{K + L-1}2^Li _{p = 0}Σ^K-1n_pb_{p + i}
[0032]
The upper L-bit integer term of the data Q ′ is quantized data.
Here, if j = L−i, the integer term of Q ′ becomes a value in the range of j = 0 to L−1. Therefore, the quantized data q obtained by quantizing the product of the frequency data B and the count output N into L bits is:
q =_{j = 0}Σ^L-1(2^jv_j) ... (2)
However, v_j=_{p = 0}Σ^K-1(N_pb_{p + L-j})
It is expressed.
[0033]
Each v of the above formula (2)_jThe value of_{p = 0}Σ^K-1(N_pb_{p + L-j}) Product sum operation for each value of j._jIs divided into (K + L−1) -bit frequency data B from the frequency setting means 23 into L sets of K-bit data whose leading bits are shifted by 1 bit, and each set of K-bit data and the K bits of the counter 24 The total number of bits for which the operation result of the logical product in bit units with the count output N is 1 is shown.
[0034]
Also, the quantized data q is represented by each v obtained by the product-sum operation._j2 each^jAre multiplied and added, that is, as shown in FIG._jCan be obtained by shifting to the upper side by j bits and adding L bits data on the lower side of the addition result.
[0035]
The multiplication quantization circuit 25 of the embodiment is configured based on the above principle, and as shown in FIG. 1, L product-sum operation circuits 26 (1) to 26 (L), shift addition The circuit 30 is configured.
[0036]
As shown in FIG. 2, each product-sum operation circuit 26 (1) to 26 (L) is composed of K AND circuits 27 and an adder 28, and (K + L) from the frequency setting means 23. -1) L sets of K bit data (b₁~ B_K), (B₂~ B_{K + 1}), ..., (b_L-1~ B_{L + K-2}), (B_L~ B_{L + K-1}The AND circuit 27 calculates the logical product of these K-bit data and the K-bit count output N of the counter 24 by the AND circuit 27, and the total number v of bits whose operation result is 1_jIs obtained for each group by the adder 28.
[0037]
Total number data v obtained by each product-sum operation circuit 26 (1) to 26 (L)_jThe number of bits H is 2^HIs a minimum value equal to or greater than K, which is much smaller than the number of bits K + L−1 of the frequency data B, so that the delay due to this addition does not cause a problem. For example, when K = 62 and L = 16, the total number data v_jThe number of bits H is 6 and is very small compared to the number of bits of frequency data B K + L-1 = 77.
[0038]
Each total number data v obtained by each product-sum operation circuit 26 (1) -26 (L)_jAre shifted one bit at a time by the shift addition circuit 30 and added.
[0039]
For example, as shown in FIG. 4, the shift adder circuit 30 can be configured using L shift adders 31 (1) to 31 (L). Note that the data shift processing in the shift adders 31 (1) to 31 (L) is simply to input data by shifting the digit, and to add 0 to the lower side for the shifted digit. The processing time is not required. In FIG. 4 and FIGS. 5 and 6 described later, the number of bits to which the value of S is shifted is shown.
[0040]
The shift adder 31 (1) calculates the total number data v₀And total data v₁Is added to the data shifted by 1 bit higher (data with 0 added to the lower bit), and the shift adder 31 (2) outputs the output of the shift adder 31 (1) and the total data v₂Is added to the data shifted to the upper side by 2 bits (data in which 0 is added to the lower side by 2 bits).
[0041]
Similarly, total data v_jAnd the quantized data q quantized to L bits is output from the shift adder 31 (L) at the final stage.
[0042]
However, when the shift adder circuit 30 is actually configured, if the L K shift adders 31 (1) to 31 (L) are simply cascade-connected as shown in FIG. Since this is disadvantageous in terms of speed, it is desirable to perform shift addition processing in parallel as in a shift addition circuit 30 described later.
[0043]
That is, the expression (2) of the quantized data q can be expanded as follows.
(When L is an even number)
q = (v₀+ 2v₁+2²(V₂+ 2v₃+2⁴(V₄+ 2v₅)
+ ... + 2^L-4(V_L-4+ 2v_L-3+2^L-2(V_L-2+ 2v_L-1) ... (2)
[0044]
(When L is an odd number)
q = (v₀+ 2v₁+2²(V₂+ 2v₃+2⁴(V₄+ 2v₅)
+ ... + 2^L-3(V_L-3+ 2v_L-2+2^L-1v_L-1... (3)
[0045]
The above formulas (2) and (3)^XHere, as an example, a shift adder circuit 30 corresponding to Expression (2) is shown in FIG.
[0046]
In the shift addition circuit 30 of FIG. 5, the total number data v is shifted and added by two sets by L / 2 shift adders 31 (1) to 31 (R) (R = L / 2), and their outputs are output. Shift addition of R-1 shift adders 31 (R + 1) to 31 (2R-1) is performed to obtain L-bit quantized data q.
[0047]
By including parallel processing in this way, the number of addition stages can be reduced to half that in the case of FIG. 4, and high-speed processing is possible. As described above, the formula (2) or the formula (3) is further changed to 2^XIn summary, the number of addition stages can be further reduced. This will be described in the following section on actual operation.
[0048]
Next, the operation of this embodiment will be described in the case of K = 62 and L = 16, for example.
77-bit frequency data B (b from the frequency setting means 23₁~ B₇₇) Is set, each of the product-sum operation circuits 26 (1) to 26 (16) outputs the 62-bit count output N (n₀~ N₆₁)
v₀=_{p = 0}Σ⁶¹(N_pb_{p + 16})
v₁=_{p = 0}Σ⁶¹(N_pb_{p + 15})
v₂=_{p = 0}Σ⁶¹(N_pb_{p + 14})
......
v₁₅=_{p = 0}Σ⁶¹(N_pb_{p + 1})
The total number of data v₀~ V₁₅Is output to the shift adder circuit 30. In this case, as described above, each total number data v₀~ V₁₅The number of bits H is 6 bits.
[0049]
The shift addition circuit 30 calculates the total number data v₀~ V₁₅Shift addition processing is performed on the basis of the following equation.
q = [v₀+ 2v₁+2²v₂+ ... + 2¹⁴v₁₄+2¹⁵v₁₅]_mod16
= [V₀+ 2v₁+2²v₂+ ... + 2¹⁰v₁₀]_mod16
+ [2¹¹v₁₁]_mod16+ [2¹²v₁₂]_mod16
+ [2¹³v₁₃]_mod16+ [2¹⁴v₁₄]_mod16
+ [2¹⁵v₁₅]_mod16
However, bracket sign [Y]_mod16Indicates data obtained by converting data Y into 16 bits.
[0050]
Here, 6-bit data v_jThe data generated by shifting 11 bits (adding 11 bits of 0 to the lower side) and taking the lower 16 bits is the original 6-bit data v_jLower 5 bits of data V_jIs equivalent to 11 bits shifted.
[0051]
Therefore, v₁₁Lower 5 bits of V₁₁, V₁₂Lower 4 bits of V₁₂, V₁₃Lower 3 bits of V₁₃, V₁₄Lower 2 bits of V₁₄, V₁₅Lower 1 bit (LSB) of V₁₅Then, the quantized data q is
q = [v₀+ 2v₁+2²v₂+ ... + 2¹⁰v₁₀]_mod16
+ [2¹¹V₁₁]_mod16+ [2¹²V₁₂]_mod16
+ [2¹³V₁₃]_mod16+ [2¹⁴V₁₄]_mod16
+ [2¹⁵V₁₅]_mod16
= [{(V₀+ 2v₁+2²(V₂+ 2v₃)}
+2⁴{(V₄+ 2v₅+2²(V₆+ 2v₇)}
+2⁸{(V₈+ 2v₉+2²v₁₀}]_mod16
+ [2¹¹{(V₁₁+ 2V₁₂)
+2²(V₁₃+ 2V₁₄+2⁴V₁₅}]_mod16
It becomes.
[0052]
The shift adder circuit 30 performs this calculation with 15 shift adders 31 (1) to 31 (15) as shown in FIG.
[0053]
The number of addition stages of the shift addition circuit 30 is five at the maximum, and each shift adder 31 performs only a maximum of 16-bit addition processing.
[0054]
In addition, the speed of the counter 24 that counts the clock signal CK is much higher than that of a conventional M-bit adder or the like. Therefore, even when the clock frequency is as high as 100 MHz, for example, the frequency can be set with a resolution of 77 bits. Can achieve high frequency resolution.
[0055]
Thus, since the frequency synthesizer 20 of the embodiment has a wide frequency range and high frequency resolution, it can be used as a signal source of a general signal generator, and has a frequency accuracy of 10 as described above.^-15Even when a frequency resolution of 16 digits or more is required, as in the case of generating a signal of an arbitrary frequency using the output of the hydrogen maser oscillator (for example, 100 MHz) as a reference clock signal CK, it can be used without any problem.
[0056]
Further, since the frequency synthesizer 20 has a very high frequency setting resolution, the frequency synthesizer 20 can be used as a sine wave generator when generating Gaussian noise whose amplitude distribution approximates to a Gaussian distribution with high accuracy.
[0057]
Next, a Gaussian noise generator that generates a Gaussian noise signal using this frequency synthesizer will be described.
[0058]
In the Gaussian noise generator described below, each frequency of a plurality of sine waves is duplicated in a geometric sequence having a u-order algebraic integer as a common ratio for an integer u larger than the number of the sine waves. This is based on the knowledge that the distribution of the sample values of the synthesized wave obtained by synthesizing the plurality of sine waves approaches a Gaussian distribution (this proof method will not be described in detail).
[0059]
Here, the u-order algebraic integer is the following polynomial U (x),
U (x) = x^u+ M_u-1x^u-1+ ... + m₁x + m₀
(Coefficient m₀~ M_u-1Is an integer)
Suppose that U (x) is irreducible in the range of integer coefficients, that is, U (x) cannot be factored.
[0060]
For example, the value E^{1 / u}Is the root of the above polynomial U (x), that is, u-algebraic integer, this value E^{1 / u}Geometric sequence with a common ratio
E^{1 / u}/ G, E^{2 / u}/ G, E^{3 / u}/G,...,E^{(U-1) / u}/ G
(G is an integer of 1 or more)
Thus, a Gaussian noise signal can be obtained by selecting the frequency of each sine wave without overlapping.
[0061]
FIG. 7 shows a sine wave generator that generates a plurality of sine waves having different frequencies in parallel by using a plurality of waveform memories 21, frequency setting means 23, and multiplication quantization circuit 25 of the frequency synthesizer 20 described above. A noise signal generator 50 that generates a Gaussian noise signal by adding and synthesizing a plurality of sine waves is shown.
[0062]
The noise generator 50 is provided with W (W is an integer less than or equal to 1 and less than u) waveform memories 21 (1) to 21 (W) as amplitude data output means, and the waveform memories 21 (1) to 21 (W) are provided. In 21 (W), the same sine waveform data is stored in advance in an area that can be specified by an L-bit address signal for one period.
[0063]
The sine wave data is represented by q, where L-bit quantized data for designating an address is q.
cos (2πq / 2^L)
(Sin (2πq / 2^L).
[0064]
Each of the frequency setting means 23 (1) to 23 (W) is a frequency data B corresponding to a frequency selected without duplication from the geometric sequence having a common ratio of the u-th order algebraic integer.₁~ B_WAre set in the multiplication and quantization circuits 25 (1) to 25 (W), respectively.
[0065]
For example, when generating a noise signal having a spectrum distributed in the band of the upper limit frequency fa and the lower limit frequency fb, each frequency data B within the range of the frequencies fa / fc and fa / fc normalized by the clock frequency fc.₁~ B_WIs set as follows.
[0066]
B₁= E^{1 / u}/ G
B₂= E^{2 / u}/ G
B₃= E^{3 / u}/ G
......
B_W= E^{W / u}/ G
[0067]
Each multiplication quantization circuit 25 (1) to 25 (W) has frequency data B set by frequency setting means 23 (1) to 23 (W), respectively.₁~ B_WAnd the count output N of the counter 24 are multiplied in the same manner as above to quantize them to L bits, and the quantized data q₁~ Q_WAre output as address signals to the respective waveform memories 21 (1) to 21 (W).
[0068]
The multipliers 51 (1) to 51 (W) are amplitude data D output from the waveform memories 21 (1) to 21 (W).₁~ D_WIn contrast, the amplitude coefficient S set by the amplitude setting means 52₁~ S_WAnd the multiplication result is output to the synthesis circuit 53.
[0069]
The synthesis circuit 53 adds and synthesizes the outputs of the multipliers 51 (1) to 51 (W), and outputs the addition result as a noise signal Ng.
[0070]
When an analog noise signal is required, the digital output of the synthesis circuit 53 is converted into an analog signal by a D / A converter (not shown) and output.
[0071]
In the Gaussian noise generator 50 configured as described above, the frequency data B of K + L−1 bits is obtained by the multiplication quantization circuits 25 (1) to 25 (W) as described above.₁~ B_WAnd the K bit count output N of the counter 24 are multiplied and quantized, and the L bit quantized data q₁~ Q_WAre output to each of the waveform memories 21 (1) to 21 (W).
[0072]
For this reason, from each waveform memory 21 (1) to 21 (W),
D₁= Cos (2πq₁/ 2^L)
D₂= Cos (2πq₂/ 2^L)
D₃= Cos (2πq₃/ 2^L)
......
D_W= Cos (2πq_W/ 2^L)
Amplitude data D₁~ D_WAre output in parallel every clock.
[0073]
These amplitude data D₁~ D_WAmplitude coefficient S₁~ S_WIs multiplied and the multiplication result
D₁'= S₁cos (2πq₁/ 2^L)
D₂'= S₂cos (2πq₂/ 2^L)
D₃'= S₃cos (2πq₃/ 2^L)
......
D_W'= S_Wcos (2πq_W/ 2^L)
Is output to the synthesis circuit 53, and data obtained by adding and synthesizing these multiplication results is output as the noise data signal Ng.
[0074]
Here, the amplitude setting means 52 causes, for example, all the amplitude coefficients S₁~ S_WIs set to an equal value, white Gaussian noise in which the spectrum is distributed almost uniformly in the set frequency range fa to fb can be obtained as shown in FIG.
[0075]
Further, the amplitude coefficient decreases by the amplitude setting means 52 in inverse proportion to the frequency in the range of frequencies fa to f1, for example, the amplitude coefficient is constant in the range of frequencies f1 to f2, and proportional to the frequency in the range of frequencies f2 to fb. If the amplitude coefficient is set to increase, colored Gaussian noise with a nonuniform spectrum distribution can be obtained as shown in FIG.
[0076]
The Gaussian noise generator 50 generates a plurality of sine waves in parallel using the frequency synthesizer and synthesizes them in parallel. Therefore, the operating speed is high and Gaussian noise can be generated up to a high frequency band.
[0077]
The Gaussian noise generating device 50 has a circuit scale that increases according to the number of sine waves. Therefore, when the number of sine waves is small, for example, when a Gaussian noise signal in a relatively narrow band and a high frequency band is generated. However, when the number of sine waves is large, it is easy to switch between frequency data and coefficients at a high speed with a set of frequency synthesizers as in the Gaussian noise generator 60 shown in FIG. A wide-band Gaussian noise can be generated with a simple circuit configuration.
[0078]
The Gaussian noise generating device 60 has a plurality of sine wave frequency data B described above.₁~ B_WA frequency data memory 61 that stores (K + L-1 bits) in advance in the order of addresses, and a coefficient S₁~ S_WAre stored in advance in the order of addresses, and a coefficient data memory 62 and an address counter 63 for reading data from these memories in order.
[0079]
The address counter 63 is a (W + 1) -ary counter, counts a clock signal CK 'having a frequency (W + 1) times the clock frequency fc, and outputs a count until the clock signal CK' is input from 1 to W clocks. To specify the addresses of the frequency data memory 61 and the coefficient data memory 62, and the frequency data B₁~ B_WAnd coefficient S₁~ S_WAre read one by one in synchronization with the clock signal CK ′, and when the (W + 1) -th clock is input, the clock signal CK is output to the counter 24 by one clock. The clock signal CK is also used as a reset signal for a latch circuit 65 described later.
[0080]
The counter 24 counts the clock signal CK from the address counter 63 and inputs the K-bit count output N to the multiplication quantization circuit 25 in the same manner as described above.
[0081]
The multiplication quantization circuit 25 outputs the count output N of the counter 24 and the frequency data B of K + L−1 bits sequentially output from the frequency data memory 61.₁~ B_WAnd the quantized data q of L bits for the same count output N₁~ Q_WAre sequentially output to the waveform memory 21 as address signals.
[0082]
The waveform memory 21 stores each quantized data q₁~ Q_WAmplitude data D of the address specified by₁~ D_WAre sequentially output to the multiplier 51.
[0083]
The multiplier 51 receives each amplitude data D sequentially read from the waveform memory 21 in synchronization with the clock signal CK ′.₁~ D_WThe coefficient S sequentially read out from the coefficient data memory 62 in synchronization with the clock signal CK ′.₁~ S_WAnd the multiplication result S₁・ D₁~ S_W・ D_WAre sequentially output to the adder 64.
[0084]
The adder 64 adds the output of the multiplier 51 and the output of the latch circuit 65 and inputs the addition result to the latch circuit 65.
[0085]
The latch circuit 65 latches the output of the adder 64 every time it receives the clock signal CK ′, and inputs the latch output to the adder 64.
[0086]
For this reason, when the count result of the address counter 63 reaches W, the latch circuit 65 has a multiplication result S of each frequency obtained for one of the count results N of the counter 24.₁・ D₁~ S_W・ D_WWill be memorized.
[0087]
The latch circuit 65 receives the clock signal CK as a reset signal and returns the stored contents to zero.
[0088]
The latch circuit 66 latches the data latched in the latch circuit 65 when receiving the clock signal CK, and outputs this as noise signal data Ng.
[0089]
In the Gaussian noise generator 60 configured as described above, amplitude data of one frequency is generated every time the count value of the address counter 63 is incremented by one, and the count value is incremented by W and W types having different frequencies. After the amplitude data is obtained one by one, the noise signal data obtained by adding them is output, and the operation in which the count output N of the counter 24 is incremented by one is repeated, and the Gaussian noise generating device 50 is repeated. Generates a Gaussian noise signal similar to
[0090]
In this Gaussian noise generator 60, the frequency data B is increased while the counter 24 advances by one.₁~ B_WAnd coefficient S₁~ S_WSince the noise signal data for each frequency is generated in order, the configuration is simple even when the frequency of the sine wave is large.
[0091]
Further, a very high speed device is realized as the address counter 63 and the latch circuits 65 and 66, and the number of bits of the adder 64 is determined by the amplitude resolution of the noise signal data to be output. Since it is less than a bit, the delay is not a problem.
[0092]
It is also possible to configure a Gaussian noise generator that is smaller in circuit scale than the Gaussian noise generator 50 and can operate at a higher speed than the Gaussian noise generator 70 by combining the Gaussian noise generators 50 and 70 described above.
[0093]
For example, when W is an even number, as in the Gaussian noise generator 70 shown in FIG. 10, for example, two sets (three or four sets) of the waveform memory 21, the multiplication quantization circuit 25, and the multiplier 51 are provided.
[0094]
The frequency data memory 61 ′ stores two frequency data so that it can be output with one address designation, and is output from the frequency data memory 61 to the coefficient data memory 62 ′ with one address designation. Two coefficients corresponding to the two frequency data are stored so that they can be output.
[0095]
For example, the frequency data B from the frequency data memory 61 ′ is transferred to one multiplication quantizing circuit 25 (1).₁~ B_{W / 2}Are sequentially output, and the frequency data B is supplied to the other multiplication and quantization circuit 25 (2)._{1 + W / 2}~ B_WAre output in order.
[0096]
Similarly, from the coefficient data memory 62 ', one multiplier 51 (1) receives the count S.₁~ S_{W / 2}Are sequentially output, and the other multiplier 51 (2) has a coefficient S_{1 + W / 2}~ S_WAre output in order.
[0097]
Note that the frequency of the clock signal CK ′ is (1 + W / 2) fc, and the address counter 63 ′ uses the count output until the clock signal CK ′ is input for 1 to W / 2 clocks. 61 ', the address of the coefficient data memory 62' is designated, and the clock signal CK is output to the counter 24 at the 1 + W / 2 clock.
[0098]
The outputs of the multipliers 51 (1) and 51 (2) are once added by the adder 71, and the addition result is output to the adder 64.
[0099]
In the Gaussian noise generator 70 configured in this way, amplitude data of two different frequencies is generated every time the count value of the address counter 63 'advances by one, and the count value advances to W / 2. After obtaining W-type amplitude data having different frequencies one by one, noise signal data obtained by adding them is output, and the operation of incrementing the count output of the counter 24 is repeated. To generate a Gaussian noise signal.
[0100]
Therefore, the Gaussian noise generator 70 can operate at a speed almost twice as fast as that of the Gaussian noise generator 60 and is simpler in configuration than the Gaussian noise generator 50.
[0101]
In the above embodiment, the waveform memory 21 storing the amplitude data in advance is used as the amplitude data output means for outputting the amplitude data of the periodic function including the sine wave having the phase specified by the L-bit data. This does not limit the present invention, and a predetermined approximation operation may be performed on L-bit data to output amplitude data of a periodic function.
[0102]
For example, when outputting a sine wave signal in a high frequency band that does not require high waveform accuracy, amplitude data is output by calculating a function that approximates a sine wave with a trapezoidal wave or a triangular wave.
[0103]
That is, when approximated by a triangular wave, the L-bit data q is 0 to (2^LIn the range of / 4) -1, the input data q is output as amplitude data as it is, and the L-bit data q is (2^L/ 4) to (2^L/ 2) -1, the range is (2^L/ 2) A value obtained by subtracting the data q input from −1 is output as amplitude data, and the L-bit data q is (2^L/ 2) to (3.2^LIn the range of / 4) -1, (2^L/ 2), the value obtained by subtracting the input data q is output as amplitude data, and the L-bit data q is (3.2).^L/ 4) to (2^L-1), the input data q to 2^LThe value obtained by subtracting is output as amplitude data.
[0104]
Further, in the case of approximating with a trapezoidal wave, the L-bit data q is (2^L/ 4) -1 predetermined range before and after (3.2)^L/ 4) Fixed amplitude data is output within a predetermined range before and after -1.
[0105]
As described above, the amplitude data output means for calculating and outputting the amplitude data approximated by a triangular wave, a trapezoidal wave or the like can output a periodic function signal at a very high speed because the calculation process is very simple. Note that the output waveform can be made a sine wave by band limiting the approximate signal using a filter.
[0106]
On the other hand, when a high waveform accuracy is required even when the frequency is low, the following approximate expression is calculated.
[0107]
That is, 2 × 10 for the sine function sin (2πa) in the range where the absolute value of a is ¼ or less.^-4An approximate expression with the accuracy of
f (a) = 2πa [1−0.16605 (2πa)²+0.00761 (2πa)⁴]
However, a = q / (2^L-1)
It is expressed.
[0108]
Therefore, L-bit data q is 0 to (2^L/ 4) -1 range,
f (q / 2^L) X (2^L-1-1)
The amplitude data obtained by converting the result of the calculation into an integer is output.
[0109]
Also, the L-bit data q is (2^L/ 4) to (3.2)^L/ 4) -1 range,
f (1 / 2-q / 2^L) X (2^L-1-1)
The amplitude data obtained by converting the result of the calculation into an integer is output.
[0110]
The L-bit data q is (3.2)^L/ 4) to (2^LIn the range of -1)
f (q / 2^L-1) x (2^L-1-1)
The amplitude data obtained by converting the result of the calculation into an integer is output.
[0111]
The Gaussian noise generator 70 described above may use the frequency synthesizer 20 as a fixed frequency signal source. However, as a usage form of the frequency synthesizer, the frequency of the output signal is frequently changed by frequency sweep or manual operation. There is also a case.
[0112]
As described above, in the frequency synthesizer that frequently changes the frequency of the output signal, the generation of noise due to phase discontinuity when the frequency is changed becomes a problem.
[0113]
FIG. 11 shows the configuration of a frequency synthesizer 80 that can suppress the generation of noise due to this phase discontinuity.
[0114]
Similar to the frequency synthesizer 20, the frequency synthesizer 80 includes a waveform memory 21 as an amplitude data output unit, a frequency setting unit 23, a counter 24, and a multiplication quantization circuit 25. An L-bit adder circuit 81 is provided between the adder circuit 30 and the waveform memory 21, and the latch circuit 82 receives the latch signal LH and latches L-bit data input from the adder circuit 81 to the waveform memory 21. The latch output R is input to the adder circuit 81.
[0115]
The control circuit 83 outputs a set signal SET to the counter 24 and initializes the count output N of the counter 24 to a value 1 (or a value close to it) every time the frequency data is changed by the frequency setting means 23. At the same time, the latch signal LH is output to the latch circuit 82 in accordance with the timing when the L-bit data corresponding to the output of the initialized counter 24 is output from the shift addition circuit 30, and the amplitude output from the waveform memory 21. The phase value immediately before the data frequency change and the phase value immediately after the frequency change are made substantially continuous.
[0116]
In the frequency synthesizer 80 configured as described above, every time the clock signal CK shown in FIG. 12A is input, the count output N of the counter 24 increases by 1 as shown in FIG. The product-sum operation of the count output N and the frequency data B from the frequency setting means 23 is performed by the product-sum operation circuits 26 (1) to 26 (L) in the same manner as described above, and the total data v_jThis total data v_jAs described above, the shift addition process is performed by the shift addition circuit 30 and, as shown in FIG. 12D, only the number of clocks corresponding to the number of addition stages of the shift addition circuit 30 (5 clocks in this example). The quantized data q (N, B) for the count output N is output with a delay.
[0117]
The quantized data q (N, B) is input to the adder circuit 81 together with the latch output R (j) latched in the latch circuit 82 as shown in FIG. 12 (f), and the lower L bits of the addition result. Data r (N, B) is output to the waveform memory 21 as shown in FIG. 12G, and the amplitude data D () of the address (phase) specified by the data r (N, B) is output from the waveform memory 21. r) is output.
[0118]
The above operation is repeated until the frequency data B is changed. As shown in FIG. 13, every time one clock signal CK is input, L-bit data r (N, B) input to the waveform memory 21. Are updated by a predetermined interval Δφ determined by the frequency data B, and the amplitude data D (r) of the address (phase) designated by the data r (N, B) is sequentially output.
[0119]
Here, when the frequency data is changed to B ′ smaller than B, for example, by the frequency setting means 23 at time t0 when the count output N of the counter 24 is i, as shown in FIG. The set signal SET is output to the counter 24 at the next clock input time t1, and the count result N of the counter 24 is initialized to 1 as shown in FIG.
[0120]
Therefore, the quantized data q (1, B ′) corresponding to the counting result 1 is the number of addition stages described above following the previous quantized data q (i, B) as shown in FIG. Is output from the shift addition circuit 30 at t2, which is delayed by the number of clocks corresponding to.
[0121]
At t2, the latch signal LH is output from the control circuit 83 to the latch circuit 82 as shown in FIG. 12 (e), and the output R (j + 1) of the latch circuit 82 is sent to the waveform memory 21 at the previous stage. It is updated to a value equal to the input L-bit data r (i, B).
[0122]
For this reason, as shown in FIG. 12G, the addition circuit 81 outputs the lower L bits of data r (1, B ′) of r (i, B) + q (1, B ′). Therefore, every time one clock signal CK is input, r (i, B) + q (2, B ′), r (i, B) + q (3, B ′),... Bit data r (2, B ′), r (3, B ′),... Are output.
[0123]
Here, the first data r (1, B ′) for the frequency data B ′ is obtained by adding the quantized data q (1, B ′) to the final data r (i, B) for the frequency data B. Quantized data q (1, B ′) indicates an address interval Δφ ′ for reading amplitude data with frequency data B ′.
[0124]
Therefore, as shown in FIG. 13, the phase of the amplitude data for the frequency data B ′ increases by an interval Δφ ′ with the final phase r (i, B) of the amplitude data output as the frequency data B as the initial phase. Therefore, phase discontinuity due to the change of frequency data does not occur, and noise due to this phase discontinuity does not occur.
[0125]
Similarly to the frequency synthesizer 20, even when the number of bits of frequency data to be set is large, the phase of amplitude data can be specified with a small delay time compared to the conventional DDS method, and the clock frequency is lowered. And high frequency resolution can be realized.
[0126]
Here, the counter 24 is initialized to 1. However, even when the counter 24 is initialized to a value close to 1, the level of noise generated due to phase discontinuity can be reduced.
[0127]
For example, when the count output N of the counter 24 is initialized to 0, the quantized data q (0, B ′) obtained first for the frequency data B ′ becomes 0, and the output of the adder circuit 81 is the output of the previous stage. Since it becomes equal to the value, the same amplitude data is output twice consecutively as indicated by Ja in FIG. In addition, when the count output N of the counter 24 is initialized to 2, the quantized data obtained first for the frequency data B ′ is q (2, B ′), and as shown by Jb in FIG. The first amplitude data of the frequency data B ′ increases by 2Δφ ′ with respect to the phase of the final amplitude data of the frequency data B.
[0128]
Thus, when the value to be initialized is set to a value close to 1, the complete continuity of the phase is lost, but since the phase difference is small, the level of generated noise can be small. Note that the range of the initial value needs to be limited by a ratio to the number L of input bits of the waveform memory 21. If the initial value is sufficiently smaller than K, the generated noise is sufficiently small. For example, the initial value is 2^L′, The peak value of the generated noise is 6 L ′ dB worse than when the initial value is set to 1.
[0129]
Even in the case of the frequency synthesizer 80, as described in the frequency synthesizer 20, amplitude data for performing a predetermined approximation operation on L-bit data instead of the waveform memory 21 and outputting amplitude data of a periodic function. An output means may be used.
[0130]
【The invention's effect】
As described above, the frequency synthesizer according to claim 1 of the present invention has the amplitude data output means for outputting the amplitude data of the predetermined periodic function having the phase specified by the L-bit data, and the desired frequency at the frequency of the predetermined clock signal. Frequency setting means for setting (K + L-1) -bit data obtained by dividing the output frequency as frequency data, a K-bit counter for counting clock signals, and (K + L-1) from the frequency setting means ) Divide the bit frequency data into L sets of K bit data with the leading bit shifted by 1 bit, calculate the K bit count output of the counter and the bitwise logical product, and the bit whose result is 1 L sets of product-sum operation circuits for which the total number is obtained for each set and the total data obtained by the L sets of product-sum operation circuits are bit-shifted and added, And a shift and add circuit for outputting a low-order L bits of the addition result to the amplitude data output means.
[0131]
Therefore, even when the number of bits of frequency data to be set is large, the phase of the amplitude data can be specified with a small delay time compared to the conventional DDS method, and high frequency resolution is achieved without lowering the clock frequency it can.
[0132]
The frequency synthesizer according to claim 2 of the present invention is
An amplitude data output means for receiving L-bit data and outputting amplitude data of a predetermined periodic function having a phase specified by the data, and a desired output frequency divided by a predetermined clock signal frequency (K + L−) 1) A frequency setting means for setting bit data as frequency data, a K-bit counter for counting clock signals, and (K + L-1) -bit frequency data from the frequency setting means for each bit at the head bit Dividing into L sets of shifted K bit data, calculating the K bit count output of the counter and the logical product in units of bits, and obtaining the total number of bits for which the calculation result is 1 for each set of L sets of products The total number of data obtained by the sum operation circuit and the L sets of product-sum operation circuits are bit-shifted and added, and the lower L bits of the addition result are output. A latch circuit that latches L-bit data input to the amplitude data output means every time a latch signal is received, and the output of the shift adder circuit and the output of the latch circuit are added, and the lower L bits of the addition result are Each time the frequency data set by the adding circuit that outputs to the amplitude data output means and the frequency setting means is changed, the counter is initialized to the value 1 or a value close thereto, and the L corresponding to the initialized value. A latch signal is output to the latch circuit in synchronization with the timing when the bit data is output from the shift adder, and the phase value immediately before the frequency change and the phase value immediately after the frequency change of the amplitude data output from the amplitude data output means And a control circuit for substantially continuously.
[0133]
Therefore, even when the number of bits of frequency data to be set is large, the phase of the amplitude data can be specified with a small delay time compared to the conventional DDS method, and high frequency resolution is achieved without lowering the clock frequency In addition, the generation of noise due to phase discontinuity when changing the frequency can be suppressed.
[0134]
The Gaussian noise generator according to claim 3 of the present invention has a sine wave generator that generates a plurality of sine waves having different frequencies, and adds and synthesizes the plurality of sine waves generated by the sine wave generator. In the Gaussian noise generating device that generates a Gaussian noise signal, the sine wave generator includes: amplitude data output means for outputting amplitude data of a sine wave function having a phase specified by L-bit data; and the number of sine waves (K + L−1) -bit data obtained by dividing a frequency selected from a geometric series having a u-order algebraic integer as a common ratio for a large integer u by the frequency of a predetermined clock signal is set as frequency data. Frequency setting means, a K-bit counter for counting clock signals, and (K + L−1) -bit frequency data from the frequency setting means are shifted by 1 bit from the first bit. L sets of product-sum operation circuits that calculate the K bit count output of the counter and the bitwise logical product and obtain the total number of bits for which the operation result is 1 for each set. Each of the total number data obtained by the L sets of product-sum operation circuits is bit-shifted and added, and a shift addition circuit that outputs the lower L bits of the addition result to the amplitude data output means, It is configured to generate a sine wave having a plurality of frequencies selected without overlapping from a geometric series having an integer as a common ratio.
[0135]
Therefore, it is possible to generate a highly accurate Gaussian noise signal whose amplitude is very close to a Gaussian distribution.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of an embodiment of a frequency synthesizer of the present invention.
FIG. 2 is a diagram for explaining the operation principle of the main part of the present invention.
FIG. 3 is a diagram illustrating a circuit configuration example of a main part of the embodiment.
FIG. 4 is a diagram showing a circuit configuration example of a main part of the embodiment.
FIG. 5 is a diagram showing a circuit configuration example of a main part of the embodiment.
FIG. 6 is a diagram showing a circuit configuration example of a main part of the embodiment.
FIG. 7 is a block diagram showing a configuration of an embodiment of a Gaussian noise generator according to the present invention.
FIG. 8 is a diagram illustrating an example of an output spectrum of the Gaussian noise generator according to the embodiment;
FIG. 9 is a block diagram showing the configuration of another embodiment of the Gaussian noise generator of the present invention.
FIG. 10 is a block diagram showing the configuration of another embodiment of the Gaussian noise generator of the present invention.
FIG. 11 is a block diagram showing the configuration of another embodiment of the frequency synthesizer of the present invention.
12 is a timing chart for explaining the operation of the embodiment of FIG.
13 is a diagram for explaining the operation of the embodiment of FIG. 11;
FIG. 14 is a block diagram showing a configuration of a conventional apparatus.
[Explanation of symbols]
20, 80 frequency synthesizer
21 Waveform memory
22 D / A converter
23 Frequency setting means
24 counter
25 Multiplication quantization circuit
26 Product-sum operation circuit
27 AND circuit
28 Adder
30 shift adder circuit
31 shift adder
50, 60, 70 Gaussian noise generator
51 multiplier
52 Coefficient setting means
53 Synthesis Circuit
61, 61 'Frequency data memory
62, 62 'coefficient data memory
63, 63 'address counter
64 adder
65, 66 Latch circuit
71 adder
81 Adder circuit
82 Latch circuit
83 Control circuit

Claims (5)

Amplitude data output means for receiving L-bit data and outputting amplitude data of a predetermined periodic function having a phase specified by the data;
Frequency setting means for setting (K + L-1) -bit data obtained by dividing a desired output frequency by a predetermined clock signal frequency as frequency data;
A K-bit counter for counting the clock signal;
The frequency data of (K + L-1) bits from the frequency setting means is divided into L sets of K bit data whose leading bits are shifted by 1 bit, and the K bit count output of the counter and the logical product in units of bits are calculated. And L sets of product-sum calculation circuits for obtaining the total number of bits for which the calculation result is 1 for each set,
The L sets of each total number data Vj obtained by the product sum operation circuit (j = 0~L-1), said lower L bits of the result obtained by adding a shift to the higher side by j bits each amplitude data A frequency synthesizer comprising a shift addition circuit for outputting to an output means. Amplitude data output means for receiving L-bit data and outputting amplitude data of a predetermined periodic function having a phase specified by the data;
Frequency setting means for setting (K + L-1) -bit data obtained by dividing a desired output frequency by a predetermined clock signal frequency as frequency data;
A K-bit counter for counting the clock signal;
The frequency data of (K + L-1) bits from the frequency setting means is divided into L sets of K bit data whose leading bits are shifted by 1 bit, and the K bit count output of the counter and the logical product in units of bits are calculated. And L sets of product-sum calculation circuits for obtaining the total number of bits for which the calculation result is 1 for each set,
Shift for outputting the lower L bits of the result of the L sets of the total number of data obtained by the product sum operation circuits Vj (j = 0~L-1) , obtained by adding a shift to the higher side by j bits, respectively An adder circuit;
A latch circuit that latches L-bit data input to the amplitude data output means each time a latch signal is received;
An addition circuit for adding the output of the shift addition circuit and the output of the latch circuit, and outputting the lower L bits of the addition result to the amplitude data output means;
Each time the frequency data set by the frequency setting means is changed, the counter is initialized to a value of 1 or a value close thereto, and L-bit data corresponding to the initialized value is received from the shift adder. A control circuit that outputs a latch signal to the latch circuit in accordance with the output timing, and makes the phase value immediately before the frequency change and the phase value immediately after the frequency change of the amplitude data output from the amplitude data output means substantially continuous And a frequency synthesizer. The shift addition circuit includes:
The total data is divided into a plurality of sets, and parallel processing for performing the shift addition for each set in parallel and serial processing for performing the shift addition processing for the parallel processing in cascade are combined to generate the total data Vj (j = 3. The frequency synthesizer according to claim 1, wherein lower L bits are obtained as a result of shifting and adding 0 to L-1) to the upper side by j bits. In a Gaussian noise generator that has a sine wave generator that generates a plurality of sine waves with different frequencies, and generates a Gaussian noise signal by adding and synthesizing a plurality of sine waves generated by the sine wave generator,
The sine wave generator is
Amplitude data output means for receiving L-bit data and outputting amplitude data of a sinusoidal function having a phase specified by the data;
(K + L−1) bits obtained by dividing a frequency selected from a geometric series having a u-order algebraic integer as a common ratio for an integer u larger than the number of sine waves by the frequency of a predetermined clock signal. Frequency setting means for setting data as frequency data;
A K-bit counter for counting the clock signal;
The frequency data of (K + L-1) bits from the frequency setting means is divided into L sets of K bit data whose leading bits are shifted by 1 bit, and the K bit count output of the counter and the logical product in units of bits are calculated. And L sets of product-sum calculation circuits for obtaining the total number of bits for which the calculation result is 1 for each set,
The amplitude data output means outputs the lower L bits of the total number data Vj (j = 0 to L−1) obtained by the L sets of product-sum operation circuits as a result of shifting and adding j bits to the upper side. And a shift addition circuit that outputs to
A Gaussian noise generator configured to generate a sine wave having a plurality of frequencies selected without overlapping from a geometric series having a u-algebraic integer as a common ratio. The shift addition circuit includes:
The total data is divided into a plurality of sets, and parallel processing for performing the shift addition for each set in parallel and serial processing for performing the shift addition processing for the parallel processing in cascade are combined to generate the total data Vj (j = 5. The Gaussian noise generating apparatus according to claim 4, wherein lower L bits are obtained as a result of shifting and adding 0 to L-1) by j bits to the upper side.

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