JP2996195B2 - Semiconductor device positioning method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for positioning a semiconductor device, and more particularly, to a semiconductor device having a multi-layered wiring, which is covered by an upper layer wiring from a front surface side on which a wiring pattern is formed. The present invention relates to a semiconductor device positioning method for accurately determining the position of a lower wiring pattern from above an upper wiring.

[0002]

2. Description of the Related Art With the current demand for semiconductor devices,
Various methods of positioning various semiconductor devices for failure analysis, repair, inspection, and the like have been proposed. In particular, a method of irradiating light including infrared light from the back surface or the front surface of the semiconductor device and recognizing wiring or the like by transmitted or reflected light is useful, and the method or device described below is useful. It is disclosed in the gazette.

In the method described in Japanese Patent Application Laid-Open No. 01-109735, after a wiring layer is formed on a semiconductor substrate, light including infrared light having a wavelength of 1.3 μm to 6 μm is irradiated from the back surface of the semiconductor substrate. There is described an inspection method of a wiring layer, characterized in that light transmitted through the wiring layer is detected by an infrared detector, and the covering state of the wiring layer is inspected by the transmitted light.

In Japanese Patent Application Laid-Open No. 04-194736, attention is paid to the fact that an organic compound serving as an insulating layer has an infrared light absorption spectrum peculiar to its structure, and is specially applied to each layer of a resin-based insulating layer of a multilayer wiring board. Insulation layer inspection equipment for multi-layer wiring boards, which detects non-destructive defects in the insulation layer as an image by irradiating infrared light with the absorption wavelength of the light and receiving the reflected light and imaging it. Are listed.

Further, in Japanese Patent Application Laid-Open No. 04-206927, a detector for detecting infrared rays of a specific wavelength is arranged on the back side of a Si wafer, and an aluminum film formed on the wafer from the front side of the Si wafer is arranged. Irradiation is performed on the front surface of the Si wafer by the configuration in which the infrared light is reflected on the aluminum film before etching and the infrared light is transmitted through the wafer after etching and detected by the detector. An apparatus is described that facilitates detecting the end point of etching of a formed coating.

As described above, when a failure analysis is performed on a semiconductor device having a multi-layered wiring, the position is specified using the above-described semiconductor device positioning method or apparatus, and an etching technique using an ion beam or a laser is used. It is effective to use an exfoliation technique by using the technique described above to locally remove an upper layer wiring, expose a lower layer element or wiring, and perform observation and analysis.

[0007]

However, in recent semiconductor devices, with an increase in the scale and integration of the semiconductor device, multilayer wiring has been developed, and the area of the lower wiring covered by the upper wiring has increased. In particular, in a semiconductor device in which an upper wiring having a large wiring width is patterned, the position of an analysis portion in a lower layer cannot be recognized from above the upper wiring, so that a portion to be locally removed in the upper wiring can be accurately determined. However, the problem that the analysis time increases has become apparent.

In addition, wiring correction of semiconductor devices, cross-section observation,
In the case of secondary particle images used for electron beam probing, etc., the lower wiring at a depth where the irradiated ion beam or electron beam does not reach is recognized as an image even if it is not covered by the upper wiring. There is a problem that cannot be done. In particular, in a semiconductor device in which the wiring layers are multi-layered, the area of the lower layer where a wiring pattern image cannot be observed is increasing. Therefore, there is a problem that it is extremely difficult to specify a processed portion by losing the lower layer wiring pattern image used as a guide for searching for a place.

In the description of the prior art, methods using transmission or reflection of infrared light have been described. However, these methods cannot solve the above-mentioned problems. The reason will be described below.

First, there is an inspection method disclosed in Japanese Patent Application Laid-Open No. 01-109735. In this method, infrared light is irradiated from the back side of a semiconductor device, and infrared light transmitted through Si is exposed. Infrared light transmitted through the lower layer near the wiring from the back side is blocked by the upper layer wiring having a wide wiring width, and does not appear on the front surface because the detection is performed by the detector installed on the surface side. . Therefore, the silhouette of the lower wiring cannot be obtained, and as a result, only the silhouette of the upper wiring is visualized in the infrared light image, and the lower element or wiring cannot be recognized from above the upper wiring.

An apparatus disclosed in Japanese Patent Application Laid-Open No. 04-194736 is a device which irradiates an organic compound which is an insulating layer with infrared light, receives reflected light thereof, and receives defects in the insulating layer. However, there is a method for recognizing the position of the lower layer wiring covered by the upper layer wiring from above the upper layer wiring and reflecting it in the processing location determination at the time of local removal from above the upper layer wiring. Since it is not disclosed, it is not possible to effectively perform local removal from above the upper wiring.

Finally, in the device disclosed in Japanese Patent Application Laid-Open No. 04-206927, infrared light is irradiated from the front side of the semiconductor device, and the infrared light transmitted through Si is set on the back side. Since the detection is performed by the detector, the lower layer element or wiring covered by the upper wiring cannot be recognized from above the upper wiring.

The present invention has been made in view of the above circumstances,
To provide a semiconductor device positioning method capable of accurately recognizing the position of a lower element or wiring covered by an upper wiring from above the upper wiring in the positioning of the semiconductor device, and performing accurate and efficient failure analysis. With the goal.

[0014]

According to the first aspect of the present invention,
An optical microscope image, a laser microscope image, or a secondary particle image, a method for positioning a semiconductor device using a wiring pattern image on a front surface of the semiconductor device, the method comprising: Irradiating light including infrared light having a wavelength in the range of 1.3 to 6 μm from the back surface, and transmitting the light through the Si substrate of the semiconductor device, reflecting the metal wiring of the semiconductor device, and again returning the back surface of the semiconductor device. Detecting light including the irradiated infrared light that appeared on the side, and obtaining a wiring pattern viewed from the back surface of the semiconductor device as a back wiring pattern image viewed from the back surface based on the detected light; A step of mirror-inverting the backside wiring pattern image viewed from the backside of the semiconductor device to obtain a backside wiring pattern image viewed from the front side of the semiconductor device, and from the front side of the semiconductor device. The back side wiring pattern image is superimposed on the front side wiring pattern image of the semiconductor device represented by any of the optical microscope, the laser microscope or the secondary particle image, and the And projecting and observing the semiconductor device using the front surface wiring pattern image on which the back surface wiring pattern image is projected.

Therefore, according to the present invention, light including infrared light having a wavelength of 1.3 to 6 μm is irradiated from the back surface of the semiconductor device.
After the irradiated light passes through the Si substrate, the reflected light is reflected on the metal wiring, and the light that has appeared again on the back surface side of the semiconductor device is detected. By overlaying the wiring pattern image observed from the front surface and projecting the lower wiring pattern on the front image, the upper layer wiring shows the position of the lower element and wiring covered by the upper wiring. It can be accurately recognized from the image that exists.

According to a second aspect of the present invention, in the first aspect of the present invention, the backside wiring pattern image viewed from the front surface side of the semiconductor device is selected from the group consisting of the optical microscope, the laser microscope, and the secondary particle image. Superimposing on the front surface wiring pattern image of the semiconductor device represented by, and projecting the back surface wiring pattern image on the front surface wiring pattern image,
The method further comprises a step of superimposing a part of an image commonly appearing on the front surface wiring pattern image and the back surface wiring pattern image viewed from the front side as a guide.

Therefore, according to the present invention, the front surface wiring pattern image and the back surface wiring pattern image viewed from the front surface are partially superimposed on each other as a guide. Therefore, the position of the back wiring pattern image projected on the front wiring pattern image is less likely to shift, and accurate positioning can be performed. Further, even if the overlapping position is shifted, the positional deviation can be easily corrected using the common pattern as a guide.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of a semiconductor device positioning method according to the present invention will be described below with reference to the drawings. FIG. 1A is a secondary particle image when the semiconductor device is viewed from the front side. However, the wirings 1AL and 2AL in the lower layer, which are not normally imaged, are also shown for simplicity of description (portions drawn by dotted lines). FIG. 1B is a cross-sectional view taken along a line a-b in FIG. Hereinafter, as shown in these figures, it is assumed that the semiconductor device has four wiring layers, the wiring at the uppermost layer of the semiconductor device is 4AL, the wiring one layer below this 4AL is 3AL, and The wiring in the lower layer is called 2AL, and the wiring in the lowermost layer is called 1AL. Also, the top layer of the semiconductor device can be set to the 4AL layer without specifying the wiring.
A layer immediately below this 4AL layer is called a 3AL layer, and is used to designate a layer in the same manner. In addition, silicon Si is provided under the lowermost wiring 1AL.

FIG. 2A shows an image obtained by irradiating infrared light from the back side of the semiconductor device and reflecting it on the wiring and reappearing on the back side of the semiconductor device, that is, an image of the semiconductor device. It is a figure which shows the infrared light image when it sees from a back surface side. The image 1b shown in FIG. 2B is an image obtained by mirror-inverting the portion 1a surrounded by the thick broken line in FIG. 2A and further enlarging it at a predetermined magnification.

FIG. 3A is a secondary particle image of the same portion as FIG. 2A viewed from the front side of the semiconductor device.
An image 2b shown in FIG. 3B is an enlarged image of a portion 2a surrounded by a thick broken line in FIG.

FIG. 4 shows the image 1 shown in FIG.
FIG. 5B is a view showing a step of superimposing the image 2b shown in FIG. 3B and FIG. 3B, and FIG. 5 shows the completion of the superposition step shown in FIG. It is a figure showing the state where it overlapped.

Hereinafter, a first embodiment of the method for positioning a semiconductor device according to the present invention will be described in more detail with reference to the above-described drawings.

FIG. 1A is a top view of a portion where 2AL and 1AL are arranged below 4AL which is the uppermost wiring pattern and 3AL which is a wiring pattern under the uppermost layer. When viewed from the front side, 2AL and 1AL are
4AL and 3AL indicate that they are obscured. FIG. 1B, which is a cross-sectional view taken along a line a-b in FIG. 1A, shows that wirings are arranged in four wiring layers.

FIG. 2A is a wiring pattern diagram obtained by irradiating infrared rays from the back surface of the semiconductor device. Not only the wiring patterns of the 4AL and 3AL layers but also the underlying 2AL and 1AL images are shown. It appears in. This image is obtained by irradiating light including infrared light having a wavelength of 1.3 to 6 μm from the back surface of the semiconductor device, transmitting the above-mentioned light through the Si substrate, reflecting the light on the metal wiring, and again irradiating the semiconductor device. This is obtained by detecting light appearing on the back surface side and performing image processing, and is therefore a mirror-inverted view from the front view of the semiconductor device.

Therefore, first, as shown in FIG.
The portion 1a surrounded by the thick broken line in (a) is enlarged by image processing and mirror-inverted. In the enlarged image 1b, wiring patterns of the 4AL layer and the 3AL layer that can be recognized even in the secondary particle image of FIG. 3B described later are displayed as 4AL1 and 3AL1, respectively. This mirror surface inversion is performed so that the wiring pattern direction is the same as the direction viewed from the front surface of the semiconductor device.

FIG. 3A is a wiring pattern diagram of a secondary particle image at the same position as FIG. 2A as viewed from the front surface of the semiconductor device. This figure is different from FIG. 2 (a), where 1AL and 2AL in the lower layer are 4AL2 and 3AL2
And is not visible on this image. When wiring correction processing or the like is performed on 2AL and 1AL hidden by 4AL2 and 3AL2 using the front surface image as shown in FIG. 3A, 2A from the top of 4AL2 as the uppermost layer.
It is necessary to know the positions of L and 1AL.

For this reason, as shown in FIG. 3B, first, in FIG. 3A, the same portion 2a as the portion 1a surrounded by the thick broken line in FIG. 2A is enlarged by image processing. An image 2b enlarged at the same magnification as that of FIG.

Then, as shown in FIG. 4, (b) of FIG.
The image 1b shown in FIG. 2B is superimposed on the image 1b shown in FIG. 3B and the image 2b shown in FIG.
Project the wiring pattern diagram. At the time of superposition, 4A which is a pattern commonly appearing in the image 1b and the image 2b
Using the L1 and 3AL1 wiring patterns as a guide, the reference patterns 4AL1 and 3AL1 are overlapped. Therefore, the positions of the other wirings shown in FIG. 2B correspond to the positions of the wirings in FIG.

As a result, as shown in FIG. 5, the positions of 2AL and 1AL that do not appear on the secondary particle image of FIG. 3B are superimposed on the infrared light image 1b of FIG. 2B. This allows accurate determination of the processing position for 2AL and 1AL hidden by 4AL2 and 3AL2. Note that the method for positioning a semiconductor device described in the first embodiment can be applied to laser processing for correcting wiring using an optical image, and similar effects can be obtained. That is, FIG. 3A is an optical image viewed from the front side of the semiconductor device, FIG. 3B is an enlarged optical image by image processing, and FIGS. And an optical image observed from the front side is superimposed on the infrared light image obtained from the back side.

Next, a second embodiment of the method for positioning a semiconductor device according to the present invention will be described with reference to the drawings.
FIG. 6 shows an infrared image obtained from the back surface of the semiconductor device by superimposing the infrared light images of 1AL1 and 2AL1, which are originally covered by 4AL3 and 3AL3 when viewed from the front surface side of the semiconductor device, by the above-described method. This is a secondary particle image that appears on the front surface of the lever.

In the second embodiment, as shown in FIG. 7 (b), the repair and processing location is determined when the upper wiring pattern serving as a guide for positioning does not appear on the processing magnification screen. Is the way.

First, in FIG. 6, since the infrared light image is superimposed on the secondary particle image using the wiring patterns of 4AL4 and 3AL4 as a guide, the position of 1AL1 can be recognized. Next, the image position is adjusted by moving the 1AL1 to be processed to the center of the superimposed screen, that is, moving it in the direction of the arrow in FIG.

Next, as shown in FIG. 7A, after the 1AL1 to be processed is moved to the center of the superimposed image, an area 3a including the processing object (portion surrounded by a thick broken line) is moved to the position shown in FIG. (B), the superimposed image is enlarged to the processing magnification. At this time, the secondary particle image as the processed image and the infrared light image superimposed on the secondary particle image are enlarged while being superimposed on the center point of the screen. When the processing magnification is set to a desired value, the ion beam 26 is irradiated to the processing area 25 of 1AL1 represented by the infrared light image to perform the etching processing. In the etching process using the ion beam 26, the irradiation position of the beam may be shifted due to instability of the ion beam, charge-up of a sample to be processed, or the like. It needs to be corrected early.

Therefore, when performing the etching process while monitoring the screen shown in FIG. 7B, the process is interrupted at predetermined time intervals to correct the above-mentioned positional deviation, and the process is interrupted at every interruption. Observing the secondary particle image and the infrared light image at low magnification, obtaining a superimposed image as shown in FIG. 8, observing the actual 1AL1 position and the degree of overlap between the processing locations 25, and determining the position between the two. Correct any deviation.

FIG. 8 shows 4AL4 which is a guide for positioning.
FIG. 7 is a diagram in which a secondary particle image and an infrared light image at such a low magnification that 3AL4 and 3AL4 appear on the screen are superimposed. In this figure, by using 4AL4 and 3AL4 as a guide,
The degree of overlap between the secondary particle image and the infrared light image can be confirmed. Further, in FIG.
At the processing location 25 irradiated with 6, a hole is dug by etching, and the hole appears as the processing location 25 in the secondary particle image of FIG. The hole formed by this etching is compared with the position of 1AL1 represented by the infrared light image, and the coincidence between the two is confirmed. When the agreement is confirmed, the process returns to FIG. 7B, and the etching process is restarted. If the position shift has occurred, after the position is corrected, the process returns to FIG. 7B and the etching process is restarted.

Therefore, according to this embodiment, even during the processing, the processing position can be confirmed accurately, so that the repair and inspection of the semiconductor device can be performed more accurately and efficiently. .

[0037]

As is apparent from the above description, according to the present invention, in a semiconductor device having a multi-layered wiring structure, when viewed from the front surface side where the wiring pattern is formed, the semiconductor device is covered by the upper layer wiring. A method of positioning a semiconductor device, which can accurately determine the position of a lower wiring pattern to be performed and can greatly contribute to a short TAT for failure analysis, which has become increasingly difficult due to the progress of multilayer wiring. Can be provided.

Further, the position of both images can be confirmed more accurately by using a pattern common to the image obtained from the front side of the semiconductor device and the image obtained from the back side as a guide. A method for positioning a semiconductor device capable of positioning the device can be provided.

[Brief description of the drawings]

1A and 1B are diagrams illustrating a structure of a semiconductor device, wherein FIG. 1A is a diagram illustrating a secondary particle image viewed from a front surface side of the semiconductor device, and FIG. 1B is a diagram illustrating a semiconductor device illustrated in FIG. FIG.

2A and 2B are diagrams illustrating a structure of a semiconductor device, and FIG. 2A is a diagram illustrating an infrared light image viewed from a back surface side of the semiconductor device;
(B) is a diagram showing an image obtained by mirror-inverting and enlarging the infrared light image shown in (a).

3A and 3B are diagrams illustrating a structure of a semiconductor device, in which FIG. 3A is a diagram illustrating a secondary particle image of the same portion as that illustrated in FIG. (b) is a view showing an enlarged image of the secondary particle image shown in (a).

FIG. 4 is a view showing a process of superimposing the image shown in FIG. 2B and the image shown in FIG. 3B.

FIG. 5 is a diagram showing an image in a state where a superposition process shown in FIG. 4 is completed.

FIG. 6 is a diagram showing an image in a state where an infrared light image and a secondary particle image are superimposed.

7A and 7B are diagrams illustrating a structure of the semiconductor device, and FIG. 7A is a diagram illustrating an image obtained by translating the image illustrated in FIG. 6;
FIG. 2B is a view illustrating a process when processing the semiconductor device by enlarging the image illustrated in FIG.

FIG. 8 is a diagram showing an image to be confirmed when correcting positional deviation.

[Explanation of symbols]

4AL, 4AL1, 4AL2, 4AL3, 4AL4 Wiring pattern of the uppermost layer of the semiconductor device 3AL, 3AL1, 3AL2, 3AL3, 3AL4 Wiring pattern of the layer one layer below the uppermost layer of the semiconductor device 2AL, 2AL1 2 from the uppermost layer of the semiconductor device Wiring pattern of lower layer 1AL, 1AL1 Wiring pattern of lower three layers from the uppermost layer of semiconductor device 25 Processing location 26 Ion beam

Claims (2)

(57) [Claims] 1. A semiconductor device positioning method for positioning a semiconductor device by using a wiring pattern image on a front surface of the semiconductor device, which is represented by an optical microscope image, a laser microscope image, or a secondary particle image. Irradiating light including infrared light having a wavelength in the range of 1.3 to 6 μm from the back surface of the semiconductor device; and transmitting the light through the Si substrate of the semiconductor device, and reflecting the light on the metal wiring of the semiconductor device; Detecting the light including the irradiated infrared light again appearing on the back surface side of the semiconductor device; and forming the wiring pattern viewed from the back surface of the semiconductor device based on the detected light as a back wiring pattern image viewed from the back surface. Obtaining the back surface wiring pattern image as viewed from the back surface of the semiconductor device, and obtaining a back surface wiring pattern image as viewed from the front surface side of the semiconductor device, The back side wiring pattern image viewed from the front side is superimposed on the front side wiring pattern image of the semiconductor device represented by any one of the optical microscope, the laser microscope, and the secondary particle image. Projecting the backside wiring pattern image on the surface wiring pattern image, and processing and observing the semiconductor device using the front surface wiring pattern image on which the backside wiring pattern image is projected. Semiconductor device positioning method. 2. A front surface wiring pattern of a semiconductor device, wherein a back surface wiring pattern image viewed from the front surface side of the semiconductor device is represented by any one of the optical microscope, the laser microscope, and the secondary particle image. Superimposing on the image, projecting the back wiring pattern image on the front wiring pattern image, the front wiring pattern image and the back wiring pattern image viewed from the front side 2. The method according to claim 1, further comprising the step of superimposing a part of the image which appears in common as a guide.