JP2996099B2 - Scan line interpolation circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a conversion technique of a television system for converting a scanning line between different television systems, and more specifically, to NTS.
EDT from systems with relatively few scanning lines such as C and PAL
The present invention relates to a scanning line interpolation circuit suitable for up-conversion to a system having relatively many scanning lines such as V and HDTV.

[0002]

2. Description of the Related Art In order to view an image based on an image signal of a normal resolution such as the NTSC system with a high-vision or EDTV system receiver, conversion of a television system is required. The number of scanning lines in the NTSC system is 525, that in the high-vision system is 1,125, and that in the EDTV system is 1,050. Therefore, when converting an image of the NTSC system to a high-vision system or the like, it is necessary to simply up-convert the image to almost twice as many scanning lines.

In such an up-converter, in order to convert all NTSC signals having a small amount of information into a higher-level television system, interpolation in a field and interpolation in a frame are selectively used according to the motion of an image. ing. These two interpolation techniques have the following features. Intra-frame interpolation-an interpolation method for still images. The vertical band of the signal frequency is 525 (TV lines) of the NTSC system. When a moving image is converted in this manner, moving vertical lines are erroneously converted into jaggies. Intra-field interpolation—an interpolation technique for moving images. The vertical frequency band becomes half of the intra-frame interpolation, and the high frequency component of the vertical band is erroneously converted to another band.

Among these, the following two methods are known as intra-field interpolation to which the present invention relates. A method of taking an average value of pixels on upper and lower two lines in a field and using the average value as an interpolated value of a line between the two lines (1993 Annual Meeting of the Institute of Television Engineers of Japan, 5-
8, "Development of new scanning line conversion method"). A method of performing high-quality interpolation using the correlation in the oblique direction in the field (Japanese Patent Laid-Open Nos. 4-343590 and 4-35).
No. 5581).

[0005]

However, the above background art has the following disadvantages. (1) The above-described method Since only interpolation using upper and lower pixel average values is performed, accurate interpolation cannot be performed in an image portion having a high vertical frequency, that is, an image portion that changes rapidly in the vertical direction, and diagonal lines are jagged. turn into. FIG. 8A shows the state. This figure shows that the scanning line is doubled by interpolating the CZP (circular zone plate) of NTSC with the average value of the upper and lower pixels, and the vertical direction corresponds to the vertical frequency and the horizontal direction corresponds to the horizontal frequency. The center is a horizontal and vertical frequency “0”. In the high vertical frequency portion of the field indicated by hatching in FIG.
As shown in an enlarged manner in FIG. As described above, the vertical band that can be accurately interpolated is narrow.

[0006] (2) The above-mentioned method [1] According to this, as shown by Db and Dd in FIG. 9A, the detection of the correlation in the oblique direction is performed at a position two pixels apart in the horizontal direction. According to this method, in the case of a diagonal line having a width of two or more horizontal pixels as shown in FIG. 7B, the correlation in the same direction as the diagonal line becomes small as indicated by an arrow in FIG. Therefore, correct interpolation can be performed.

However, in the case of a diagonal line having less than two horizontal pixels as shown in FIG. 1C, the correlation in the direction opposite to the diagonal line becomes small as indicated by the arrow in FIG. Therefore, erroneous interpolation is performed. As a result,
It can be determined in which direction the inclination is in a quarter of the band of the sampling frequency fs.
Interpolation can be performed accurately up to a quarter of the band.
FIG. 3D shows an example of the case of CZP. In the frequency domain hatched in the figure, the correlation in the oblique direction is turned back, and the interpolation in the reverse direction is performed. As described above, the horizontal band in which accurate interpolation can be performed is narrow.

The present invention focuses on the above points, and provides a scanning line interpolation circuit capable of performing accurate interpolation in a wider horizontal band and improving the image quality of an image after interpolation. Its purpose is to provide.

[0009]

In order to achieve the above object, the present invention reduces the number of pixels of an input image in the horizontal direction to two.
With respect to the doubled image, the position of the pixel having the strongest interphase among the adjacent pixels located in the vertical direction and a plurality of diagonal directions centering on the vertical pixel position to be interpolated is used. Are interpolated. In another invention,
After that, the number of pixels in the horizontal direction of the
/ 2. The above and other objects, features and advantages of the present invention will become apparent from the following detailed description and the accompanying drawings.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The scanning line interpolator of the present invention can have many embodiments, but an appropriate number of embodiments are shown and described in detail. <Outline of Embodiment> First, an outline of an embodiment will be described with reference to FIGS. In this embodiment, the horizontal frequency band (FIG. 9D) using the image (pixel) correlation in the oblique direction is expanded from fs / 4 to fs / 2.

As described above, the reason why the horizontal band of the interpolation method using the correlation in the oblique direction is narrow is that the correlation in the oblique direction is detected at a position two pixels away from the sample point. Therefore, in this embodiment, before the correlation determination, the horizontal pixels of the input image shown in FIG. 1A are doubled as shown in FIG. And in this state,
The interpolation using the vertical and diagonal correlations is performed as shown in FIG. This doubles the number of scanning lines (the number of pixels) in the vertical direction, as shown in FIG. Thereafter, the number of pixels is halved in the horizontal direction, and the number of pixels in the vertical direction is doubled as shown in FIG.

FIG. 2 shows a basic configuration of a circuit for performing such processing. FIG. 1B shows only the interpolation block using the correlation in the vertical and diagonal directions in the configuration of the background art described above. On the other hand, in the embodiment, as shown in FIG. 3A, a block for doubling the pixels in the horizontal direction, an interpolation block using the correlation in the vertical and diagonal directions, and thinning out the pixels in the horizontal direction by half. Blocks are included.

<Configuration of Embodiment> Next, a specific configuration of the embodiment will be described with reference to FIG. In FIG. 1, for example, an image signal of the NTSC system is supplied to an A / D converter 1.
0 is input. This A / D converter 1
The output of 0 is directly connected on the one hand to the memory 12. On the other hand, the output side of the A / D converter 10 has a horizontal pixel number doubling circuit 14 and a vertical pixel interpolation circuit 1
6, a horizontal pixel number 1/2 circuit 18 and a memory 20 connected in series. The outputs of the memories 12 and 20 are both connected to a selection switch 22, and the output of the selection switch 22 is connected to a D / A converter 24. In addition, if necessary, the selection switch 22 and the D / A converter 2
4, an interlacing circuit 26 is provided.

Of the above components, the horizontal pixel number doubling circuit 14 includes, for example, as shown in FIG. 4, a series circuit of simple delay elements T and multiplication circuits K1 to K4 to extract their outputs.
K6, FI by adder SUMA adding these outputs
It is composed of an R filter and a changeover switch SWA. The FIR filter performs coefficient multiplication and addition on a plurality of horizontally adjacent pixels. The output of the FIR filter and the input with a constant delay are alternately selected and output at twice the frequency of the input signal by the changeover switch SWA, thereby doubling the number of horizontal pixels.

The vertical pixel interpolation circuit 16 is disclosed in, for example,
In the method disclosed in Japanese Unexamined Patent Publication No. 343590/1991, values are compared between three adjacent pixels in each of the upper and lower horizontal lines located in the vertical direction and the oblique direction of the position to be interpolated, and the pixel having the closest correlation is determined. This is a circuit for interpolating a vertical pixel by a method of obtaining an interpolation pixel value from those pixel values assuming that the pixel is a strong pixel.

The horizontal pixel number 1/2 circuit 18 is, for example, as shown in FIG.
As shown in the figure, the circuit is composed of a series circuit of simple delay elements T, multiplication circuits KA to KE for extracting their outputs, an FIR filter formed by an addition circuit SUMB for adding these outputs, and a changeover switch SWB. After the band is limited by the FIR filter, the input is selected and output at half the frequency by the changeover switch SWB, whereby the number of pixels in the horizontal direction is reduced to 2.

The memory 12 stores the input signal as it is, and the memory 20 stores the signal interpolated in the vertical direction. Select switch 22
Is for alternately selecting and outputting the data stored in the memories 12 and 20 for each horizontal line.

The interlacing circuit 26 is a circuit required for an HDTV signal. For example, as shown in FIG. 6, the delay circuit 26 delays an input by one horizontal line (1H).
A, average value circuit 26B, field changeover switch 26C
It is constituted by. For the image of the first field, the field changeover switch 26C is switched to the side a, and for the image of the second field, the field changeover switch 26C is switched to the side b, so that interlacing is performed. Note that the delay circuit 2
6A, a vertical filter that creates a new horizontal line in the middle of the input horizontal line may be used instead of the average value circuit 26B.

Referring to FIG. 7, interlacing circuit 26
In the operation described above, the input image signal of the first field and the image signal of the second field of the NTSC are arranged in the vertical direction as shown in FIG. As shown in the figure, an interpolated image signal is present at an intermediate position in the vertical direction of an image signal existing from the beginning. In the case of HDTV, the number of scanning lines is about twice as large as that of NTSC, so that an additional line is required between the lines shown in FIG. Therefore, as shown by an arrow in FIG. 2A, an average value of signals before and after one horizontal line is obtained, and this is set as a line of the second field of the HDTV as shown in FIG. 2B.

<Operation of the Embodiment> Next, the operation of the embodiment configured as described above will be described. For example, an NTSC image signal is converted into a digital signal by the A / D converter 10 and then written directly to the memory 12 on the one hand and supplied to the horizontal pixel doubling circuit 14 on the other hand. In the horizontal pixel doubling circuit 14, an interpolation pixel in the horizontal direction is generated (see FIG. 1B), and an image signal whose pixels are increased twice in the horizontal direction is supplied to the vertical pixel interpolation circuit 16.

The vertical pixel interpolation circuit 16 compares three adjacent pixels of the line before and after the interpolation position in the vertical direction in the image increased in the horizontal direction (see FIG. 1C), and determines the pixels in the vertical direction. Interpolated (see Fig. 1 (D)), horizontal pixel number 1
The signal is supplied to a / 2 conversion circuit 18. As described above, the interpolation process using the diagonal correlation in the vertical direction is performed while the number of pixels in the horizontal direction is doubled. For this reason, as shown in FIG. 1C, the correlation in the oblique direction is detected at a position four pixels apart, and the horizontal band is expanded. next,
In the horizontal pixel halving circuit 18, the number of pixels in the horizontal direction is thinned out by half (see FIG. 1E) and written to the memory 20.

The image signals stored in the memories 12 and 20 are alternately output line by line by the selection switch 22.
At this time, signals are read from the memories 12 and 20 by the ED
This is performed at the timing of a high definition image signal such as TV or HDTV. The read image signal is converted into an analog signal by the D / A converter 24, and then a synchronization signal is added by a synchronization adding circuit (not shown) to obtain a high-definition image signal.
In the case of HDTV, the interlacing processing shown in FIG.

<Effects of Embodiment> As described above, according to this embodiment, the following effects can be obtained. (1) Compared with the vertical pixel interpolation method of detecting a correlation at a position separated by two pixels as described in the background art, accurate interpolation can be performed in a double horizontal band, thereby performing higher quality television system conversion. be able to. (2) Limit band 0 to f with respect to sampling frequency fs
Accurate interpolation is possible up to s / 2 (see FIG. 9D).

<Other Embodiments> The present invention can be variously modified based on the above disclosure, and includes, for example, the following. (1) In the above embodiment, the vertical interpolation of the image signal of the NTSC system is mainly performed, but the present invention can be similarly applied to other systems such as PAL. (2) If the clock frequency at the time of D / A conversion of the image signal is high and the number of horizontal pixels of the output image is twice the number of horizontal pixels of the input image, the horizontal pixel
It is also possible to omit the 1/2 circuit 18. (3) Various changes can be made to achieve the same effect, for example, processing of digitally converted image signals by software using a microprocessor or the like.

[0025]

As described above, according to the present invention, after doubling the number of pixels in the horizontal direction, scanning line interpolation using the correlation in the oblique direction is performed, or thereafter, the number of pixels in the horizontal direction is calculated. Is reduced to 1/2, accurate interpolation can be performed in a wider horizontal band, and the image quality of the image after the interpolation can be improved.

[Brief description of the drawings]

FIG. 1 is a diagram showing a basic interpolation processing method according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a basic device configuration of the embodiment.

FIG. 3 is a block diagram illustrating a configuration of an embodiment.

FIG. 4 is a block diagram illustrating an example of a horizontal pixel number doubling circuit according to the embodiment;

FIG. 5 is a block diagram illustrating an example of a circuit for reducing the number of horizontal pixels to one half according to the embodiment;

FIG. 6 is a block diagram illustrating an example of an interlacing circuit according to the embodiment;

FIG. 7 is a diagram illustrating the operation of the interlacing circuit.

FIG. 8 is a diagram illustrating a relationship between interpolation and a frequency band according to the background art.

FIG. 9 is a diagram illustrating a relationship between interpolation and a frequency band according to the background art.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 ... A / D converter 12 ... Memory 14 ... Horizontal pixel number doubling circuit (pixel number doubling means) 16 ... Vertical pixel interpolation circuit (scanning line interpolation means) 18 ... Horizontal pixel number 1/2 circuit ( 20: memory 22: selection switch 24: D / A converter 26: interlace circuit 26A: 1H delay circuit 26B: average value circuit 26C: field changeover switch T: delay elements K1 to K6, KA to KE: Multiplication circuit SUMA, SUMB: Addition circuit SWA, SWB: Switch

Claims (2)

(57) [Claims] 1. A pixel number doubling means for doubling the number of pixels in a horizontal direction of an input image; thereby, a vertical direction centering on a vertical pixel position to be interpolated with respect to the doubled image And a plurality of adjacent pixels located in the oblique direction,
A scanning line interpolation circuit comprising: a scanning line interpolation unit for interpolating a vertical pixel at the position by using a pixel in the strongest direction between phases. 2. A pixel number doubling means for doubling the number of pixels in the horizontal direction of an input image; thereby, in the vertical direction centering on a vertical pixel position to be interpolated with respect to the doubled image. And a plurality of adjacent pixels located in the oblique direction,
A scanning line interpolating means for interpolating a vertical pixel at the position by using a pixel in the strongest direction between the phases; thereby reducing the number of pixels in the horizontal direction of the image interpolated by the scanning line to 1/2, A scanning line interpolation circuit comprising: