JP2993570B2 - Digital / analog conversion circuit - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a digital / analog conversion circuit for converting a digital signal to an analog signal.

[Prior Art] FIG. 2 shows a conventional digital / analog conversion circuit 1 based on voltage synthesis. In the digital / analog conversion circuit 1, the input digital signal gp = ｛am am-1
A DC voltage Ei corresponding to each bit ai (i is 0 to m) of a1 a0 is formed by the ladder resistor 2 in advance. The switch circuit 4i corresponding to each bit ai is opened and closed according to the logic of each bit ai of the digital signal gp input and latched by the register circuit 3, and only the DC voltage corresponding to the bit of logic "1" Is given to the summation calculator 5 to perform the summation, and the calculation result is transmitted as an output analog signal h.

The conversion by the digital / analog conversion circuit 1 shown in FIG. It becomes as shown in.

The voltage Em in FIG. 2 is a DC fixed voltage (also a power supply voltage of this circuit) corresponding to the most significant bit am,
As described above, the voltage Ei corresponding to the other bits is formed from the voltage Em using the ladder resistor 2. However, in addition to the one using the ladder resistor 2 for this formation, there is one using an active element. The register circuit 3 has a set signal SET as a latch command for the input digital signal gp.
Is also given. Therefore, in this specification, the digital / analog conversion circuit 1 shown in FIG. 2 will be used as one block as shown in FIG. Conversion unit).

By the way, in practice, in the digital / analog conversion unit 1, the values g0, g1,... Gr... Change at t = 0, T,. In many cases, a digital signal sequence (represented by gr if necessary) shown in FIG. 5 is input, and in synchronization with this, the digital signal is converted into a unit as shown in FIG. 1 is taken in.

In this case, each switch circuit 4i in the unit 1 corresponding to the bit of the digital signal gr having the logic “1” is switched at every sampling period, and the time until the next switching is performed.
The open / closed state is maintained for rT to (r + 1) T. Therefore, as shown in FIG. 4B, the output analog signal h becomes the input digital signal g during the time rT to (r + 1) T.
The analog value hr corresponding to r is maintained (for easy understanding of the relationship between the analog value hr and the digital signal gr, in each figure, the reference symbol hr is denoted by the corresponding reference symbol gr. Represented). That is, the output analog signal h is a step-like analog signal. Generally,
Thereafter, as shown in FIG. 4 (C), the step-like analog signal is smoothed and applied to the next stage.

[Problems to be Solved by the Invention] As described above, in the conventional configuration, the open / close state of each switch circuit 4i is controlled in accordance with the digital signal gr for each sampling period T.

Ideally, there should be no variation between the switch circuits 4i and their operations should be completely synchronized.However, in practice, variations between the switch circuits 4i cannot be avoided, and slight shifts in operation timing should be avoided. Can not. The output analog signal h becomes unstable during such a shift period of the operation timing by each switch circuit 4i. As described above, the effect is reduced by smoothing the output analog signal h and sending it to the next stage, but it is desired that the output analog signal h itself be stable in order to further improve the conversion accuracy. In addition, noise due to a shift in switching timing between switch circuits becomes a problem.

Incidentally, in the future, the sample period T tends to be shorter. For example, in the case of a device that handles image data, the number of pixels tends to increase to improve image quality.However, increasing the number of pixels increases the time required to scan between horizontally adjacent pixels, and thus the pixel data. This means shortening the sample period. As the cycle T becomes shorter, the influence of the timing shift period of each switch circuit 4i becomes relatively large. Even if the cycle T is made shorter, the conventional configuration cannot improve the accuracy as expected. .

The present invention has been made in view of the above points,
The noise component of the output analog signal caused by the variation of the switch circuit can be reduced. That is, an object of the present invention is to provide a digital / analog conversion circuit capable of further improving the conversion accuracy compared to the related art.

[Means for Solving the Problems] In order to solve such problems, in the present invention, a digital / analog conversion circuit is constituted by the following means.

That is, n digital / analog conversion units that incorporate a switch circuit corresponding to each bit of an input digital signal and convert an input digital signal into an analog signal, and convert n input digital signal data into n digital / analog There are provided data distribution means for distributing the data to the conversion units in a predetermined order, and addition means for combining and outputting the analog signals output from the respective digital / analog conversion units.

Also, n for each digital / analog conversion unit
Power supply means for forming a power supply voltage which fluctuates at a cycle of n times the sample period of the input digital signal, and instructing each digital / analog conversion unit to take in the input digital signal And
Set signal forming means for forming n set signals whose instruction timing is substantially the minimum value of the corresponding power supply voltage.

[Operation] In the present invention, the data of the input digital signal is distributed to the digital / analog conversion units by the data distribution means in a predetermined order. Each digital / analog conversion unit fetches given data based on the set signal provided from the set signal forming means, changes the state of a built-in switch circuit group, and converts it into an analog signal. The analog signals converted by the respective digital / analog conversion units are combined by the adding means and output to the next stage.

Each digital / analog conversion unit is operated by the power supplied from the power supply means, and this power is different and fluctuates in each digital / analog conversion unit. The power supply fluctuation is such a fluctuation that the value becomes almost minimum at the timing when the set signal instructs the data fetch. That is, when the switching circuit group is switched inside each digital / analog conversion unit, the size is small, and the influence of a slight shift in switching timing between the switching circuits is suppressed by suppressing the power supply voltage.

Example 1 Example 1 First, Example 1 of the present invention will be described with reference to the drawings.

FIG. 1 shows the configuration of the main part of the first embodiment (this is also a diagram showing the configuration of the main part of the second and third embodiments described later). As shown in FIG. 1, the digital / analog conversion circuit 10 of this embodiment comprises two digital / analog conversion units (see FIGS. 2 and 3) 11e and 11o.
It has.

A data distribution circuit (not shown) is provided at a stage preceding the conversion units 11e and 11o. The data distribution circuit alternately distributes the sample values g0, g1,... Of the input digital signal. An input data sequence g0 starting at a value g0 and appearing every 2T, which is twice the allocated sample period T,
g2,... are input to the first digital / analog conversion unit 11e, and the other input data strings g1, g3,.
.. Are input to the second digital / analog conversion unit 11o.

Therefore, the set signals SETe and SETo which need to be synchronized with the data sequence for each conversion unit 11e and 11o
Is also significant as a period 2T with twice the sample period T. Here, the set time t for the head data g0
Is 0, the first digital / analog conversion unit
The significant time of the set signal SETe for 11e is 0, 2T, 4T ...
, And the significant times of the set signal SETo for the second digital / analog conversion unit 11o are 1T, 3T,.

An output analog signal he obtained by the first digital / analog conversion unit 11e converting the input data sequence g0, g2,.
Are supplied to the adder 12, and the output analog signal ho obtained by the second digital / analog conversion unit 11o converting the input data strings g1, g3,... Is also supplied to the adder 12. Adder 1
2 adds the applied two analog signals he and ho to form and output an output analog signal h.

This first embodiment, as described above, uses two digital /
An analog conversion unit 11e and 11o are provided, and each data value of the input digital signal is distributed to each unit 11e and 1o.
1o, and add the obtained analog signals he and ho to the adder
It is characterized in that it is added and synthesized in 12 and output. Further, the first embodiment has the following features. The second point is that the power supply voltage applied to each digital / analog conversion unit 11e, 11o, and thus the voltage Eme, Emo corresponding to the most significant bit fluctuates (AC voltage) instead of a fixed value (DC voltage).
It has the characteristics of

FIG. 6 shows voltage waveforms Eme and Emo corresponding to the most significant bit in the first embodiment. Most significant bit corresponding voltage Eme for first digital / analog conversion unit 11e
Has a waveform shape shown in FIG. 6A, and can be expressed by the following equation: Eme = Em sin ² (πt / 2T) (2) The most significant bit corresponding voltage Emo for the second digital / analog conversion unit 11o has a waveform shape shown in FIG. 6B, and is expressed by the following equation: Emo = Em cos ² (πt / 2T) (3) be able to. Here, Em is the maximum value of each waveform, and can be expressed by the following equation: Em = Eme + Emo (4).

Here, as is clear from the equations (A) and (2) in FIG. 6, the most significant bit corresponding voltage Eme to the first digital / analog conversion unit 11e is set by the internal register circuit when the set signal SETe becomes significant. The waveform has a minimum value of 0 at the timing of capturing the data value. Similarly, the most significant bit corresponding voltage Emo for the second digital / analog conversion unit 11o also has a waveform that takes the minimum value 0 at the timing when the set signal SETo becomes significant and the internal register circuit takes in the data value. .

The highest-order bit corresponding voltages Eme and Emo are set to the set signals SETe and
The reason why the minimum value is set to 0 at the timing when SETo becomes significant is that if the voltage becomes 0 even if the switch circuit group is switched to a significant value, the converted analog signals he and ho also become almost 0 and each switch circuit becomes This is because a slight shift in the switching timing due to the variation in the operation does not pose a problem.

Even if the voltages Eme and Emo corresponding to the most significant bit are 0, if the set signals SETe and SETo become significant, each of the digital / analog conversion units 11e and 11o fetches the data value and outputs the internal data based on the data value. Switches the switch circuit state. This switched switch circuit state lasts for a period 2T, which is twice the sampling period T. Even if the switch circuit state is the same, since the voltages Eme and Emo corresponding to the most significant bit have changed, the analog signals he and ho from the units 11e and 11o during that period also change.

FIG. 7 shows a converted analog signal for a certain data value. FIG. 8 shows a converted analog signal for a data string.

FIG. 7 (A) shows the data for the data value g2r set at time 2rT relating to the first digital / analog conversion unit 11e, and FIG. 7 (B) shows the second digital / analog conversion unit.
It shows a data value g2r + 1 set at time (2r + 1) T relating to the analog conversion unit 11o.

As is apparent from these waveforms, the waveform has a sinusoidal waveform shape with a period of 2T and a maximum value when the time T has elapsed from the set time. Then, the peak value (indicated by the symbol g2r) or (indicated by the symbol g2r + 1) is a converted value of the data value g2r or g2r + 1 with respect to the maximum value Em of the most significant bit corresponding voltage Eme or Emo.
Further, when one converted analog signal has a peak value, the other converted analog signal has a bottom value (0).

Therefore, the first digital / analog conversion unit 11e
Outputs an analog signal he as shown in FIG. 8A for the data strings g0, g2,..., And the second digital / analog conversion unit 11o outputs the data strings g1, g3,. An analog signal ho as shown in FIG. 8 (B) is output. The output analog signal h obtained by combining these analog signals he and ho is as shown in FIG. 8 (C).

In FIG. 8, the data value and the converted peak value corresponding to the data value are shown on the same time axis and at the same height.

From FIG. 8 (C), the input digital signals g0, g1,... G2r, g
It can be seen that 2r + 1... Are accurately converted into the analog signal h.

As described above, the feature of the first embodiment is that the data sequence of the input digital signal is alternately sorted to obtain different units 11e and 1e.
It is to combine after performing the conversion processing at 1o, and to vary the most significant bit corresponding voltages Eme and Emo. Therefore, the formation configuration of the most significant bit corresponding voltages Eme and Emo and the formation configuration of the set signals SETe and SETo are naturally different from those of the related art.

Therefore, the configuration for forming the most significant bit corresponding voltage and the configuration for forming the set signal will be described below together with the operation.

FIG. 9 is a block diagram showing this component, and FIG.
The figure is the signal waveform diagram.

An oscillator (for example, a crystal oscillator) 20 regularly oscillates and outputs a sine wave signal Sa (FIG. 10 (A)) whose period is 4T, 4 times the sample period T. This sine wave signal Sa is an extremely low positive voltage oscillation signal when a crystal oscillator is applied. This signal Sa is passed through the capacitor 21 so that the DC component is cut off and becomes a positive and negative uniform sine wave signal Sb (FIG. 10 (B)). The sine wave signal Sb is directly supplied to the multiplier 22 and also supplied to the multiplier 22 via the volume 23, and is squared by the multiplier 22. Here, a fixed voltage Em is given to the multiplier 22 as a reference voltage, and the multiplier 22 outputs a sine wave square signal Sc having a peak value of Em.
(FIG. 10 (C)) is output.

The sine wave square signal Sc is a sine wave signal before squaring.
Its period is 1/2 compared to Sb.

This sine wave square signal Sc is supplied to one subtractor 24 as a subtracted input and to the other subtractor 25 as a subtracted input. The subtractor 24 subtracts 0 from the signal Sc and outputs a subtraction output Se (FIG. 10C) as the most significant bit corresponding voltage Eme to the first digital / analog conversion unit 11e. The subtractor 25 subtracts the sine wave square signal Sc from the fixed voltage Em and outputs a subtraction output Sd (FIG. 10D) as the most significant bit corresponding voltage Emo for the second digital / analog conversion unit 11o.

Note that the other most significant bit corresponding voltage Emo can be obtained by subtracting one most significant bit corresponding voltage Eme from voltage Em, because the following expression (4) modified from the above expression (Emo = Em−Eme... ( It is clear from 5). In addition, the subtractor 24 is theoretically unnecessary, but is provided as described above from the viewpoint of aligning the phase relationship between the two most significant bit corresponding voltages Eme and Emo, that is, from the balance of the signal processing system. To be precise, the signals Sc and Se
Means that there is a phase shift corresponding to the processing time of the subtractor 24.

The voltage Eme is provided to the inverting input terminal of the comparator 26, and the other voltage Emo is provided to the inverting input terminal of the comparator 27. The non-inverting input terminals of these comparators 26 and 27 have a fixed voltage Em.
Voltage which is almost zero by dividing the voltage by the volume 28
V0 is given. The comparator 26 forms a narrow pulse signal Sf (FIG. 10 (E)) which takes a significant logic "1" when the voltage Eme is smaller than the reference voltage V0 and outputs the pulse signal Sf to the first digital / analog conversion unit 11e. The comparator 27 outputs a set signal SETe, and the comparator 27 outputs a narrow pulse signal Sg (10th pulse) that takes a significant logic “1” when the voltage Emo is smaller than the reference voltage V0.
(F) is formed and output as a set signal SETo to the second digital / analog conversion unit 11o.

Each set signal SETe, SETo is required to be significant when the corresponding voltage Eme, Emo is 0,
In actuality, since delays occur in various circuits, in this embodiment, as described above, the corresponding voltages Eme and Emo are set to become significant shortly before becoming zero.

The most significant bit corresponding voltages Eme and Emo obtained by the configuration shown in FIG. 9 and the set signals SETe and SETo
Are supplied to the corresponding conversion units 11e and 11o to perform the digital / analog conversion described above.

According to the digital / analog conversion according to the first embodiment, at the timing of switching the state of the switch circuit group in the digital / analog conversion units 11e and 11o, the most significant bit corresponding voltages Eme and Emo are 0. Even if there is a slight shift in the timing of switching between opening and closing in the circuit, the analog signal he, ho from each of the conversion units 11e, 11o has almost no effect. Compared with the above, the sample period T can be greatly improved, and the sample period T can be shortened. Further, according to the first embodiment, the shortening (speeding up) is realized not only in terms of noise due to variations between switch circuits, but also in terms of executing parallel processing. .

In practice, digital-to-analog conversion can be performed on an input digital signal of several hundred MHz.

Even if the effect of reducing noise due to such variations in the switch circuit is obtained, the highest-order bit corresponding voltage Em
If an adverse effect is caused by changing e and Emo from a fixed voltage to a sine wave square voltage, the effect is meaningless. Therefore, the most significant bit corresponding voltages Eme and Emo are set to the sine wave 2
Consider the effect of changing to a square-shaped voltage. FIG. 11 is an explanatory diagram used for such consideration.

The conversion of the data unit by the conventional circuit shown in FIG.
As shown in FIG. 11 (A), it can be considered that the digital signal gr is multiplied by a rectangular wave signal, so that the frequency characteristic is as shown by the solid line in FIG. 11 (C). On the other hand, the conversion in the data unit according to the first embodiment can be considered to be obtained by multiplying the digital signal gr by the cosine square signal cos ² (πt / 2T) as shown in FIG. 11 (B). Therefore, the frequency characteristic is as shown by the broken line in FIG. 11 (C).

From a comparison of these frequency characteristics, it can be seen that the frequency characteristics of the conversion according to the first embodiment and the conversion according to the conventional method are almost the same. That is, theoretically, it can be said that almost the same analog signal can be obtained.

The frequency fc in FIG. 11 (C) is 1 / 2T.

Second Embodiment Next, a second embodiment of the present invention will be described with reference to the drawings.

The second embodiment differs from the first embodiment only in the configuration of forming the set signal and the configuration of forming the most significant bit corresponding voltage, and is otherwise the same.

That is, as shown in FIG. 1, two digital / analog conversion units 11e and 11o are provided, and the data values of the input digital signal are alternately distributed to these conversion units 11e and 11o. At 11o, digital / analog conversion is performed based on the most significant bit corresponding voltages Eme and Emo which fluctuate as shown in FIG.
Adders analog signals he and ho output from 11e and 11o
The point that the output analog signal h is formed by adding and combining at 12 is the same as in the first embodiment.

Therefore, in the second embodiment, a description will be given of the configuration of forming the voltage corresponding to the most significant bit and the configuration of forming the set signal, which are different from those of the first embodiment, together with the operation.

FIG. 12 is a block diagram showing this component, and FIG.
The figure is a signal waveform diagram of each part.

The configuration shown in FIG. 12 according to the second embodiment is the same as that of the first embodiment.
This is performed based on equations (8) and (9), which are obtained by modifying equations (2) and (3) described in the embodiment, and are equivalent to these equations.

 As is well known, for the trigonometric function, the following equation is used. β)｝ / 2 There is a sum and product formula shown in (7).

By applying the formula (6) to the formula (2) according to the first embodiment and transforming the formula, the following formula Eme = Em {1-cos (t / T)} / 2 (8) can be obtained. By applying equation (7) to equation 3) and transforming it, the following equation can be obtained: Emo = Em ｛1 + cos (t / T)｝ / 2 (9)

In FIG. 12, a sine wave signal Sa whose cycle is twice the sample period T, 2T, is output from an oscillator (for example, a crystal oscillator) 30.
2 (FIG. 13 (A)) is regularly oscillated and output. This sine wave signal Sa2 is, when a crystal oscillator is applied,
It becomes an extremely low positive voltage oscillation signal. Period 2 of this signal Sa2
T is the same as the period of cos (πt / T) in equations (8) and (9). This signal Sa2 is supplied to a multiplier 31 whose reference terminal is supplied with a fixed voltage Em and whose multiplication coefficient terminal is supplied with a fixed voltage from a volume 32. The voltage is adjusted to 0, and the adjusted sine wave signal Sb2 (the thirteenth
((B)) is output. Note that this sine wave signal Sb2
Is the same as the sine wave square signal Sc according to the first embodiment. The sine wave signal Sb2 is supplied to the subtractor 33 as a subtracted input and to the subtractor as a subtracted input. Note that the subsequent processing configurations 33 to 37 and their operations are the same as in the first embodiment, and a description thereof will be omitted.

The set signal SETe shown in FIG. 12 (FIG. 13D), SE
To (FIG. 13 (E)) and the most significant bit corresponding voltage Eme (1st
The configuration of FIG. 3 (B) and Emo (FIG. 13 (C)) are also of the same complexity as the first embodiment, and are otherwise the same as the first embodiment. Accordingly, the same effect as in the first embodiment can be obtained.

Third Embodiment Next, a third embodiment of the present invention will be described with reference to the drawings.

In the third embodiment, basically, similarly to the first embodiment, two digital / analog conversion units 11e are used.
And 11o, and alternately distribute the data values of the input digital signal to these conversion units 11e and 11o, and provide digital / analog conversion based on the most significant bit corresponding voltages Eme and Emo which fluctuate in these conversion units 11e and 11o. And the analog signal h output from each of the conversion units 11e and 11o.
e and ho are added and synthesized by the adder 12, and the output analog signal h
To form

However, the third embodiment differs from the first embodiment in the most significant bit corresponding voltage waveforms Eme and Emo. for that reason,
The formation configuration of the most significant bit corresponding voltages Eme and Emo and the formation configuration of the set signals SETe and SETo are also different.

FIG. 14 is a signal waveform diagram of the most significant bit corresponding voltage in the third embodiment, FIG. 15 is a block diagram showing the configuration thereof, FIG. 16 is a signal waveform diagram of each part in FIG. 15, and FIG. FIG. 4 is a waveform diagram of a converted analog signal.

As shown in FIG. 14 (A), the most significant bit corresponding voltage Eme to the first digital / analog conversion unit 11e.
Is a time t = 0, 2T,..., Which is delayed from the time when the set signal SETe becomes significant by a predetermined time (about T / 2 in this embodiment) longer than the maximum time required for the switch circuit group in the unit to perform the switching operation. And its rising period fluctuates in a rectangular wave shape equal to the sample period T. The voltage Emo corresponding to the most significant bit to the second digital / analog conversion unit 11o is the other as shown in FIG. 14 (B). Of the voltage Eme.

The formation of these highest-bit-corresponding voltages Eme and Emo and the formation of the set signals SETe and SETo will be described together with their operations with reference to FIGS. 15 and 16.

In FIG. 15, the oscillator 40 oscillates regularly to form and output a sine wave signal Sa3 (FIG. 16 (A)) having a period of the sample period T. This sine wave signal Sa3 is
The pulse is applied to the inverter circuit 41 and shaped. That is, it is converted into a pulse signal Sb3 (FIG. 16 (B)) which takes a TTL level output of logic "0" and "1". Note that the duty ratio of the pulse signal Sb3 is not always 50%.

This pulse signal Sb3 is provided as a clock signal to a binary counter circuit 42 as a frequency divider. Accordingly, from the binary counter circuit 42, the cycle is the cycle T of the pulse signal Sb3.
And a signal having a duty ratio of 50% is output.

The pulse signal Sc3 (FIG. 16 (C)) output from the positive output terminal of the binary counter circuit 42 is supplied to the amplifying transistor 43, and the logic “1” level is set to the voltage Em, and the first digital signal is output. This is output as a voltage waveform Eme (FIG. 16 (E)) for the analog conversion unit 11e. The pulse signal Sd3 (FIG. 16 (D)) output from the negative output terminal of the binary counter circuit 42 is supplied to the amplifying transistor 44, where the logic “1” level is set to the voltage Em and the second digital signal Voltage waveform Emo for analog conversion unit 11o (No.
16 (F)).

The pulse signal Sc3 from the binary counter circuit 42 is given to the AND circuit 45, and the pulse signal Sb from the inverter circuit 41
3 is ANDed, and its AND output Se3 (FIG. 16 (G)) is output to the second digital / analog conversion unit 11o.
Is output as a set signal SETo. The other pulse signal Sd3 from the binary counter circuit 42 is supplied to an AND circuit 46, which takes an AND with the pulse signal Sb3 from the inverter circuit 41, and outputs an AND output Sf3 (FIG. 16 (H)) of the first signal. It is output as a set signal SETe for the digital / analog conversion unit 11e.

The most significant bit corresponding voltage Em thus formed
e, Emo and the set signals SETe, SETo, the first
As shown in FIG. 17 (A), the digital / analog conversion unit 11e outputs an analog signal he having a value converted from time 2rT to time (2r + 1) T (r is a natural number), From the other digital / analog conversion unit 11o, the time (2r +
1) An analog signal ho having a value converted from T to time (2r + 2) T is output. Thus, the final analog signal h is as shown in FIG. 17 (C).

As is apparent from this figure, the output waveform is the same as the waveform in the conventional device. Therefore, in the case of the third embodiment, there is no need to consider the frequency characteristics due to applying the waveforms shown in FIG. 14 as the most significant bit corresponding voltage waveforms Eme and Emo.

Also in the third embodiment, at the timing of switching the state of the switch circuit group in the digital / analog conversion units 11e and 11o, the most significant bit corresponding voltages Eme and Emo are 0.
Therefore, even if there is a slight timing shift in the opening and closing switching in each switch circuit, the effect hardly appears on the analog signals he and ho from the conversion units 11e and 11o,
The conversion accuracy of the final output analog signal h can be greatly improved as compared with the related art, and the sampling period can be shortened. Further, not only the reduction in terms of noise due to the variation between the switch circuits, but also the reduction in terms of executing parallel processing is realized.

Other Embodiments The waveform shapes of the most significant bit corresponding voltages Eme and Emo are not limited to those of the above-described first to third embodiments. For example, a triangular waveform, a symmetric trapezoidal waveform, or the like can be applied. However, at the timing when the set signals SETe and SETo become significant, the most significant bit corresponding voltages Eme and Emo need to be at the minimum value (or a value close thereto).

In the above description, two digital / analog conversion units are provided and each data value of the input digital signal is alternately distributed and processed. However, the number of digital / analog conversion units is n (n is a natural number of 3 or more). ) May be provided so that each data value of the input digital signal is distributed and processed in n cycles. This makes it possible to respond to a higher-speed digital signal.

Further, in the above description, the voltage synthesis type digital / analog conversion circuit has been described. However, the present invention can be applied to a current synthesis type digital / analog conversion circuit having a switch circuit corresponding to each bit of a digital signal.
In this case, the current corresponding to each bit is generated by using the same power supply voltage, but the power supply voltage may be changed.

[Effects of the Invention] As described above, according to the present invention, a plurality of digital / analog conversion units are provided, and at the timing of switching the state of the switch circuit group in each unit, the power supply voltage takes a substantially minimum value. Therefore, even if there is a slight difference in timing between the open / close switching in each switch circuit, the analog signal from each conversion unit has almost no effect, and the conversion accuracy of the final output analog signal is lower than in the past. And the sampling period can be shortened.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a main part of a first embodiment of the present invention, FIG. 2 is a block diagram showing a conventional circuit, and FIG.
FIG. 4 is an explanatory diagram showing a simplified expression of a circuit, FIG. 4 is a signal waveform diagram of each part of a conventional circuit, FIG. 5 is a block diagram showing a simplified expression of a circuit in FIG. 2 for a data string, and FIG. FIG. 7 is a signal wave diagram showing a voltage corresponding to the most significant bit of FIG.
FIG. 8 is a signal waveform diagram showing a converted analog signal for one data value in the embodiment, FIG. 8 is a signal waveform diagram showing a converted analog signal for a data sequence in the first embodiment, and FIG. 9 is a first embodiment. FIG. 10 is a block diagram showing the formation of the most significant bit corresponding voltage and set signal of the example, FIG. 10 is a signal waveform diagram of each part in FIG. 9, FIG. 11 is an explanatory diagram used to consider the effects of the first embodiment, FIG. FIG. 9 is a block diagram showing a configuration for forming a most significant bit corresponding voltage and a set signal according to the second embodiment;
13 is a signal waveform diagram of each part in FIG. 12, FIG. 14 is a signal waveform diagram of the most significant bit corresponding voltage in the third embodiment, and FIG. 15 is a most significant bit corresponding voltage and set signal of the third embodiment. FIG. 16 is a block diagram showing a formation structure, FIG. 16 is a signal waveform diagram of each part in FIG. 15, and FIG. 17 is a waveform diagram showing a converted analog signal for a data string in the third embodiment. 11e, 11o ... Digital / analog conversion unit, 12 ...
Adder, 20 ... Oscillator, 21 ... Capacitor, 22 ... Multiplier, 24, 25 ... Subtractor, 26, 27 ... Comparator, Eme, Emo ...
… Power supply voltage (voltage for the most significant bit), SETe, SETo ……
Set signal.

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H03M 1/08 H03M 1/66

Claims (1)

(57) [Claims] 1. A digital / analog conversion unit which includes a switch circuit corresponding to each bit of an input digital signal and converts an input digital signal into an analog signal, and converts the data of the input digital signal into n Data distributing means for distributing the digital / analog conversion units in a predetermined order, adding means for synthesizing and outputting analog signals output from each of the digital / analog conversion units, and power supply means for forming a power supply voltage which is n power supply voltages and fluctuates at a cycle of n times the sample period of the input digital signal; and instructs each digital / analog conversion unit to take in the input digital signal. And the instruction timing is substantially the minimum value of the corresponding power supply voltage. A digital / analog conversion circuit, comprising: set signal forming means for forming a set of n set signals.