JP2988130B2 - Pulse phase difference detection circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pulse phase difference detection circuit, and more particularly to a detection circuit for connecting a plurality of signal delay circuits having a predetermined delay time to accurately detect a pulse phase difference with high resolution over a wide range. .

[0002]

2. Description of the Related Art Detecting the phase difference between two pulses is useful for various measurement circuits for accurately knowing a physical quantity such as pressure or accurately knowing a distance from a reflected light of a laser to an object. .

As such a pulse phase difference detecting circuit, for example, in Japanese Patent Application Laid-Open No. Sho 60-253994, a large number of delay gates as signal delay circuits having a fixed delay time are connected in series to detect the phase difference between two input pulses. A signal output from a delay gate at a different position is encoded to obtain a phase difference signal.

If the phase difference detection circuit attempts to detect a wide range of phase differences without deteriorating the accuracy, the detection resolution is determined by the delay time of each delay gate, so that it is necessary to provide a large number of delay gates. Therefore, it is difficult to form a compact on a semiconductor chip.

To solve this problem, Japanese Patent Laid-Open Publication No. Hei.
The 220,814 discloses, a ring shape a plurality of delay gates connected to a final stage delay gate and top-stage delay gate as well as connected in series, allowed orbits the preceding pulse inputted, the preceding pulse when a subsequent pulse is inputted There is shown one that detects the phase difference between both pulses from the orbital position and the number of revolutions, and according to such a configuration, it is possible to accurately detect the phase difference over a wide range without significantly increasing the number of gates. .

[0006]

The above detection circuit in which delay gates are connected in a ring shape exhibits excellent characteristics as described above . If the delay gates are connected in a ring, if the delay gates can be arranged in a circle,
Can be made equal in delay time. But,
The area efficiency is poor and the size of the semiconductor chip is increased .

On the other hand, in order to avoid an increase in size, a detection circuit is required.
Multiple delay gates in a straight line and
It consists of one or more delay blocks
The connection line from the delay gate at the last stage of the
Connected to the delay gate of the
It is possible to show. In such a case, the wiring length of the connection line connecting the last-stage delay gate and the first-stage delay gate of a single delay block, or from the last-stage delay gate of a plurality of delay blocks to the first-stage delay gate of the next-stage delay block The wiring length of the connecting line between the two becomes longer than the wiring length of the connecting line between each delay gate in the delay block, and the delay time of this part changes. May lose linearity.

An object of the present invention is to provide a pulse phase difference detection circuit which prevents variation in the delay time of a signal delay circuit and ensures a good linearity between the signal delay circuit and the pulse phase difference. With the goal.

[0009]

To explain the structure of the present invention, a signal delay circuit having a predetermined delay time is sequentially placed in the next stage.
The final addition to connect via a connecting line to the signal delay circuit
The signal delay circuit of the first stage is the next stage with the signal delay circuit of the first stage
Unbroken by these signal delay circuits connected thereto
And a ring-shaped delay pulse generating circuit, the delay pulse
And it allowed orbiting preceding pulse input to the generator in the delayed pulse generating circuit, at the time the subsequent pulse is inputted, leading pulse pulse phase difference detecting circuit for detecting a phase difference between the orbital position and both pulses from laps of Wherein the delay pulse is
The generator circuit is connected to a plurality of signals connected in series and arranged linearly.
Signal delay circuit comprising at least one delay block.
Signal delay at the final stage of the delay block.
Fold the connection line from the circuit and connect it to the signal delay circuit of the next stage.
Continued to, and in which the current driving capability of the signal delay circuit of at least the final stage of each delay block, and set larger than the current drive capability of the remaining signal delay circuit.

[0010]

In the above arrangement, the length of the connection line between the signal delay circuit at the last stage of the delay block and the signal delay circuit at the next stage is smaller than the length of the connection line between the signal delay circuits in the delay block. If the length is too long, the relatively large wiring capacitance and resistance of the connection line will increase the delay time of the preceding pulse that is circulated only in this portion, and the linearity between the actual pulse phase difference and the detection signal will be lost. . Here, in the present invention, since the current drive capability of the final-stage signal delay circuit that outputs to the connection line is increased, it is possible to prevent an increase in delay time for a connection line having a large wiring capacitance or the like. , The linearity between the pulse phase difference and the detection signal is ensured.

[0011]

Embodiment 1 The configuration of a pulse phase difference detection circuit is shown in FIG. In the figure, the detection circuit comprises two delay blocks 1A,
1B, the delay blocks 1A and 1B are arranged in parallel with a pulse selector 15 interposed therebetween, and each of the delay blocks 11A, 12A and 12B, which are a large number of signal delay circuits, are linearly formed in opposite directions.
Are connected in series.

In this embodiment, these delay gates 11, 1
2a and 12b denote the PMOS 111 and the NM as shown in FIG.
The OS 112 is connected in series, and is constituted by a CMOS inverter having a common gate as an input terminal and a common drain as an output terminal. The delay time is substantially constant several nanoseconds, 31 in the delay block 1A, and 31 in the delay block 1B. There are 32 each.

The output terminals of the delay gates 11, 12a and 12b are also connected to a pulse selector 15, and the last stage delay gate 12a of the delay block 1A is connected to the first stage delay gate 11 of the delay block 1B by a connection line 13. , delay gates 12b of the final stage of the delay blocks. 1B, the connection lines 14 are respectively connected to the first delay gate 11 of the delay block 1A through the oR gate 18 and NAND gate 19, a delay pulse generating circuit 1 of the ring Make up.

When the preceding pulse PA is input to the OR gate 18, the pulse PA is applied to each of the delay gates 11, 12a,
The light is sequentially propagated with a delay time of 12b and circulates in the delay pulse generating circuit 1. At this time, each delay gate 11,
Each time the light passes through 12a and 12b, a part thereof is input to the pulse selector 15 as a delay pulse. The pulse selector 15 includes delay gates 11, 12a, 12b
And a predetermined number of EXOR gates for inputting the delayed pulse from the memory. When the subsequent pulse PB is input, the state of each delayed pulse is stored in the built-in flip-flop, and the delay of the preceding pulse PA is reached. Gates 11, 12a,
A select signal is output from the EXOR gate corresponding to 12b.

The encoder 16 issues a binary code output corresponding to the order of the EXOR gate that has issued the select signal. On the other hand, the number of times the preceding pulse PA circulates through the delay pulse generating circuit 1 is integrated by the counter 17 and output as a binary code. Thus, the phase difference (time difference) from the input of the preceding pulse PA to the input of the subsequent pulse PB is known from the outputs of the encoder 16 and the counter 17. The reset of the delay pulse generating circuit 1 is performed by a reset pulse PC of "0" level.

FIG. 3 shows a mask diagram when the delay pulse generating circuit 1 is formed on a semiconductor chip. The figure shows the final stage of the delay block 1A and the initial stage of the delay block 1B. Each of the delay gates 11 and 12a has a common polysilicon film 113 as a gate and a PMOS 111 having a source and a drain formed of a P ⁺ diffusion layer 114. And the N ⁺ diffusion layer 1
NMOS 112 having source and drain composed of
And a CMOS inverter comprising:

The PMOS 11 of each delay gate 11, 12a
1 and the drain of the NMOS 112 are connected to the gate 113 of the delay gate 11 at the next stage by a metal wiring 116 of Al or the like. Among these, metal wires 116 extending from the delay gate 12a of the final stage of the delay block 1A is the slow
The extended gate 12a is folded back in a U-shape to form a relatively long connection line 13 to form the first stage delay gate 11 of the delay block 1B.
, And the wiring capacitance and resistance are increased at this portion. In the figure, reference numeral 118 denotes a metal wiring for a power supply, and 119 denotes a metal wiring for a ground. P ⁺ diffusion layer 1
14, diffusion layers other than the N ⁺ diffusion layer 115 (for example, P well and N well) are omitted.

Here, the PMOS 11 of the delay gate 12a
Paying attention to the gate 113 of No. 1, the gate length is L, the gate width is W2, and the gate length is equal to the other delay gates 11, but the gate width W2 is equal to the gate width W1 of the other delay gates 11. It is almost doubled. This is NM
The same applies to the gate 113 of the OS 112. As a result, the current drive capability of the delay gate 12a is twice that of the other delay gates 11. Of course, it is not limited to twice as long as the required current driving capability can be obtained.

With this structure, even if the connection line 13 having a large wiring capacitance is connected to the output terminal, the delay gate 12
The pulse transmission delay from “a” to the first-stage delay gate 11 of the delay block 1B is as small as between the other delay gates 11. Note that the last stage delay gate 12b (see FIG. 1) of the delay block 1B has the same structure as the delay gate 12a.

This effect is shown in FIG.
, The linearity between the pulse phase difference and the detected digital output is well maintained. On the other hand, in the conventional detection device shown in FIG. 5, since the delay time becomes longer due to the wiring capacitance of the connection line at the delay gate at the last stage of each delay block, the portions indicated by arrows A and B in FIG. The linearity between the pulse phase difference and the detected digital output has been lost.

[0021]

Embodiment 2 In the above embodiment, each delay block 1A, 1
B. CMOS of final stage delay gates 12a and 12b in B
Is made larger than the gate widths of the other delay gates 11, but this is because
As a result, the load capacity increases. Therefore,
As shown in FIG. 6, the gate width W4 of the PMOS 111 constituting the last stage delay gate 11 immediately before the last stage is smaller than the gate width W5 of the last stage delay gate 12a, but the gate width W3 of the other delay gates 11 remaining. To increase the current drive capability. The same applies to the gate width of the NMOS 112. As a result, an increase in the delay time due to an increase in the gate capacitance at the final stage is suppressed, and the linearity of the detection output can be further improved.

In each of the above embodiments, the same effect can be obtained by shortening the gate length instead of increasing the gate width.

The gate width may be gradually increased or the gate length may be reduced not only at the last stage of each delay block and immediately preceding stage but also several stages before.

The number of delay blocks is not limited to two as in the above embodiments, but one or three or more delay blocks can be provided as necessary.

[0025]

As described above, according to the present invention, a pulse phase difference detection circuit having a wide measurement range and excellent detection output linearity can be compactly formed on a semiconductor chip.

[Brief description of the drawings]

FIG. 1 is a block circuit diagram of a pulse phase difference detection circuit.

FIG. 2 is a circuit diagram of a delay gate.

FIG. 3 is a partial mask diagram of a delay pulse generation circuit.

FIG. 4 is an output characteristic diagram of the circuit of the present invention.

FIG. 5 is an output characteristic diagram of a conventional circuit.

FIG. 6 is a partial mask diagram showing another example of the delay pulse generation circuit.

[Explanation of symbols]

 Reference Signs List 1 delay pulse generating circuit 1A, 1B delay block 11, 12a, 12b delay gate (signal delay circuit) 13, 14 connection line

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) G01R 25/00 H03K 5/26 G04F 10/06

Claims (1)

(57) [Claims] A signal delay circuit having a predetermined delay time is provided.
Sequentially, the signal delay circuit of the first stage of the signal delay circuit of the last stage as well as connected via a connecting line to the next stage of the signal delay circuit
Connected to this as the next stage and cut by these signal delay circuits
Forming a ring-shaped delay pulse generating circuit with
The leading pulse input to the delay pulse generation circuit is the delay pulse
And allowed to orbit within the generator, a pulse phase difference detecting circuit for detecting a phase difference between at the time the subsequent pulse is inputted, orbital position of the preceding pulse and than the number of turns both pulses, the
The delay pulse generation circuit is connected in series and arranged linearly.
At least one delay block comprising a plurality of signal delay circuits.
The final stage of the delay block
The connection line from the signal delay circuit of
A pulse phase difference detection circuit connected to the extension circuit, wherein the current drive capability of at least the last signal delay circuit of each of the delay blocks is set to be larger than the current drive capability of the remaining signal delay circuits. .