JP2987592B2 - Electronic clock - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a stepping motor drive control method for a CPU-type electronic timepiece equipped with a ROM and a RAM.

SUMMARY OF THE INVENTION The present invention relates to a CPU type electronic timepiece equipped with a step motor drive unit, a ROM and a RAM, a normal drive pulse generation unit as a step motor drive unit, and a detection unit for detecting a rotation state of the step motor. Means for generating a correction drive pulse having a larger effective power than the normal drive pulse in accordance with the output of the detection means, and a start means for starting these step motor drive means by an interrupt signal An operation signal generating means for generating an operation signal while the step motor driving means is operating; and a driving signal output from the step motor driving means during the generation of the operation signal. Provision of a prohibition unit for prohibiting an operation that stops the occurrence of a fuel cell reduces power consumption of the step motor, It is possible to realize a variety of hand-moving modes, which is a feature of the CPU system, and also to reduce software processing.

[Prior Art] With respect to a drive system for the purpose of reducing the power consumption of a step motor, for example, as described in Japanese Patent Publication No. 15385/1986, the rotational state of the step motor is detected to generate a correction drive pulse. An optimal driving method for outputting has been proposed and put to practical use.

On the other hand, an electronic timepiece of the CPU system equipped with ROM and RAM
Since a variety of applications can be developed by changing the program described in the above document, the system is frequently used, especially in the multifunctional field of digital electronic watches.

In the field of analog electronic timepieces, multifunctionality has been advanced, and various hand movement expressions are performed by driving a stepping motor to rotate forward or reverse by a driving pulse having a fixed effective power.

[Problems to be Solved by the Invention] In the conventional stepping motor drive of a CPU type analog electronic timepiece equipped with ROM and RAM, a drive pulse having a fixed effective power is used, so that the seconds of the basic timepiece are displayed. In this case, there is a problem that the driving power of the step motor becomes large. Further, the optimum driving as proposed in Japanese Patent Publication No. 61-15385 is advantageous for reducing the power consumption of a step motor, but is not suitable for performing various hand movement expressions.

[Object of the Invention] It is an object of the present invention to provide a CPU type analog electronic timepiece in which the power consumption of a stepping motor is reduced and which is capable of displaying various hand movements.

[Means for Solving the Problems] In order to solve the above problems, according to the present invention, the step motor driving means is controlled by a CPU, and the step motor driving means detects a normal drive pulse generating means and a rotation state of the step motor. And a correction drive pulse generating means for generating a correction drive pulse having a larger effective power than the normal drive pulse in accordance with the output of the detection means,
An interrupt signal generating means for activating the step motor driving means, an operation signal generating means for outputting an operation signal while the step motor is operating, and a step signal for generating an operation signal while the step motor is operating; Prohibition means is provided for prohibiting an operation that stops the generation of the drive signal during the generation of the drive signal output from the motor drive means.

[Operation] With the above configuration, it is possible to realize the optimal drive of the stepping motor of the CPU system, and to reduce the power consumption of the step motor. Further, the power consumption of the CPU main body can be reduced by operating the step motor driving means by the interrupt signal generating means.

Also, by providing a prohibition means for prohibiting an operation that stops the generation of the drive signal during the generation of the drive signal output from the operation signal generation means and the step motor drive means, software processing can be reduced. It is also intended. For example, when the stepping motor is temporarily stopped by an input signal of the external input means and the hands are moved at a cycle earlier than usual, it is easy to determine whether or not to perform the fast-forward processing immediately by the operation signal generating means. Since the wait state is set by the prohibition means during the generation of the operation signal, the next step motor drive can be guaranteed.
In other words, the operation signal generating means and the inhibiting means are very useful means when processing must be performed at an arbitrary timing as in the case of external input.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a system block diagram of an electronic timepiece according to the present invention. In FIG. 1, an output of an oscillation circuit 1 is input to a system clock generation circuit 2 for generating a system clock, and a CPU 3 for performing various arithmetic processes is operated by the system clock. In order to display seconds with a stepping motor, a 1HZ signal required for clocking is input from the frequency dividing circuit 4 to the interrupt signal generating circuit 6, and the interrupt signal generating circuit 6
Outputs an interrupt signal to CPU3. The CPU 3 starts the interrupt operation in response to the interrupt signal. In the interrupt operation, first
The address of the ROM 5 is determined, and the programming data is sent to the CPU 3 via the data bus 11. The CPU 3 decodes the programming data and performs various arithmetic processing. In the time counting process such as the second display, the second counter assigned to the RAM 8 is incremented every time the 1 HZ is interrupted, and stored in the RAM 8 again, and the step motor driving means 9 is operated to display the second.

Next, the step motor driving means 9 which is a feature of the present invention is described.
Will be described.

FIG. 2 is a detailed block diagram of the step motor driving means 9 shown in FIG. In FIG. 2, after a normal drive pulse is output to the step motor 28 by the normal drive pulse generation means 23, a detection means for detecting the rotation state of the step motor 28, and if the detection result of 26 is non-rotation, the step motor 28 The selection circuit 25 selects whether to output the correction drive pulse of the correction drive pulse generation means 24 for outputting the correction drive pulse to the step motor drive circuit 27.

FIG. 5 shows the output signal P1OU of the normal drive pulse generation means 23.
FIG. 3 shows a timing chart of T, an output signal P2OUT of the correction drive pulse generation unit 24, and a detection signal SP of the detection unit 26. After the normal drive pulse P1OUT is output, the detection signal SP
This signal detects rotation / non-rotation of the rotor several times. Regarding the method of detecting the rotation / non-rotation of the rotor,
A method is known in which a closed loop including a coil is formed after a normal drive pulse is output, the impedance value of the impedance component in the closed loop is rapidly changed, and rotation / non-rotation is detected based on a voltage value that elongates in the closed loop. . The correction drive pulse P2OUT is a drive pulse having a larger effective power than the normal drive pulse, and must be a drive pulse that can surely rotate the rotor even in a heavy load state.
Further, the normal drive pulse P1OUT is a pulse set to an effective power that can rotate the rotor in a relatively light load state. However, if the effective power is suppressed too much, the probability that the correction drive pulse P2OUT will be output increases, which results in an increase in current consumption. Must be set. The above normal drive pulse generating means 23,
The circuit configurations of the detection unit 26, the correction pulse generation unit 24, the selection circuit 25, and the step motor drive circuit 27 can be easily configured by a conventional technique.

In FIG. 2, a starting means 20 for starting the normal drive pulse generating means 23, the detecting means 26, and the correction pulse generating means 24.
Is the WRITE signal of the program and the prohibiting means 3 described later.
Is controlled by The activation unit 20 activates the normal drive pulse generation unit 23, the detection unit 26, and the correction pulse generation unit 24, and while these are operating, the operation signal generation unit 21 generates an operation signal. In addition, while the operation signal generating unit 21 is generating the operation signal, the prohibiting unit 33 prohibits the control of the WRITE signal of the program, and during the generation of the driving signal output from the step motor driving unit,
An operation that stops the generation of this signal is prohibited.

Next, the operation of the activation means 20 and the operation signal generation means 21 according to the present invention will be described with reference to FIG. The operations of the normal drive pulse generation means 23, the detection means 26, and the correction drive pulse generation means 24 are performed by the WRITE signal of the program.
This is done by writing "1" to. When "1" is written to the latch circuit 30, the clock signal CL passes through the gate circuit 31 and is input to the sequential circuit stage 35, and the output signal of each stage is output to the normal drive pulse generation unit 23, the detection unit 26, the correction drive The operation is started by being input to the pulse generation means 24, respectively. Also,
The latch circuit 30 has been automatically reset by the BRST signal. After the correction drive pulse P2OUT is output as shown in the timing chart of FIG.
This is a signal generated by the gate circuit 34. By the BRST signal, the supply of the clock signal CL can be stopped without writing “0” to the latch circuit 30 in the program. In addition, the latch circuit 30 generates operation signals of the normal drive pulse generator 23, the detector 26, and the correction drive pulse generator 24 together with the gate circuit 32. The gate circuit 32 opens the gate by the READ signal of the program, and the latch circuit 30
The function of placing the output signal BUSY on the data bus 11 is achieved. The above is the operation of the activation unit 20 and the operation signal generation unit 21.

Next, the operation of the inhibiting means 22 will be described with reference to FIG. The prohibiting means 22 can be easily incorporated in the ROM 5 similarly to a normal timekeeping processing program. Here, consider the processing content when transitioning from the normal clock display mode to the clock correction mode. FIG. 4 shows the processing contents of the operation of returning the second hand to a specific position at a rapid traverse at the same time as setting the correction mode when correcting the timepiece. FIG. 4A shows a processing procedure when an interrupt signal is generated by the external input means 7. When the correction condition is established by the external input means 7, a read operation is performed to determine the level of the BUSY signal which is an operation signal. If the BUSY signal is "1" due to this read operation, a loop process is performed until the BUSY signal becomes "0" because an operation signal has been generated. This loop processing is the function of the prohibition unit 22. Step motor driving means
It is possible to prohibit stopping 27 and to quickly transition to the next operation. After this loop processing, a correction processing is performed, a timing interrupt for fast-forwarding is enabled, and the program is stopped by HALT. 4th
FIG. 7B shows the subsequent timing processing. In this timing process, the stepping motor 28 is fast-forwarded by operating the activation means 20 at a cycle earlier than usual. Even in such a timing process, the prohibiting means 22 has an effective function. That is, by determining the level of the BUSY signal before writing “1” to the latch circuit 30, it is prohibited to write “1” again during the generation of the operation signal. Such a case does not occur when interrupt processing is performed in a normal cycle, but occurs when other interrupt processing takes time and the interrupt processing cycle of timing is disturbed. Even in such a case, the fast-forward operation can be performed quickly. Further, in order to switch the normal operation to the fast-forward operation more quickly, it is conceivable to switch the timing of the BRST signal based on the detection result of the detection means 26. That is, when the rotation is detected by the detection means 26, the BRST signal may be output after the detection signal SP is output.

[Effects of the Invention] As described above, the reduction in power consumption of the driving means of the step motor according to the present invention has the effect of contributing to the reduction in thickness and size of the timepiece. Further, the drive processing time of the step motor by the program is shortened, and the software processing is reduced. This allows ROM
The capacity can be used efficiently, and a more versatile hand movement expression has become possible.

[Brief description of the drawings]

FIG. 1 is a system block diagram of an electronic timepiece according to the present invention, FIG. 2 is a block diagram of a step motor driving means,
FIG. 3 is an embodiment of the starting means and the operation signal generating means, FIG. 4 is a flowchart of the inhibiting means, and FIG. 5 is a timing chart of the step motor driving means. DESCRIPTION OF SYMBOLS 1 ... Oscillation circuit 2 ... System clock generation circuit 3 ... CPU 4 ... Divider circuit 5 ... ROM 6 ... Interrupt signal generation circuit 7 ... External input means 8 ... RAM 9 ... Step motor drive Means 10 Address bus 11 Data bus 20 Starting means 21 Operating signal generating means 22 Prohibiting means 23 Normal driving pulse generating means 24 Correcting driving pulse generating means 25 Selection circuit 26 Detecting means 27 Step motor drive circuit 28 Step motors 30, 33 Latch circuits 31, 32, 34 Gate circuit 35 Sequence circuit stage

──────────────────────────────────────────────────続 き Continued on the front page (58) Fields investigated (Int. Cl. ⁶ , DB name) G04C 3/14 G04G 1/00-15/00 G04C 3/00-5/00 H02P 8/00

Claims (2)

(57) [Claims] An oscillation circuit, a system clock generation circuit for generating a system clock from an output of the oscillation circuit, a frequency division circuit for dividing the output of the oscillation circuit, and a processing procedure such as a clock operation of a clock are programmed. ROM
An arithmetic processing means for decoding data programmed in the ROM and performing various arithmetic processing, a RAM for storing various data, and an interrupt signal generating means for generating an interrupt signal to the arithmetic processing means; In an electronic timepiece having external input means and step motor driving means, starting means for operating the interrupt signal generating means in response to a timing signal from the frequency dividing circuit to start the step motor driving means, and the step motor While the driving means is operating, the operation signal is generated when the operation signal generating means for generating the operation signal and the interrupt signal generating means are operated by the input signal from the external input means to perform the input processing. An electronic timepiece is provided with a prohibiting means for prohibiting the operation of stopping the signal while the time is on. 2. The method according to claim 1, wherein the step motor driving means includes a normal driving pulse generating means, a detecting means for detecting a rotation state of the step motor, and a correction having a larger effective power than the normal driving pulse in accordance with an output of the detecting means. 2. The electronic timepiece according to claim 1, further comprising a correction drive pulse generating means for generating a drive pulse.