JP2985510B2 - Current saving switch circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a case where a contact of an operation switch is turned on unnecessarily for a long period of time, and the operation switch contact is turned on unless the CPU takes in the state signal from the operation switch. The present invention relates to a current-saving switch circuit capable of preventing current consumption based on the current.

[0002]

2. Description of the Related Art FIG. 2 shows a configuration example of a conventional circuit. In the figure, 1 is an operation switch such as a toggle switch, 5 is a pull-up resistor provided in series with the switch 1, + V is a battery power supply, 2 is a 3-state buffer,
3 is a CPU.

In this example, the CPU 3 always has a role of measuring the power pulse of the watt-hour meter, and is operated by the battery power supply + V floatingly charged from the AC power supply to be measured. Then, when the AC power supply fails, when the power failure is detected via a power failure detection circuit (not shown), the mode shifts to a standby mode to suppress the current consumption of the battery.

When it is necessary to read, for example, a calculated value of an electric energy or the like from the watt hour meter in the power outage state, the state in which the CPU 3 stops executing the program (hereinafter referred to as a standby mode) is temporarily released, and the program is executed. It is necessary to shift to an execution state (hereinafter referred to as a continuous operation mode). The switch 1 is one of the operation switches for releasing the CPU 3 from the standby mode. Now, when this switch 1 is turned on, the switch state signal 1
1 changes from the H level to the L level (active), becomes the standby mode release signal 12, is input to the non-mask interrupt terminal NMi of the CPU 3, and the CPU 3 enters the continuous operation mode. Then, the three-state buffer 2 is made conductive by the L-level (active) read signal 14 output in the read cycle, and the switch state signal 11 is read as a signal (referred to as a data bus signal) 13 on the data bus.

Accordingly, the CPU 3 determines the ON operation of the switch 1 and executes a predetermined process ("display of a weighing value" in this example). Then, if the power failure state continues thereafter, the mode shifts to the standby mode again.

[0006]

However, in the circuit of FIG. 2, if the switch 1 is inadvertently kept in the ON state, current always flows from the battery power supply via the resistor 5 and the switch 1, and the current consumption is reduced. There is a problem that the battery life is large and the life of the battery is shortened. Therefore, an object of the present invention is to provide a current-saving switch circuit that can prevent the current consumption of the switch at all times even if the state where the switch does not return after the operation of the switch continues.

[0007]

According to a first aspect of the present invention, there is provided a current-saving switch circuit comprising: a switch contact provided in series with a resistor (eg, 5) between a DC power source (eg, + V); (Such as 1) (switch state signal 1
In a circuit that a CPU (such as 1) reads (eg, via a three-state buffer 2), an output circuit of a logic circuit that receives at least a read signal (such as 14) of the CPU as an input in series with the switch contact The output circuit is turned on when the read signal is valid, and is turned off when the read signal is invalid.

Further, in the current saving switch circuit according to the second aspect,
2. The current saving switch circuit according to claim 1, wherein
The PU can be in a standby mode, and the output circuit of the logic circuit is a CPU indicating the standby mode.
On the basis of the output signal (e.g., control signal 15), and the state signal when the switch contact is on is given to the CPU (e.g., an interrupt terminal NMi) as a signal (e.g., 12) for releasing the standby mode. Things.

Further, in the current-saving switch circuit according to claim 3,
3. The current-saving switch circuit according to claim 2, wherein the logic circuit is a gate circuit (such as an AND gate 4).

[0010]

An output circuit of a logic circuit (such as an AND gate 4) that enables the switch 1 to be normally energized only by the read signal 14 of the CPU 3 is inserted in series with the switch 1, and the switch 1 is always kept ON. However, current is prevented from flowing through the switch 1 except for the read cycle, and the current consumption of the battery power supply by the switch 1 is suppressed.

[0011]

FIG. 1 is a circuit diagram showing a main part of an embodiment of the present invention, corresponding to FIG. 2, and FIG. 3 is a waveform diagram showing the operation thereof. In FIG. 1, an AND gate 4 (open drain output circuit) is provided in series with the ground side terminal of the switch 1 in FIG. 2, and a read signal 14 and a control signal 15 of the CPU 3 are supplied to the AND gate 4 as input signals. The difference was that The control signal 15 is at the L level when the CPU 3 is in the standby mode, and is at the H level when the CPU 3 is in the continuous operation mode.
Level.

Next, the operation of FIG. 1 will be described with reference to FIG. When the CPU 3 is in the standby mode as shown in the waveform (a) of FIG. 3, the switch 1 is turned on (time t1). At this time, the read signal 14 (waveform (d) in FIG. 3) is at the H level and the control signal 15 (waveform (e) in FIG. 3) is at the L level, so that the output of the AND gate 4 has the waveform (f).
As shown in FIG. When the switch 1 is turned on and a current flows through the switch as shown in the waveform (b) of FIG. 3, the CPU 3 enters the linked operation mode at time t2,
The control signal 15 becomes H level. At this time, since the read signal 14 is at the H level and the control signal 15 is also at the H level, the output of the AND gate 4 is also at the H level. Since the output circuit of the AND gate 4 is connected to the switch 1, when the output of the AND gate 4 becomes H level, no current flows even when the switch 1 is in the ON state (waveform (b)). Next, during the period from time t3 to t4, when the read signal goes low (becomes a read cycle), the output of the AND gate 4 goes low, current flows through the switch 1, and the three-state buffer 2 is turned on. The CPU 3 reads the L-level switch state signal 11 as the data bus signal 13 and, as in FIG.
Is determined.

Therefore, even when the CPU 3 is in the interlocking operation mode, the input signals 14 and 15 of the AND gate 4 are both at the H level except during the read cycle.
The output of the gate 4 is at the H level, and even if the switch 1 remains ON, no current flows through the switch 1 and the constant current consumption of the switch 1 can be suppressed. Although the output circuit of the AND gate 4 has been described as an open drain, a C-MOS output can also be used.

[0014]

According to the present invention, the CPU 3 is connected in series with the switch 1 for supplying the standby mode release signal to the CPU 3.
AND between read signal and signal indicating standby mode
The output circuit of the AND gate 4 which is turned on under the condition (in other words, turned off in the non-standby mode (continuous operation mode) and in the non-read cycle) is inserted. In the continuous operation state, the current flows through the switch 1 only during the read cycle. Therefore, the current consumption of the switch 1 at all times when the switch 1 is in the ON state can be reduced.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration of a main part as one embodiment of the present invention.

FIG. 2 is a conventional circuit diagram corresponding to FIG.

FIG. 3 is an operation waveform diagram of FIG. 1;

[Explanation of symbols]

 Reference Signs List 1 switch 2 3-state buffer 3 CPU 4 AND gate 5 pull-up resistor + V battery power 11 switch state signal 12 standby mode release signal 13 data bus signal 14 read signal 15 control signal

Claims (3)

(57) [Claims] 1. A circuit in which a CPU reads a state of a switch contact provided in series with a resistor between a DC power supply, wherein a signal indicating an operation mode of the CPU and a read signal are input in series with the switch contact. A logic circuit connected thereto, wherein, when the CPU is in the continuous operation mode, the output of the logic circuit goes to H level when the read signal is invalid, thereby preventing a current flowing through the switch contact. Switch circuit. 2. The current-saving switch circuit according to claim 1, wherein said CPU can be in a standby mode, and said ON-state signal of said switch contact is given to said CPU as a signal for releasing said standby mode. Current-saving switch circuit characterized by being able to be used. 3. The current saving switch circuit according to claim 2, wherein said logic circuit is a gate circuit.