JPH06149417A - Cpu reset device - Google Patents

Cpu reset device

Info

Publication number
JPH06149417A
JPH06149417A JP4301441A JP30144192A JPH06149417A JP H06149417 A JPH06149417 A JP H06149417A JP 4301441 A JP4301441 A JP 4301441A JP 30144192 A JP30144192 A JP 30144192A JP H06149417 A JPH06149417 A JP H06149417A
Authority
JP
Japan
Prior art keywords
cpu
power supply
signal
voltage
edge
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4301441A
Other languages
Japanese (ja)
Inventor
Masaru Nagashima
優 長島
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Co Ltd filed Critical Fuji Electric Co Ltd
Priority to JP4301441A priority Critical patent/JPH06149417A/en
Publication of JPH06149417A publication Critical patent/JPH06149417A/en
Pending legal-status Critical Current

Links

Classifications

    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02BCLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/30Systems integrating technologies related to power network operation and communication or information technologies for improving the carbon footprint of the management of residential or tertiary loads, i.e. smart grids as climate change mitigation technology in the buildings sector, including also the last stages of power distribution and the control, monitoring or operating management systems at local level
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y04INFORMATION OR COMMUNICATION TECHNOLOGIES HAVING AN IMPACT ON OTHER TECHNOLOGY AREAS
    • Y04SSYSTEMS INTEGRATING TECHNOLOGIES RELATED TO POWER NETWORK OPERATION, COMMUNICATION OR INFORMATION TECHNOLOGIES FOR IMPROVING THE ELECTRICAL POWER GENERATION, TRANSMISSION, DISTRIBUTION, MANAGEMENT OR USAGE, i.e. SMART GRIDS
    • Y04S20/00Management or operation of end-user stationary applications or the last stages of power distribution; Controlling, monitoring or operating thereof
    • Y04S20/20End-user application control systems

Landscapes

  • Measurement Of Current Or Voltage (AREA)
  • Power Sources (AREA)
  • Stand-By Power Supply Arrangements (AREA)

Abstract

PURPOSE:To reduce current consumption just after the reduction of a power supply voltage by immediately stopping the operation of a CPU after data are saved, detecting the power supply voltage when it recovers a specified value before the lapse of prescribed time, generating an interruption signal and returning the CPU to the normal operation. CONSTITUTION:An edge detection circuit 4 for detecting the edge of a voltage detection signal (b) is added and when a voltage drop is caused and recovered, an interruption signal (d) is generated. Namely, each time the falling edge and rising edge of the voltage detection signal (b) are respectively detected, the edge detection circuit 4 outputs the pulse of a prescribed short time width. Thus, a CPU 3 stops the operation and turns to a low current consumption state after processing such as saving data in an internal register corresponding to the falling edge of the interruption signal (d) at the time of voltage drop occurrence and when the voltage drop is recovered in a short time and a CPU reset signal is not generated, the CPU 3 is returned to the operating state with the fall edge of the interruption signal (d) at the time of this power supply voltage recovery.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は電源消失時などに電子式
電力量計などを制御するCPUをリセットする装置、特
に電源瞬断時などにおける電源電圧低下直後のCPUの
消費電流を低減してCPUリセット発生による処理の継
続性喪失を極力防ぐようにしたCPUリセット装置に関
する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a device for resetting a CPU that controls an electronic watt-hour meter or the like when the power supply is lost, and particularly to reduce the current consumption of the CPU immediately after the power supply voltage drops at the time of a power supply interruption. The present invention relates to a CPU reset device which prevents loss of continuity of processing due to occurrence of CPU reset as much as possible.

【0002】なお以下各図において同一の符号は同一も
しくは相当部分を示す。
In the following figures, the same reference numerals indicate the same or corresponding parts.

【0003】[0003]

【従来の技術】従来、交流電圧と交流電流を乗算して電
力に比例したパルス列に変換する回路と、そのパルスを
計数して電力量,最大需要電力などを液晶に表示するな
どの制御を行い、交流電源停電時も電池バックアップさ
れて液晶表示を行うCPUと、その周辺回路とからなる
電子式電力量計が知られている。
2. Description of the Related Art Conventionally, a circuit for multiplying an AC voltage by an AC current and converting it into a pulse train proportional to power, and controlling such as counting the pulses and displaying the amount of power, maximum demand power, etc. on a liquid crystal are performed. There is known an electronic watt-hour meter including a CPU that performs a liquid crystal display with a battery backup even when the AC power supply is interrupted, and a peripheral circuit thereof.

【0004】図3はこの種の電子式電力量計のCPUの
従来のリセット回路の構成例を示し、図4は図3内の各
部の動作波形を示す。図3において、3はCPU、1は
この回路の直流電源の電圧aを監視し、この電圧aが規
定値を下回るとLレベルの電圧検出信号bを出力する電
圧検出回路、2はこの電圧検出信号bを遅延させ、CP
U3へCPUリセット信号cとして与えるCR遅延回路
である。
FIG. 3 shows a configuration example of a conventional reset circuit of a CPU of this kind of electronic watt-hour meter, and FIG. 4 shows operation waveforms of respective parts in FIG. In FIG. 3, 3 is a CPU, 1 is a voltage detection circuit that monitors the voltage a of the DC power supply of this circuit, and outputs an L level voltage detection signal b when this voltage a falls below a specified value. Delay signal b, CP
It is a CR delay circuit which is given to U3 as a CPU reset signal c.

【0005】次に図4を参照しつつ図3の動作を述べ
る。即ち図3においては電源電圧aを監視して、電圧低
下を検出する電圧検出回路1の電圧検出信号bを直接C
PU3へ割込信号として与えると共に、この電圧検出信
号bをCR遅延回路2によって遅延させてCPUリセッ
ト信号cとしてCPU3へ与えている。電圧検出信号b
は電源電圧aが規定値以下の時“L”レベル、規定値以
上の時“H”レベルとなる。割込信号bは立下がりエッ
ジのみ有効である。電圧低下時にこの割込信号bがCP
Uリセット信号cの発生に先立って入力され、CPU3
は内部レジスタのデータ退避などの処理の後、CPUリ
セット信号入力(つまり同信号cが有効レベルになる)
まで割込信号bを監視しながら1カ所でループ処理を実
行する。そして図4のように電圧低下が短時間で回復
し、CPUリセット信号cの発生に到らない場合には、
割込信号bが解除されたとき電圧低下発生前の処理に戻
るようにしている。
Next, the operation of FIG. 3 will be described with reference to FIG. That is, in FIG. 3, the power supply voltage a is monitored and the voltage detection signal b of the voltage detection circuit 1 for detecting a voltage drop is directly C
The voltage detection signal b is given to the PU 3 as an interrupt signal, and the voltage detection signal b is delayed by the CR delay circuit 2 to be given to the CPU 3 as a CPU reset signal c. Voltage detection signal b
Is at "L" level when the power supply voltage a is below the specified value, and is at "H" level when it is above the specified value. The interrupt signal b is valid only at the falling edge. When the voltage drops, this interrupt signal b becomes CP
It is input prior to the generation of the U reset signal c, and the CPU 3
Is a CPU reset signal input (that is, the signal c becomes effective level) after processing such as data saving of the internal register
The loop process is executed at one place while monitoring the interrupt signal b up to. When the voltage drop recovers in a short time as shown in FIG. 4 and the CPU reset signal c is not generated,
When the interrupt signal b is released, the process before the voltage drop occurs is returned to.

【0006】[0006]

【発明が解決しようとする課題】しかしながら図3の回
路の場合、“L”の割込信号bの発生後からCPU3は
図4のアに示すように動作し続けるため、図4のイに示
すようにその消費電流は減少せず、そのため電源電圧a
の低下が加速され、CPUリセット信号発生に到りやす
く、CPUリセット信号が発生すれば処理の継続性は失
われてしまう。もともとこの図3のリセット信号発生回
路は主として電池バックアップ時の電池電圧低下に対処
するために設けた回路であり、本来このようなCPUリ
セット信号の発生は処理を継続させるためには好ましく
ない。そこでこの発明は、この問題を解消し電源電圧低
下直後から消費電流を低減することができるCPUリセ
ット装置を提供することを課題とする。
However, in the case of the circuit of FIG. 3, since the CPU 3 continues to operate as shown in FIG. 4A after the generation of the "L" interrupt signal b, the operation shown in FIG. Its current consumption does not decrease, so the power supply voltage a
Is accelerated and the CPU reset signal is easily generated. If the CPU reset signal is generated, the continuity of the process is lost. Originally, the reset signal generation circuit of FIG. 3 is a circuit provided mainly for coping with the battery voltage drop at the time of battery backup, and originally such generation of the CPU reset signal is not preferable for continuing the processing. Therefore, an object of the present invention is to provide a CPU reset device that solves this problem and can reduce current consumption immediately after the power supply voltage drops.

【0007】[0007]

【課題を解決するための手段】前記の課題を解決するた
めに、請求項1のリセット装置は、バックアップ電源の
電圧(aなど)が規定値を下回ったことを検出して第1
の割込信号(電圧検出信号bなど)を発生し、前記電源
で動作するCPU(3など)にこの割込信号を与えて必
要なデータの退避等を行わせ、前記電源電圧の規定値を
下回った状態が所定時間(CR遅延回路2の時定数な
ど)経過したとき(CPUリセット信号cなどにより)
前記CPUをリセットさせるCPUリセット装置におい
て、前記データ退避後、直ちにこのCPUの動作を停止
させ、前記電源電圧が前記所定時間の経過以前に前記の
規定値を回復したときは、この回復を検出して第2の割
込信号(dなど)を発生し、この割込信号を前記CPU
に与えてこのCPUを正常の動作に復帰させるようにす
る。
In order to solve the above problems, a reset device according to a first aspect of the present invention detects that a voltage (a, etc.) of a backup power supply is below a specified value, and
Generates an interrupt signal (such as a voltage detection signal b) of the CPU, and supplies the interrupt signal to a CPU (3 or the like) operating on the power source to save necessary data, and When the falling state has passed a predetermined time (such as the time constant of the CR delay circuit 2) (due to the CPU reset signal c, etc.)
In the CPU reset device for resetting the CPU, immediately after the data is saved, the operation of the CPU is stopped, and when the power supply voltage recovers the specified value before the elapse of the predetermined time, this recovery is detected. Generates a second interrupt signal (d, etc.) and sends this interrupt signal to the CPU.
To allow the CPU to return to normal operation.

【0008】また請求項2のCPUリセット装置では、
請求項1に記載のCPUリセット装置は、前記電源電圧
が前記規定値を下回る時点および上回る時点で夫々2値
信号を反転させる手段(電圧検出回路1など)と、この
2値信号の反転ごとに前記第1,第2の割込信号となる
パルスを発生する手段(エッジ検出回路4など)とを備
えたものであるようにする。
Further, in the CPU reset device of claim 2,
The CPU reset device according to claim 1, wherein a means (a voltage detection circuit 1 and the like) for inverting a binary signal at a time point when the power supply voltage is below and above the specified value, and for each inversion of the binary signal. And a means for generating a pulse which becomes the first and second interrupt signals (edge detection circuit 4 etc.).

【0009】また請求項3のCPUリセット装置では、
請求項1または請求項2に記載のCPUリセット装置に
おいて、前記CPUは電子式電力量計を制御するもので
あるようにする。
According to the CPU reset device of claim 3,
The CPU reset device according to claim 1 or 2, wherein the CPU controls an electronic watt hour meter.

【0010】[0010]

【作用】電圧検出信号bの電圧低下検出時(立下がり
時)と電圧回復検出時(立上がり時)においてエッジ検
出回路4を介し夫々割込信号を発生し、前者の割込信号
でCPU3にデータ退避等を行わせたのち直ちにCPU
3の動作を停止させて電流消費を減じ、後者の割込信号
でCPU3を正常動作に復帰させる。
When the voltage drop of the voltage detection signal b is detected (at the falling edge) and when the voltage recovery is detected (at the rising edge), an interrupt signal is generated through the edge detection circuit 4, and the former interrupt signal is used to send data to the CPU 3. Immediately after evacuation, etc., CPU
The operation of No. 3 is stopped to reduce the current consumption, and the latter interrupt signal causes the CPU 3 to return to the normal operation.

【0011】[0011]

【実施例】図1は本発明の一実施例としてのCPUリセ
ット回路の構成図で図3に対応する。また図2は図1の
各部の動作波形を示す。図1においては電圧検出信号b
はエッジ検出回路4を介し割込信号dとしてCPU3に
与えられる。ここでエッジ検出回路4は図4に割込信号
dに示すように電圧検出信号bの立下がりエッジ,立上
りエッジの夫々を検出するつど、所定の短い時間巾のL
レベルのパルスを出力する。
DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a block diagram of a CPU reset circuit as an embodiment of the present invention and corresponds to FIG. Further, FIG. 2 shows operation waveforms of each part of FIG. In FIG. 1, the voltage detection signal b
Is given to the CPU 3 as an interrupt signal d via the edge detection circuit 4. Here, the edge detection circuit 4 detects the falling edge and the rising edge of the voltage detection signal b as shown by the interrupt signal d in FIG.
Output level pulse.

【0012】このように本発明では電圧検出信号bのエ
ッジを検出する回路4を付加し、電圧低下発生時,回復
時共に割込信号dに立下がりエッジを作る。これにより
電圧低下発生時の割込信号dの立下がりエッジでCPU
3は内部レジスタのデータ退避などの処理の後、図2の
アに示すように動作を停止し低消費電流状態とする。そ
して電圧低下が短時間で回復しCPUリセット信号発生
に到らない場合に、この電源電圧回復時の割込信号dの
立下がりエッジでCPU3は動作状態に戻る。
As described above, in the present invention, the circuit 4 for detecting the edge of the voltage detection signal b is added to make the falling edge of the interrupt signal d both at the time of occurrence of voltage drop and at the time of recovery. As a result, at the falling edge of the interrupt signal d when a voltage drop occurs, the CPU
After processing such as data saving in the internal register 3, the operation 3 is stopped and brought into a low current consumption state as shown in FIG. When the voltage drop is recovered in a short time and the CPU reset signal is not generated, the CPU 3 returns to the operating state at the falling edge of the interrupt signal d when the power supply voltage is recovered.

【0013】[0013]

【発明の効果】本発明によれば、電圧検出信号bの電圧
低下検出時(立下がり時)と電圧回復検出時(立上がり
時)においてエッジ検出回路4を介し夫々割込信号を発
生し、前者の割込信号でCPU3にデータ退避等を行わ
せたのち直ちにCPU3の動作を停止させて電流消費を
減じ、後者の割込信号でCPU3を正常動作に復帰させ
るようにしたので、電池電圧低下を短時間で終わらせて
処理を継続することができる。
According to the present invention, an interrupt signal is generated via the edge detection circuit 4 at the time of detecting the voltage drop of the voltage detection signal b (at the time of falling) and at the time of the voltage recovery detection (at the time of rising). Since the CPU 3 is caused to save data etc. by the interrupt signal of No. 3, the operation of the CPU 3 is immediately stopped to reduce the current consumption, and the latter interrupt signal is used to restore the CPU 3 to the normal operation. It can be completed in a short time and the processing can be continued.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例としての要部構成を示す回路
FIG. 1 is a circuit diagram showing a main part configuration as one embodiment of the present invention.

【図2】図1の各部の動作波形図FIG. 2 is an operation waveform diagram of each part in FIG.

【図3】図1に対応する従来の回路図FIG. 3 is a conventional circuit diagram corresponding to FIG.

【図4】図3の各部の動作波形図FIG. 4 is an operation waveform diagram of each part of FIG.

【符号の説明】[Explanation of symbols]

1 電圧検出回路 2 CR遅延回路 3 CPU 4 エッジ検出回路 a 電源電圧 b 電圧検出信号 c CPUリセット信号 d 割込信号 1 voltage detection circuit 2 CR delay circuit 3 CPU 4 edge detection circuit a power supply voltage b voltage detection signal c CPU reset signal d interrupt signal

───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.5 識別記号 庁内整理番号 FI 技術表示箇所 H02J 9/00 Q 4235−5G ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 5 Identification code Office reference number FI technical display location H02J 9/00 Q 4235-5G

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】バックアップ電源の電圧が規定値を下回っ
たことを検出して第1の割込信号を発生し、前記電源で
動作するCPUにこの割込信号を与えて必要なデータの
退避等を行わせ、前記電源電圧の規定値を下回った状態
が所定時間経過したとき前記CPUをリセットさせるC
PUリセット装置において、 前記データ退避後、直ちにこのCPUの動作を停止さ
せ、前記電源電圧が前記所定時間の経過以前に前記の規
定値を回復したときは、この回復を検出して第2の割込
信号を発生し、この割込信号を前記CPUに与えてこの
CPUを正常の動作に復帰させることを特徴とするCP
Uリセット装置。
1. A first interrupt signal is generated by detecting that the voltage of a backup power supply falls below a specified value, and the CPU operating on the power supply is provided with this interrupt signal to save necessary data. And resets the CPU when a predetermined time has passed while the power supply voltage is below the specified value C
In the PU reset device, when the CPU operation is immediately stopped after the data is saved and the power supply voltage has recovered to the specified value before the elapse of the predetermined time, this recovery is detected and a second interrupt is detected. CP for generating an interrupt signal and giving the interrupt signal to the CPU to restore the normal operation of the CPU.
U reset device.
【請求項2】請求項1に記載のCPUリセット装置は、
前記電源電圧が前記規定値を下回る時点および上回る時
点で夫々2値信号を反転させる手段と、 この2値信号の反転ごとに前記第1,第2の割込信号と
なるパルスを発生する手段とを備えたものであることを
特徴とするCPUリセット装置。
2. The CPU reset device according to claim 1,
Means for inverting the binary signal at the time when the power supply voltage falls below and above the specified value, and means for generating a pulse that becomes the first and second interrupt signals at each inversion of the binary signal. A CPU reset device comprising:
【請求項3】請求項1または請求項2に記載のCPUリ
セット装置において、 前記CPUは電子式電力量計を制御するものであること
を特徴とするCPUリセット装置。
3. The CPU reset device according to claim 1 or 2, wherein the CPU controls an electronic watt hour meter.
JP4301441A 1992-11-12 1992-11-12 Cpu reset device Pending JPH06149417A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4301441A JPH06149417A (en) 1992-11-12 1992-11-12 Cpu reset device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4301441A JPH06149417A (en) 1992-11-12 1992-11-12 Cpu reset device

Publications (1)

Publication Number Publication Date
JPH06149417A true JPH06149417A (en) 1994-05-27

Family

ID=17896934

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4301441A Pending JPH06149417A (en) 1992-11-12 1992-11-12 Cpu reset device

Country Status (1)

Country Link
JP (1) JPH06149417A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009151789A (en) * 2007-12-19 2009-07-09 Arm Ltd Device for storing hardware driven processor state prior to entering low power mode
JP2010041879A (en) * 2008-08-07 2010-02-18 Hitachi Omron Terminal Solutions Corp Electronic equipment
JP2021528875A (en) * 2018-06-27 2021-10-21 インテル コーポレイション Equipment for autonomous clock and voltage security and functional safety

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009151789A (en) * 2007-12-19 2009-07-09 Arm Ltd Device for storing hardware driven processor state prior to entering low power mode
JP2010041879A (en) * 2008-08-07 2010-02-18 Hitachi Omron Terminal Solutions Corp Electronic equipment
JP2021528875A (en) * 2018-06-27 2021-10-21 インテル コーポレイション Equipment for autonomous clock and voltage security and functional safety

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