CN116742737A

CN116742737A - Monitoring battery voltage delivery

Info

Publication number: CN116742737A
Application number: CN202310210457.4A
Authority: CN
Inventors: A·特拉莫尼; N·拉法格
Original assignee: STMicroelectronics Rousset SAS; STMicroelectronics Alps SAS
Current assignee: STMicroelectronics Rousset SAS; STMicroelectronics Alps SAS
Priority date: 2022-03-08
Filing date: 2023-03-07
Publication date: 2023-09-12

Abstract

The present disclosure relates to monitoring battery voltage delivery. A circuit monitors a first voltage delivered by a battery. The monitored first voltage is compared to the second voltage. When the comparator detects that the first voltage is smaller than the second voltage, the counter starts counting. If the value of the counter exceeds a limit value during the counting, an interrupt signal is generated to control an operating mode of the electronic device powered by the battery.

Description

Monitoring battery voltage delivery

Priority claim

The present application claims the benefit of priority from french patent application number 2202016 filed 3/8 2022, the entire contents of which are incorporated herein by reference to the maximum extent allowed by law.

Technical Field

The present disclosure relates generally to battery-powered electronic systems and devices. More specifically, the present disclosure relates to monitoring of the voltage delivered by a battery.

Background

A large number of currently used electronic systems and devices include an internal battery that is at least partially powered.

Typically, the battery is expected to deliver a DC voltage. However, most batteries exhibit a voltage drop that can prevent the electronic system or device from operating properly.

It would be desirable to be able to at least partially improve the power supplied by a battery to an electronic system or device.

Higher performance power is required from the battery of the electronic system or device.

It is desirable to detect the voltage drop across the battery of an electronic system or device.

It is desirable to prevent the voltage drop of the battery of an electronic system or device from occurring.

It is desirable to overcome all or some of the disadvantages of known battery power sources.

Disclosure of Invention

One embodiment provides a circuit for monitoring a first voltage delivered by a battery, the circuit comprising: a comparator configured to compare the first voltage with the second voltage; and a counter configured to start counting whenever the comparator indicates that the first voltage is less than the second voltage, wherein if the value of the counter exceeds a limit value during the counting, an interrupt signal is generated.

Another embodiment provides a method performed by a monitoring circuit for monitoring a first voltage delivered by a battery, the method comprising: comparing the first voltage with the second voltage; starting counting each time the first voltage is smaller than the second voltage; and generating an interrupt signal when the value of the counter exceeds a limit value during the counting.

According to one embodiment, the monitoring circuit further comprises a circuit configured to generate an interrupt signal when the comparator indicates that the first voltage is greater than the second voltage.

According to one embodiment, the interrupt signal is configured to modify an operating mode of an electronic device comprising the battery.

According to one embodiment, the electronic device switches to the low consumption mode if an interrupt signal is generated due to the value of the counter exceeding a limit value.

According to one embodiment, if the device is in a low consumption mode, an interrupt signal generated due to the value of the counter being greater than the limit value is disabled.

According to one embodiment, the apparatus includes a processor having a reduced clock frequency during a low consumption mode.

According to one embodiment, if an interrupt signal is generated because the first voltage is greater than the second voltage, the electronic device then switches to full power mode.

According to one embodiment, if the device is in full power mode, an interrupt signal generated as a result of the first voltage being greater than the second voltage is disabled.

According to one embodiment, the counter is configured to be reset to zero each time the first voltage is greater than the second voltage. According to one embodiment, the counter is configured to be reset to zero each time the value of the counter is greater than the limit value.

According to one embodiment, the second voltage is configurable.

According to one embodiment, the limit value is configurable.

In one embodiment, an electronic device includes a battery and a monitoring circuit as previously described.

According to one embodiment, the device further comprises near field communication circuitry.

Drawings

The above features and advantages and other features and advantages will be described in detail in the remaining disclosure of the particular embodiments, which is set forth by way of illustration and not limitation with reference to the accompanying drawings, wherein:

fig. 1 very schematically shows in block form an electronic device that can comprise the embodiments of fig. 3-5;

fig. 2A to 2B show graphs illustrating voltages delivered by a battery;

FIG. 3 shows a simplified embodiment of a circuit for monitoring the voltage delivered by a battery;

FIG. 4 shows another more detailed embodiment of a circuit for monitoring the voltage delivered by a battery; and

fig. 5 shows a timing diagram illustrating the operation of the embodiments of fig. 3 and 4.

Detailed Description

In the various drawings, like features have been designated by like reference numerals. In particular, structural and/or functional features common among the various embodiments may have the same reference numerals and may be provided with the same structural, dimensional, and material characteristics.

For clarity, only the steps and elements useful for understanding the embodiments described herein are illustrated and described in detail.

Unless otherwise indicated, when referring to two elements being connected together, this means that there is no direct connection of any intermediate element other than a conductor, and when referring to two elements being coupled together, this means that the two elements may be connected, or they may be coupled via one or more other elements.

In the following disclosure, unless otherwise specified, references to orientations shown in the figures are made to absolute positional modifiers (such as the terms "front", "back", "top", "bottom", "left", "right", etc.) or to relative positional modifiers (such as the terms "above", "below", "upper" and "lower", etc.) or to orientation modifiers (such as "horizontal", "vertical", etc.).

Unless otherwise specified, the expressions "about", "approximately", "substantially" and "approximately" mean within 10%, preferably within 5%.

Fig. 1 very schematically shows in block form one example of an electronic DEVICE 100 (DEVICE), which electronic DEVICE 100 can comprise an embodiment of the battery monitoring circuit described in relation to fig. 3-5.

The device 100 is an electronic device, such as a cell phone, a connected device, the energy supply of which is at least partially internally transported. Thus, the device 100 comprises an internal energy supply system 101 (ALIM), which internal energy supply system 101 comprises at least one battery 102 (BAT). The energy supply system 101 further comprises circuitry enabling to manage the energy supply of the device 100.

The device 100 also includes circuitry and electronic components that enable it to perform at least one (preferably multiple) function. These circuits and components are described as indicative and not limiting. It will be within the ability of those skilled in the art to determine which circuits or components are necessary for the device 100 depending on the function implemented by the device 100. More specifically, the device 100 may include: a processor 103 (CPU); one or more memories 104 (MEM); one or more internal and/or external communication circuits 105 (I/O), including, for example, a near field communication module 106 (NFC); various circuits 107 (FCTs) enabling them to perform various functions; and one or more bus interfaces 108 that enable different circuits and components to exchange data and/or power.

The circuitry 107 may include one or more data measurement or processing circuits, one or more secure elements (that is, reliable electronic devices that enable processing of critical data or secret data), one or more display devices, and the like.

In fig. 1, a single bus 108 is shown that couples all of the circuits and components of the device 100 together, but multiple buses 108 that couple some of the circuits and components together are contemplated.

Fig. 2A-2B show graphs illustrating the voltage delivered by a battery of the type of battery 102 of the device 100 described with respect to fig. 1. More specifically, fig. 2A represents a real-time measurement of the voltage VBAT delivered by the battery, and fig. 2B represents a simplified version of the time variation of the voltage VBAT.

The battery discussed herein is assumed to deliver a DC voltage, however, as can be seen in graph (a), the voltage VBAT delivered by the battery includes a DC component vbat_dc and an AC component vbat_ac.

The AC component vbat_ac includes a large voltage drop 201 or negative peak. These voltage peaks may often be neither expected nor avoided.

The DC component vbat_dc may also include a voltage drop 202, which voltage drop 202 differs from the voltage drop 201 in that the duration of the voltage drop 202 is longer than the duration of the voltage drop 201.

A problem that may occur is that when the DC component vbat_dc and the AC component vbat_ac simultaneously exhibit voltage drops, as at time t_lim visible in graph (a), the voltage VBAT may become less than the limit voltage vbat_lim and may interfere with the operation of the battery powered device.

In graph (B), the manner in which the voltage drop 202 of the DC component vbat_dc is detected is defined. Component vbat_dc is considered to exhibit voltage drop 202 when voltage VBAT is less than threshold voltage vbat_th, greater than limit voltage vbat_lim, during the voltage drop having minimum duration T1. According to one example, the minimum duration T1 is approximately 4ms.

The embodiments described with respect to fig. 3 to 5 aim to prevent the device from presenting a voltage drop of the type of voltage drop 202 as defined with respect to graph (B) so that it can act accordingly.

Fig. 3 illustrates, very schematically, in block form, one embodiment of a circuit 300 for monitoring the voltage delivered by a battery. The circuit 300 may form part of the power supply system 101 of the device 100 described in relation to fig. 1 and enable to prevent the device 100 from generating a voltage drop of the type of voltage drop 202 described in relation to fig. 1 on the voltage delivered by the battery 102.

The monitoring circuit 300 includes: a comparator 301 (COMP); an edge detector 302; a counter 303 (CNT); and an interrupt generator 304 (IT).

Comparator 301 includes at least three inputs IN, TH, and EN and at least one output OUT. The input IN receives the voltage to be compared, here the voltage VBAT delivered by the battery. The input TH receives a threshold voltage that is compared to the voltage received on the input IN, where the input TH receives a threshold voltage v_th that is defined IN the same manner as the voltage vbat_th described with respect to fig. 3. The input EN receives the voltage for enabling the comparator 301, where the input EN receives the voltage comp_en. The output OUT delivers a comparison voltage vbat_level obtained by comparing the voltage VBAT with a threshold voltage v_th. According to one example, when the voltage VBAT is greater than the threshold voltage v_th, the voltage vbat_level is at a first LEVEL, e.g., a high LEVEL, and when the voltage VBAT is less than the threshold voltage v_th, the voltage vat_level is at a second LEVEL, e.g., a low LEVEL.

The edge detector 302 includes at least one input IN and at least one output OUT. The input IN receives the comparison voltage vbat_level, and the output OUT delivers the edge detection voltage level_high. The edge detector 302 is configured to indicate to the device that the voltage VBAT is greater than the threshold voltage v_th by detecting a transition edge from the second LEVEL to the first LEVEL of the comparison voltage vbat_level. In other words, whenever the voltage vbat_level indicates that the voltage VBAT is greater than the threshold voltage v_th, the output voltage level_high of the detector 302 indicates it, for example, by switching to a third LEVEL (e.g., HIGH LEVEL).

According to one practical example, if the comparison voltage vbat_level is at a high LEVEL when the voltage VBAT is greater than the threshold voltage v_th, the detector 302 is a rising edge detector. In the opposite case, the detector 302 is a falling edge detector. Those skilled in the art will be able to adjust the rest of the circuit 300 according to these two alternatives.

Counter 303 (CNT) includes at least five inputs IN, EN, CLK, RST and LIM and at least one output OUT. The input IN receives the comparison voltage vbat_level. The input EN receives a voltage for enabling the counter 302, where the input EN receives the voltage cnt_en. The input CLK receives the clock signal of the counter 302, where the input CLK receives the signal cnt_clk. The input RST receives a voltage for resetting the counter 302, thereby enabling the counter 302 to be reset to its initial value, where the input RST receives the voltage cnt_rst. According to one example, the voltage cnt_rst depends on the voltage level_high. The input LIM receives a voltage cnt_lim for programming a limit value that is compared with the value of the counter. The limit value is determined such that the counter needs to count from its initial value to the limit value for a time of about the duration T1 defined with respect to fig. 2A to 2B. The output OUT delivers an output voltage LEVEL LOW indicating whether the value of the counter 303 has exceeded the limit value CNT LIM.

Interrupt generation 304 includes at least two inputs and an output OUT. The generator 304 receives voltages level_high and level_low at ITs inputs and outputs an interrupt signal IT. The generator 304 takes into account the information of the voltages level_high and level_low to generate an interrupt indicating to the device that the voltage VBAT delivered by the battery exhibits a voltage drop with an extended duration or has become greater than the threshold voltage v_th.

The operation of the circuit 300 is as follows. The comparator circuit 301 continuously compares the voltage VBAT and the threshold voltage v_th to deliver the voltage vbat_level. Two situations may occur.

First case: the voltage VBAT is less than the threshold voltage v_th. The comparison voltage vbat_level indicates this information by being at a second LEVEL (e.g., low LEVEL). The counter 303 has been started from the time when the voltage VBAT has become smaller than the threshold voltage v_th.

If the value of the counter reaches the limit value CNT LIM without a change in the state of the voltage VBAT LEVEL, the voltage drop of the voltage VBAT is considered to have continued too long and the device powered by the battery delivering the voltage VBAT must be alerted. In this case, an interrupt signal must be sent. Then, the counter 303 is reset to zero. However, if the counter value is reset to zero, for example because the voltage vbat_level exhibits a new edge, no interrupt signal is sent.

The interrupt signal may have different consequences. It enables the device to be informed that the battery performance is insufficient for its proper operation. According to one embodiment, upon receipt of the interrupt signal, the device may decide to switch to a "low consumption" mode or a "low power" mode, that is, a mode in which the device reduces its power consumption. According to a preferred embodiment, during a "low consumption" mode, the device may reduce the operating frequency of its processor.

Second case: the voltage VBAT is greater than the threshold voltage v_th. At a time when the voltage VBAT has become greater than the threshold voltage v_th, the detector 302 notifies the generator 304, and the generator 304 generates an interrupt signal.

The interrupt signal may have different consequences. It enables notification to the device that the battery performance has again become sufficient for it to operate properly. According to one embodiment, upon receipt of the interrupt signal, the device may decide to switch back to the normal consumption mode, that is, the mode in which the device does not reduce its power consumption. The interrupt signal is also intended to reset the counter to its initial value.

The monitoring circuit and its operation are described in further detail with respect to fig. 4 and 5.

Fig. 4 shows, in block form, in part, a more detailed embodiment of a circuit 400 for monitoring the voltage delivered by a battery of the type of monitoring circuit 300 described with respect to fig. 3.

Similar to circuit 300, circuit 400 is configured to be included in a system for powering an electronic device D of the type of device 100 described with respect to fig. 1. Thus, the battery with the circuit 400 associated therewith is of the type of battery 102, and the circuit 400 forms part of the power supply circuit 101.

The circuit 400 comprises a comparator 401 (COMP) of the type of comparator 301 described in relation to fig. 3. Thus, comparator 401 includes at least three inputs IN, TH, and EN and at least one output OUT. The input IN receives the voltage to be compared, here the voltage VBAT delivered by the battery of the device D. The input TH receives a threshold voltage that is compared to the voltage received on the input IN, where the input TH receives a threshold voltage v_th. The input EN receives the voltage for enabling the comparator 401, where the input EN receives the voltage comp_en. The output OUT delivers a comparison voltage vbat_level obtained by comparing the voltage VBAT with a threshold voltage v_th. In the example of circuit 400, when voltage VBAT is greater than threshold voltage v_th, voltage vbat_level is at a high LEVEL, and when voltage VBAT is less than threshold voltage v_th, voltage vbat_level is at a low LEVEL. Those skilled in the art will be able to adjust the circuit 400 in the opposite case.

The circuit 400 also optionally includes a circuit 402 (TH), the circuit 402 for generating a voltage that provides a threshold voltage v_th. The circuit 402 may be a configurable voltage source driven by the control unit of the device D. According to one variation, the circuit 402 may be a simple voltage source. According to another variation, the circuit 402 may be external to the circuit 400 and/or external to the device D.

The circuit 400 further includes a counter 403 (CNT), the counter 403 (CNT) being associated with a first AND type logic gate 404 AND a second AND type logic gate 405.

The counter 403 (CNT) includes at least four inputs IN, CLK, EN and RST and at least one output OUT. Input IN receives a voltage level_en delivered by the output of gate 404, described IN further detail below. The clock signal of the counter 403 is input to the CLK reception counter, where the CLK reception signal cnt_clk is input. The input EN receives the voltage for enabling the counter 403, where the input EN receives the voltage cnt_en. The input RST receives a voltage for resetting the counter 403, thereby enabling the counter 403 to be reset to its initial value, where the input RST receives the voltage cnt_rst. The output OUT delivers an output signal cnt_low indicating the value of the counter 403.

Logic gate 404 is an and type logic gate that includes an inverting input that receives voltage vbat_level and a non-inverting input that receives voltage cnt_en. The logic gate 404 outputs a voltage level_en. The logic gate 404 is intended to invert the voltage vbat_level and to transfer it to the counter 403 only if the counter 403 is enabled by the voltage cnt_en.

The logic gate 405 is an and type gate that includes an input that receives a signal cnt_low and an input that receives a signal cnt_lim that represents a limit value of a counter. The logic gate 405 outputs a signal low_irq indicating whether the value of the counter symbolized by the signal cnt_low has reached the limit value cnt_lim as previously defined. The logic gate 405 is intended to verify whether the value of the counter is equal to a limit value.

The circuit 400 optionally further comprises a circuit 406 (LIM), the circuit 406 being arranged to generate a signal cnt_lim symbolizing the limit value of the counter 403. The circuit 406 may be a configurable signal source driven by the control unit of the device D. According to a variation, circuitry 406 may be external to circuitry 400 and/or external to device D.

The circuit 400 further comprises a rising edge detector 407, which rising edge detector 407 receives as input the voltage vbat_level and outputs a signal det_high. The detector 407 is of the type of detector 302 described in relation to fig. 3. The detector 407 is configured to indicate to the device D that the voltage VBAT is greater than the threshold voltage v_th by detecting a rising edge of the voltage vbat_level. In other words, whenever the voltage vbat_level indicates that the voltage VBAT is greater than the threshold voltage v_th, the signal det_high indicates it, for example, by switching to a HIGH LEVEL.

The circuit 400 further includes a logical AND type gate 408, the logical AND type gate 408 including an input to receive the signal det_high AND an input to receive the voltage cnt_en. The logic gate 408 outputs a voltage high_irq. The logic gate 408 is intended to filter the output of the detector 407 only when the counter 403 is disabled.

The circuit 400 further comprises a circuit 409 for resetting the counter 403, the circuit 409 taking into account the information of the signals det_high and low_irq to obtain the voltage cnt_rst. According to the example of fig. 4, the reset circuit 409 is an OR (OR) type logic gate that receives as inputs the signals det_high and low_irq.

The circuit 400 further includes a circuit 410, the circuit 410 being configured to enable and disable interrupts derived from voltage drops or voltage rises (voltage rise). In FIG. 4, circuit 410 includes AND type logic gate 410-1 AND AND type gate 410-2.

Gate 401-1 is configured to enable and disable interrupts obtained by the voltage boost. For this purpose, gate 410-1 receives as inputs the signal HIGH_IRQ and the enable signal HIGH_IRQ_EN, and outputs the signal HIGH_IRQ_2.

The gate 410-2 is configured to enable and disable interrupts obtained by the voltage drop. To this end, the gate 410-2 receives as inputs the signal LOW_IRQ and the enable signal LOW_IRQ_EN, and outputs the signal LOW_IRQ_2.

Finally, the circuit 400 also includes an interrupt generation circuit 411. In fig. 4, circuit 411 is an OR logic gate that receives signals high_irq_2 and low_irq_2 as inputs and outputs signal IRQ.

Fig. 5 shows a timing diagram of the voltages and signals of the monitoring circuit 400 described with respect to fig. 4, thereby enabling the operation of the circuit 400 to be described.

Specifically, FIG. 5 includes a timing diagram of voltage VBAT, a timing diagram of voltage VBAT_LEVEL, a time representation of operating mode CNT_STATE of counter 403, a timing diagram of signal LOW_IRQ_EN, a timing diagram of signal HIGH_IRQ_EN, a timing diagram of interrupt signal IRQ, and a time representation of operating mode DEVICE_STATE of DEVICE D.

At the initial time t0, the previously mentioned signal, counter 403 and device D are in the following states.

The voltage VBAT of the battery of device D is greater than the threshold voltage v_th, the level of which is shown by the dashed line.

The voltage vbat_level representing the result of the comparison between the voltage VBAT and the threshold voltage v_th is in a high state, thereby indicating that the voltage VBAT is greater than the threshold voltage v_th.

The counter 403 has been reset and is therefore in an initial state marked "0" (0). The counter 403 does not count.

The signal low_irq_en is in a state indicating that an interrupt due to the voltage VBAT being less than the threshold voltage v_th for an extended duration is authorized. According to one example, the signal LOW_IRQ_EN is in a high state.

The signal high_irq_en is in a state indicating that the interrupt due to the voltage VBAT being greater than the threshold voltage v_th for an extended duration is not authorized. According to one example, the signal LOW_IRQ_EN is in a LOW state.

The interrupt signal IRQ is in a state indicating that no interrupt is transmitted at time t 0. According to one example, the signal IRQ is in a low state.

Device D is in a "full power" mode of operation (HIGH PERF) in which it does not particularly reduce its power consumption.

At time t1 after time t0, the voltage VBAT decreases and becomes lower than the threshold voltage v_th. The voltage vbat_level then exhibits a falling edge, which enables the counter 403 to be started. Then, the counter 403 is in a count state (1, 2, 3, … …).

At time t2 after time t1, the voltage VBAT increases and becomes greater than the threshold voltage v_th. The voltage vbat_level then exhibits a rising edge. The counter 403 stops counting and switches back to its initial value (0). The duration between time t1 and time t2 is not long enough and the counter 403 has not had time to end its count, in other words the value of the counter 403 remains below the limit value cnt_lim.

Further, at time t2, device D is in a "full power" operating state during which device D does not attempt to reduce its power consumption, and the interruption due to voltage VBAT being greater than threshold voltage v_th is not authorized. In other words, the signal HIGH_IRQ_EN is in a low state. Thus, no interrupt IRQ is generated.

Until time t5 after time t2, the voltage VBAT oscillates between a value greater than the threshold voltage v_th and a value less than the threshold voltage v_th, and this makes the counter value unsuccessful in reaching the limit value cnt_lim. More specifically: at time t3 after time t2, voltage VBAT becomes smaller than the threshold voltage; at time t4 after time t3, the voltage VBAT becomes greater than the threshold voltage v_th; and at time t5 after time t4, the voltage VBAT becomes smaller than the threshold voltage v_th.

At time t6 after time t5, the increment value of the counter 403 reaches the limit value cnt_lim. The signal LOW IRQ EN is in a high state and an interrupt may be sent, the signal IRQ thus briefly transitioning to a high state. Upon receiving the interrupt, device D may switch to a "low consumption" mode or a "low power" mode, in which device D reduces its power consumption as previously described. Further, the counter 403 is reset to its initial value.

Further, by switching to the "low consumption" mode, device D modifies the type of interrupt that it can receive. In fact, only interrupts indicating that the voltage VBAT is greater than the threshold voltage v_th are of interest. Thus, the signal low_irq_en switches to a LOW state and the signal high_irq_en switches to a HIGH state.

At time t7 after time t6, the voltage VBAT becomes greater than the threshold voltage v_th. The signal high_irq_en is in a HIGH state and an interrupt may be sent, the signal IRQ thus briefly transitioning to a HIGH state. Upon receiving the interrupt, device D may switch back to a "full power" mode in which device D no longer reduces its power consumption.

Further, by switching to the "full power" mode, device D modifies the type of interrupt that it can receive. Thus, the signal low_irq_en switches to a HIGH state, and the signal high_irq_en switches to a LOW state.

Various embodiments and modifications have been described. Those skilled in the art will appreciate that certain features of these various embodiments and variations may be combined, and that other variations will occur to those skilled in the art.

Finally, based on the functional indications given above, the actual implementation of the described embodiments and variants is within the ability of a person skilled in the art.

Claims

1. A circuit for monitoring a first voltage delivered by a battery, comprising:

a comparator configured to compare the first voltage with a second voltage and to generate a first logic signal having a logic state dependent on the comparison;

an edge detector configured to receive the first logic signal and assert a second logic signal in response to detecting an edge of the first signal indicating that the first voltage has exceeded the second voltage;

a counter configured to start counting whenever the logic state of the first logic signal indicates that the first voltage is less than the second voltage, and to generate a third logic signal having a logic state that depends on whether a value of the counter exceeds a count limit; and

a combinational logic circuit configured to logically combine the second logic signal and the third logic signal to generate a fourth logic signal;

wherein the logic state transition of the fourth logic signal controls a modification of an operating mode of an electronic device comprising the battery between a high performance operating mode and a low performance operating mode.

2. The circuit of claim 1, wherein the combinational logic circuit comprises:

a first logic AND gate having a first input configured to receive the second logic signal, a second input configured to receive a first enable signal, and an output configured to generate a fifth logic signal, the first enable signal being asserted to a logic high when the electronic device is in the low performance mode of operation;

a second logic AND gate having a first input configured to receive the third logic signal, a second input configured to receive a second enable signal, and an output configured to generate a sixth logic signal, the second enable signal being asserted to a logic high when the electronic device is in the high performance mode of operation; and

a first logic or gate having a first input configured to receive the fifth logic signal, a second input configured to receive the sixth logic signal, and an output configured to generate the fourth logic signal.

3. The circuit of claim 2, wherein in response to the first enable signal being asserted to a logic high and the assertion of the second logic signal, the fourth logic signal generates a pulse to indicate to the electronic device comprising the battery to switch from the low-performance mode of operation to the high-performance mode of operation.

4. The circuit of claim 2, wherein in response to the second enable signal being asserted to a logic high and the assertion of the third logic signal, the fourth logic signal generates a pulse to indicate to the electronic device comprising the battery to switch from the high-performance mode of operation to the low-performance mode of operation.

5. The circuit of claim 2, wherein the combinational logic circuit further comprises a second logic or gate having a first input configured to receive the second logic signal and a second input configured to receive the third logic signal and an output configured to generate a counter reset signal that is applied to control a reset of the counter.

6. An electronic device, comprising: a battery and a monitoring circuit according to claim 1.

7. The electronic device defined in claim 6 further comprising near field communication circuitry.

8. A circuit for monitoring a first voltage delivered by a battery, comprising:

a comparator configured to compare the first voltage with a second voltage;

a counter configured to start counting each time the comparator indicates that the first voltage is less than the second voltage; and

logic circuitry configured to generate an interrupt signal;

wherein the interrupt signal is generated when the value of the counter exceeds a limit value during the counting; and

wherein the interrupt signal is generated when the comparator indicates that the first voltage is greater than the second voltage.

9. The circuit of claim 8, wherein the interrupt signal is configured to modify an operating mode of an electronic device that includes the battery.

10. The circuit of claim 9, wherein when the interrupt signal is generated as a result of the value of the counter exceeding the limit value, then the electronic device switches to a low consumption mode.

11. The circuit of claim 10, wherein when the electronic device is in a low consumption mode, then generating the interrupt signal is disabled because the value of the counter is greater than the limit value.

12. The circuit of claim 11, wherein modifying the mode of operation comprises: the clock frequency of the processor is reduced during the low consumption mode.

13. The circuit of claim 8, wherein when the interrupt signal is generated as a result of the first voltage being greater than the second voltage, then the electronic device switches to a full power mode.

14. The circuit of claim 13, wherein generating the interrupt signal is then disabled when the device is in full power mode because the first voltage is greater than the second voltage.

15. The circuit of claim 8, wherein the counter is configured to be reset each time the first voltage is greater than the second voltage.

16. The circuit of claim 8, wherein the counter is configured to be reset each time the value of the counter is greater than the limit value.

17. The circuit of claim 8, wherein the second voltage is configurable.

18. The circuit of claim 8, wherein the limit value is configurable.

19. An electronic device comprising a battery and the monitoring circuit of claim 8.

20. The electronic device defined in claim 19 further comprising near field communication circuitry.