CN116781111A - NFC module power supply - Google Patents

Abstract

The present disclosure relates to NFC module powering. An electronic device includes a near field communication module and a power supply circuit for delivering a supply voltage to the near field communication module. When the near field communication module is in the low power mode, the power supply circuit is configured to an operating mode in which the power supply circuit is periodically activated to provide a supply voltage.

Description

NFC module power supply

Cross Reference to Related Applications

The present application claims priority from the french patent application No. 2202283 filed 3/16/2022, the contents of which are incorporated herein by reference in their entirety to the maximum extent allowed by law.

Technical Field

The present disclosure relates generally to power supplies for electronic devices, and more particularly, to Near Field Communication (NFC) modules included in electronic devices. The present disclosure more particularly relates to different power modes of a near field communication module included in an electronic device.

Background

Currently, power consumption of electronic devices is an important issue in the industry. Reducing the power consumption of a device while ensuring its proper operation and performance is one of the main objectives of development.

It is desirable to at least partially improve certain aspects of the power supply of an electronic device comprising a near field communication module.

Electronic devices that consume less power are needed.

A near field communication module consuming less power is required.

It is desirable to overcome all or part of the disadvantages of known electronic devices.

Disclosure of Invention

An embodiment that addresses all or part of the shortcomings of known near field communication modules is provided by an electronic device comprising: a near field communication module; and a power supply circuit for the module, wherein the power supply circuit is configured to periodically start when the near field communication module is in a low power mode.

Another embodiment provides a method of powering a near field communication module of an electronic device in a low power mode, the method further comprising a power supply circuit for the module, wherein the power supply circuit is configured to be periodically activated when the near field communication module is in the low power mode.

According to one embodiment, in a low power mode of the near field communication module, the power supply circuit is controlled by a control circuit adapted to periodically activate the power supply circuit.

According to one embodiment, the control circuit comprises a counter.

According to one embodiment, in a low power mode of the near field communication module, a counter is started and when the value of the counter reaches a threshold value, a power supply circuit is started.

According to one embodiment, in a low power mode of the near field communication module, when the value of the counter reaches a limit value that is greater than a threshold value, the power supply circuit is stopped and the value of the counter is reset to zero.

According to one embodiment, the near field communication module comprises a field detector.

According to one embodiment, in a low power mode of the near field communication module, when a power supply circuit is activated, the near field communication module is powered on and its field detector is activated.

According to one embodiment, the near field communication module further comprises a circuit configured to compare the frequency of the electric field detected by the field detector with a reference frequency.

According to one embodiment, the frequency comparator circuit is a state machine.

According to one embodiment, during the low power mode, an alarm signal is generated when the circuit concludes that the frequency of the field detected by the field detector is equal to a reference frequency, with an error margin on the order of 10%.

According to one embodiment, the device further comprises a circuit for powering a processor adapted to receive the alarm signal.

According to an embodiment, the circuit for powering comprises a voltage regulator adapted to regulate an internal supply voltage and to deliver a voltage for powering the near field communication module.

According to one embodiment, the circuit for supplying power further comprises a circuit for a reference voltage conveyed by the bandgap.

According to one embodiment, the control circuit further comprises a circuit for a reference voltage conveyed by the bandgap.

Drawings

The above features and advantages and other features and advantages are described in detail in the remainder of the disclosure of particular embodiments, which are presented by way of illustration and not of limitation with reference to the accompanying drawings wherein:

fig. 1 very schematically shows in block form an electronic device to which the embodiments described in connection with fig. 3-5 can be applied;

fig. 2A-2B very schematically show two block diagrams in the form of blocks showing different power modes of the electronic device and the near field communication module;

FIG. 3 very schematically illustrates an embodiment of a portion of an embodiment of an electronic device in block form;

FIG. 4 illustrates in block form a more detailed embodiment of a portion of an embodiment of an electronic device; and

fig. 5A-5B show timing diagrams illustrating the operation of the embodiment of fig. 4.

Detailed Description

In the various drawings, like features have been designated by like reference numerals. In particular, structural and/or functional features common in various embodiments may have the same references and may be provided with the same structural, dimensional, and material properties.

For clarity, only the steps and elements useful for understanding the embodiments described herein have been illustrated and described in detail. In particular, near field communication protocols are not described herein, which are compatible with the embodiments described below.

Unless otherwise indicated, when two elements are referred to as being connected together, this means that there is no direct connection of any intermediate element other than a conductor, and when two elements are referred to as being connected together, this means that the two elements may be connected or they may be connected via one or more other elements.

In the following disclosure, unless otherwise indicated, when absolute positional qualifiers, such as the terms "front", "rear", "upper", "lower", "left", "right", etc., or relative positional qualifiers, such as the terms "upward", "downward", etc., or directional qualifiers, such as "horizontal", "vertical", etc., are referred to the directions shown in the drawings.

Unless otherwise indicated, the expressions "about", "substantially" and "about equal to" mean within 10%, preferably within 5%.

Fig. 1 very schematically shows an example of an electronic DEVICE 100 (DEVICE) in the form of a block, to which the embodiments described in connection with fig. 3, 4 and 5A-5B can be applied.

The device 100 is an electronic device, such as a cellular telephone or a connected device, the power of which is at least partially transmitted internally. Thus, the apparatus 100 comprises: a processor 101 (CPU); one or more memories 102 (MEM); one or more circuits 103 (FCTs) implementing different functions of the device 100; a power supply circuit 104 (ALIM); a near field communication module 105 (NFC) or NFC module 105; optionally, a secure element 106 (SE); and one or more computer buses 107, enabling the different circuits and components to exchange data and/or power.

Processor 101 may be a main processor responsible for implementing, for example, the basic and/or complex functions of device 100. For example, the device 100 may include other processors, such as an auxiliary processor linked to a particular task.

The one or more memories 102 are data storage units of the device 100. The memory 102 may be of different types, such as RAM, volatile memory, non-volatile memory, ROM, etc.

The circuitry 103 may include one or more data measurement or processing circuits, one or more display devices, and the like.

The power supply circuit 104 is a circuit for powering the device 100 and each of its circuits and components. The power supply circuit 104 may include power supply circuitry specific to particular circuits or components of the device 100. According to an example, the power supply circuit comprises at least one circuit for powering the NFC module 105. The power supply circuit 104 may also include an internal power source, such as a battery or voltage source. The power supply circuit 104 may also include circuitry configured to adapt power from an external source (e.g., from a mains).

NFC module 105 is a Near Field Communication (NFC) module that uses short range and high frequency wireless communication technologies, allowing data exchange between peripheral devices up to a distance of about 10 cm.

The secure element 106 is a reliable electronic device capable of handling critical or secret data. The secure element 106 may be used to perform data encryption and/or decryption, operations on critical data, and/or store critical data. The security element 106 is optional.

In fig. 1, a single bus 107 is shown and couples all of the circuits and components of the device 100 to each other, although multiple buses 107 coupling certain circuits and components to each other are contemplated.

Fig. 2A-2B are diagrams illustrating examples of different possible power modes of an electronic device. Fig. 2A shows examples of different possible power modes for an electronic DEVICE 200 (DEVICE) of the type of DEVICE 100 described in connection with fig. 1. Fig. 2B shows an example of a near field communication module 250 (NFC) or different power modes of an NFC module 250 forming part of the device 200, the near field communication module 250 (NFC) or NFC module 250 being of the type of NFC module 105 described in connection with fig. 1.

For example, the electronic device 200 as shown in the illustration of fig. 2A includes at least three different power modes during which the electronic device 200 consumes more or less power and/or may implement more or less functionality. The electronic device 200 may include other variations of power modes in addition to the power modes described below. The power mode is as follows: a "full power" mode 201; a "low power" mode 202; and a "sleep" mode 203.

The "full power" mode 201 is the power mode in which the electronic device 200 may consume the most power. All its functions can be used.

The "low power" mode or "low power" mode 202 is a power mode in which the electronic device 200 reduces its power consumption. To this end, the electronic device 200 may prevent the implementation of certain functions and/or intentionally slow the implementation of some or all of its functions, for example, by slowing the operation of its processor.

The "sleep" or standby mode 203 is a power mode in which the electronic device 200 substantially reduces its power consumption by authorizing only certain very specific functions. More specifically, in this power mode, most of the functions of the device 200 are disabled and only the functions that enable "wake up" the device 200 are enabled. Herein, it is referred to as functions capable of "waking up" the device 200, which functions are adapted to cause the device 200 to switch from a "sleep" mode to another power mode, such as a "full power" mode or a "low power mode. These functions are, for example, detecting a communication request, such as a near field communication request or a telephone call request, if the device 200 is a telephone, by pressing a button of the device 200 to leave the mode. Thus, NFC module 250 typically forms part of the circuitry of device 200 that is powered during sleep mode.

For example, the NFC module 250 shown in the illustration of fig. 2B includes at least two different power modes during which the NFC module 250 consumes more or less power and/or may implement more or less functionality. NFC module 250 may include other power modes in addition to the power modes described below. The power mode is as follows: a "full power" mode 251; and a "low power" mode 252.

The "full power" mode 251 is a power mode in which the NFC module 250 may consume the most power. During this mode, NFC module 250 may periodically detect the presence of a field, for example, at a frequency on the order of 1kHz, or may even continuously detect the presence of a field.

The "low power" mode or "low power" mode 252 is a power mode in which the NFC module 250 reduces its power consumption. For this purpose, NFC module 250 may for example slow down its field detection frequency to a frequency of the order of 500 Hz. Fig. 3, 4 and 5A-5B illustrate embodiments of circuits for powering NFC modules, and more particularly, their implementation in a "low power" mode.

The different power modes of the device 200 and the NFC module 250 are independent of each other. For example, device 200 may be in sleep mode and NFC module 250 may be in full power mode. According to another example, if the user of device 200 decides not to use the NFC module, it may set it to a "low power" mode.

Fig. 3 very schematically shows in block form a part 300 of a device of the type of device 100 described in connection with fig. 1 or of the type of device 200 described in connection with fig. 2.

The portion 300 includes: a near field communication module 301 (NFC) or NFC module 301; power supply circuitry 302 (ALIM NFC) associated with NFC module 301; and a control circuit 303 (CMD).

NFC module 301 is of the type of NFC module 105 described in connection with fig. 1 or of NFC module 250 described in connection with fig. 2. The NFC module 301 is configured to transmit and receive an electric field to enable near field communication. The NFC module comprises at least one power supply terminal ALIM-NFC and one internal communication terminal I/O-NFC. The power supply terminal ALIM-NFC is coupled (preferably connected) to the power supply circuit 302. The internal communication terminal I/O-NFC enables the NFC module to exchange data and instructions with the rest of the electronic device, such as alarm signals or detection information of fields that can cause NFC communication. As previously described, NFC module 301 includes a plurality of different power modes, for example, at least one "full power" power mode and at least one "low power" power mode. During the "low power" mode, NFC module 301 reduces the frequency at which it attempts to detect the electromagnetic field.

The power supply circuit 302 is a circuit configured to manage the power supply of the NFC module 301. For this purpose, the circuit 302 comprises at least one input terminal IN receiving the supply voltage VBAT, an output terminal OUT for the purpose of delivering the supply voltage VSUPP-NFC to the NFC module 301, and a control terminal CMD. The supply voltage VBAT is communicated to the circuit 302, for example, by an internal power source of the electronic device, such as a battery, or by a circuit for converting power external to the device to which it is coupled. The control terminal CMD enables the power supply circuit 302 to be turned on or off. A more detailed embodiment of the power supply circuit 302 is described in connection with fig. 4.

The control circuit 303 is a circuit configured to control the power supply circuit 302 and more precisely control the power supply circuit 302 when the NFC module 301 is in the "low power" mode. The counter 303 includes a power supply terminal ALIM-CMD that receives the voltage VBAT, an input terminal IN that receives programming data, and an output terminal OUT. The input terminal IN receives data notifying the control circuit 303 of the power mode of the NFC module 301 and, for example, the power mode of the device. According to an example, the input terminal IN receives these data directly from the NFC module 301. The output terminal OUT transmits a control voltage to the control terminal CMD of the power supply circuit 302. A more detailed embodiment of counter 303 is described in connection with fig. 4.

The operation of portion 300 is as follows.

During the "full power" mode of the NFC module 301, the power supply circuit 302 is always activated, enabled and supplies power to the NFC module 301.

During the "low power" mode of NFC module 301, and according to an embodiment, control circuit 303 periodically enables power supply circuit 302 such that power supply circuit 302 consumes power only when NFC module 301 requires power. More precisely, the NFC module 301 periodically implements the field search only during the "low power" mode, and the power supply circuit 302 is periodically enabled by the control circuit 301 to supply power only when the NFC module 301 attempts to detect the field. If the NFC module 301 detects a field, the power supply circuit 302 may remain enabled until the NFC module 301 has finished the actions it has to do, an example of which is described in connection with fig. 4. If the NFC module 301 does not detect a field, the power supply circuit 302 is turned off.

An advantage of this embodiment is that it enables limiting the power consumption of the electronic device during implementation of the "low NFC module power" mode.

Fig. 4 very schematically shows in block form a part 400 of a device of the type of part 300 of the device described in connection with fig. 3. Portion 400 is a more detailed practical example than portion 300 described previously. The operation of portion 400 during the "low power" mode of the NFC module is described in connection with the timing diagram of fig. 5.

Portion 400 includes: near field communication mode 401 (NFC) or NFC module 401, as shown by the dashed lines in fig. 4; a power supply circuit 402 (ALIM NFC) associated with the NFC module 401, shown in dashed lines in fig. 4; a control circuit 403 (CMD), as shown by the dashed line in fig. 4; a master voltage regulator 404 (LDO Main); a secondary voltage regulator 405 (LDO LP); and components of "low power" circuitry 406 (LP domain).

NFC module 401 is partially shown in fig. 4 and includes at least one field detector 4011 (EFD) and a state machine 4012 (EFD FSM). Both the field detector 4011 and the state machine 4012 are powered by a voltage vsupp_nfc provided by the power supply circuit 402.

The field detector 4011 is a circuit configured to detect a field and in particular to find the frequency of the field it detects. The field detector 4011 has other functions commonly used by those skilled in the art, which are not described herein. The field detector 4011 includes a power supply terminal that receives the voltage vsupp_nfc, an enable terminal that receives the enable signal efd_en, and a frequency output terminal that transmits a signal f_efd representing the frequency of the field detected by the field detector 4011. For example, the signal f_efd is a clock signal having a frequency equal to the frequency of the field detected by the field detector 4011. In other words, the field detector 4011 extracts the frequency of the field it detects and transmits it in the form of a clock signal.

State machine 4012 is a circuit configured to: enabling the field detector 4011; verifying whether the field detector 4011 detects a field that is likely to transmit near field communication; and informs the device that near field communication is detected.

To this end, the state machine 4012 comprises: a power supply terminal receiving a voltage vsupp_nfc; providing an enable signal EFD_EN to a terminal of the field detector 4011; the terminal receives the signal F_EFD; a terminal for providing an alarm signal fsm_info or an information signal fsm_info to the device; and supplies a signal cnt_rst for resetting the counter to a terminal of the control circuit 403.

The power supply circuit 402 (ALIM NFC) associated with the NFC module 401 includes at least: a reference voltage circuit transmitted by the bandgap circuit 4021 or the reference voltage circuit 4021; logic "AND" gate 4022; and a secondary voltage regulator 4023 (EFD LDO).

The reference voltage circuit 4021 is powered by the internal supply voltage VBAT, transmits the reference voltage V-REF, and is thus configured to transmit the status signal BG_RDY. The reference voltage circuit 4021 also receives an enable signal bg_en. The supply voltage VBAT is communicated to the circuit 402, for example, by an internal power source of the electronic device, such as a battery, or by a circuit for converting power external to the device to which it is coupled.

The logic gate 4022 is an "AND" gate including two inputs, a first input receiving the status signal bg_rdy from the reference voltage circuit 4021 AND a second input receiving the enable signal alim_en from the control circuit 403. The logic gate 4022 outputs a signal ldo_en for enabling the voltage regulator 4023.

The voltage regulator 4023 is a voltage regulator that enables the transfer of the supply voltage vsupp_nfc from the voltage VBAT to the NFC module 401 when it is enabled. To this end, the voltage regulator 4023 receives the voltage VBAT, the reference voltage v_ref, and the enable signal ldo_en to output the supply voltage vsupp_nfc.

Control circuitry 403 (CMD) associated with power supply circuitry 402 includes, for example, low frequency oscillator 4031 (LFO) and counter 4032 (CNT). When NFC module 401 is in "full power" mode, control circuit 403 is configured to permanently enable power supply circuit 402. When the NFC module 401 is in the "low power" mode, the control circuit 403 is configured to periodically enable the power supply circuit 402.

The low frequency oscillator 4031 is an oscillator that supplies the clock signal Clk at a constant frequency. According to an example, the clock signal has a frequency in the range of 60 to 70kHz, for example on the order of 64 kHz. For this purpose, the low-frequency oscillator 4031 is supplied with the supply voltage VBAT.

Counter 4032 is a circuit configured to periodically begin powering circuit 402. For this, the counter 4032 receives the clock signal Clk, the reset signal rst_cnt, and outputs the enable signal bg_en and the enable signal alim_en. The value of counter 4032 is incremented, for example, at each new rising or falling edge of clock signal Clk. The more detailed operation of the counter 4032, and the more detailed operation of the more general control circuit 403, is described in more detail in connection with fig. 5.

The master voltage regulator 404 (LDO Main) is a voltage regulator configured to deliver a supply voltage that forms the master power supply of the device. According to an example, the regulator 404 communicates a supply voltage capable of powering a main processor of the device and an information signal ldo_info to the secondary voltage regulator 405. The regulator receives a voltage VBAT and an information voltage fsm_info.

The secondary voltage regulator 405 (LDO LP) is a voltage regulator configured to deliver a supply voltage of a secondary power supply forming a device. According to the example of fig. 4, regulator 405 provides a supply voltage that enables all "low power" circuits of the device to be powered with voltage VSUPP-LP. Regulator 405 receives voltage VBAT and information signal ldo_info. For example, the information signal ldo_info may enable the regulator 404 to indicate its operating state to the regulator 405.

An assembly 406 of "low power" circuits (LP domain) is an assembly of circuits and components of a device that are powered when the device is in a "low power" mode. According to an example, when the device is in "full power" mode, both regulators 404 and 405 are enabled, but when the device is in "low power" mode, regulator 404 is disabled and regulator 405 is enabled.

According to alternative embodiments, the reference voltage circuit 4021 may form part of the control circuit 403 instead of the power supply circuit 402.

Fig. 5A-5B show timing diagrams illustrating the operation of the portion 400 of the device described in connection with fig. 4 when the NFC module 401 is in a "low power" mode. Fig. 5A shows the operation of the portion 400 when the NFC module 401 is in the "low power" mode and the field detector 4011 does not detect a field. Fig. 5B shows the operation of the portion 400 when the NFC module 401 is in the "low power" mode and the field detector 4011 detects a field.

Fig. 5A includes a timing diagram of the following signals: a clock signal Clk; a signal en_bg for enabling the reference voltage circuit 4021; a state signal bg_rdy of the reference voltage circuit 4021; signal efd_en for enabling field detector 4011; and a signal rst_en for resetting the counter 4032.

At an initial time t0, all signals of fig. 5A are in a low state, e.g., the voltage level is equal to a reference voltage, e.g., voltage v_ref or another voltage. The clock signal Clk has regular rising and falling edges.

At time t1 after time t0, enable signal en_bg switches from a low state to a high state, e.g., a voltage level higher than the reference voltage level. In other words, the counter 4032 starts the start of the reference voltage circuit 4021. According to an example, the counter 4032 initiates the start of the reference voltage circuit because its value has reached the threshold value. In parallel, the counter 4032 indicates to the power supply circuit 402 that it requests its start, e.g., via an enable signal alim_en that also transitions from a low state to a high state.

At time t2 after time t1, the state signal bg_rdy transitions from the low state to the high state. Thus, the reference voltage circuit 4021 indicates that its start phase has ended, and that it is ready to be used.

By transitioning to a high state, the signal bg_rdy allows the voltage regulator 4023 to be enabled via the enable signal ldo_en.

At time t3 after time t2, the signal efd_en for enabling the field detector 4011 is switched from the low state to the high state, and then the field detector 4011 is activated. The field detector 4011 actively searches for a field.

At time t4 after time t3, the value of the counter 4011 reaches a limit value greater than the threshold value, and its reset signal assumes a pulse. The value of the counter 4011 is then set to zero.

If the value of the counter 4011 has reached the limit value, this means that during the period in which it is active, i.e. between time t3 and t4, the field detector 4011 does not detect a field which may lead to NFC communication.

At time t5 after time t4, signals en_bg, bg_rdy, and efd_en transition to a low state due to the peak present on signal rst_cnt. The reference voltage circuit, voltage regulator 4023, and NFC module 402 are no longer powered and/or enabled.

At time t6 after time t5, a new phase of activation of the field detector starts, and as at time t1, the signal en_bg transitions from the low state to the high state.

An advantage of this embodiment is that when the field detector is not enabled, the power supply circuit 402 does not consume power because it is not enabled itself.

Fig. 5B includes a timing diagram of the following signals: the state of the field RF field that can be detected by the field detector 4011 and that may cause NFC communication; a clock signal Clk; a signal en_bg for enabling the reference voltage circuit 4021; a state signal bg_rdy of the reference voltage circuit 4021; signal efd_en for enabling field detector 4011; an internal signal freq_check of state machine 4012; and information signal fsminfo of state machine 4012.

At an initial time t10, all signals of fig. 5B are in a low state, e.g., the voltage level is equal to a reference voltage, e.g., voltage v_ref or another voltage. The clock signal Clk has regular rising and falling edges. Further, the Field detector 4011 detects no Field RF Field (RF Field).

At time t11, which is subsequent to time t10, a field RF field that may cause near field communication is close to the device and may be detected by field detector 4011.

At time t12 after time t11, and as at time t1 described previously, the enable signal en_bg transitions from the low state to the high state. In other words, the counter 4032 starts the start of the reference voltage circuit 4021. In parallel, the counter 4032 indicates to the power supply circuit 402 that it requests its activation, for example by enabling signal alim_en, which also switches from a low state to a high state.

At time t13 after time t12, the state signal bg_rdy transitions from the low state to the high state. Thus, the reference voltage circuit 4021 indicates that its start phase has ended, and that it is ready to be used.

By switching to a high state, the signal bg_rdy allows the voltage regulator 4023 to be enabled via the enable signal ldo_en.

At time t14 after time t13, the signal efd_en for enabling the field detector 4011 transitions from the low state to the high state, and then the field detector 4011 is activated. The field detector 4011 actively searches for a field.

Since the field RF field may be detected by the field detector 4011, the latter detects it and determines the frequency of the field RF field. As previously described, and for this purpose, the field detector 4011 extracts the frequency of the field RF field and transmits a clock signal f_efd having a frequency equal to the frequency of the field RF field. The state machine 4012 then estimates the frequency by comparing the frequency of the signal f_efd to a reference clock signal (e.g., signal Clk). The reference clock signal has a frequency of the order of 64kHz, for example.

To perform this comparison, the state machine 4012 may count the number of cycles of the signal f_efd, for example, during a period of the reference clock signal. According to an example, if the reference clock signal is a clock signal Clk and it has a frequency on the order of 64kHz, the state machine validation signal f_efd has 192 to 235 cycles during the period of the signal Clk. Thus, the state machine verifies whether the field frequency is close enough to the reference frequency, typically 13.56MHz, with a margin of error of 10%.

At time t15, which follows time t14, the internal signal freq_check of state machine 4012 transitions from a low state to a high state and thus indicates that the frequency received from field detector 4011 via signal f_efd is sufficiently close to the reference frequency, i.e., in the order of magnitude of the reference frequency with an error margin of the order of 10%. In other words, the state machine confirms the fact that the field RF field may cause near field communication.

At time t16 after time t15, information signal fsm_info transitions from the low state to the high state. According to an example, the information signal FSM INFO may enable the main power supply circuitry of the device, such as regulator 404. According to another example, the information signal FSM INFO may thus indicate that the device should be ready for NFC communication, and if the device is in a "sleep" mode, it should switch to an adapted power consumption mode, such as a "full power" or "low power" mode.

Various embodiments and modifications have been described. Those skilled in the art will appreciate that certain features of the various embodiments and variations may be combined and that other variations will occur to those skilled in the art.

Finally, based on the functional indications given above, the practical implementation of the described embodiments and variations is within the ability of a person skilled in the art.

Claims (17)

1. An electronic device, comprising:

a power supply circuit configured to supply a power supply voltage; and

a near field communication module having a power input coupled to receive the power supply voltage from the power supply circuit;

wherein the near field communication module is configurable to operate in a low power mode; and is also provided with

Wherein when in the low power mode, the power supply circuit is configured to periodically provide the power supply voltage to the near field communication module.

2. The device of claim 1, further comprising a control circuit coupled to the power supply circuit, and wherein the control circuit is configured to periodically activate the power supply circuit when the near field communication module is in the low power mode.

3. The apparatus of claim 2, wherein the control circuit comprises a counter.

4. The device of claim 3, wherein the counter is activated when the near field communication module enters the low power mode, and wherein the power supply circuit is activated by the control circuit when a value of the counter reaches a threshold.

5. The device of claim 4, wherein when the near field communication module is in the low power mode and when the value of the counter reaches a limit value that is greater than the threshold, the power supply circuit is stopped by the control circuit and the value of the counter is reset.

6. The apparatus of claim 2, wherein the control circuit further comprises a reference voltage generation circuit.

7. The apparatus of claim 6, wherein the reference voltage generation circuit is a bandgap circuit.

8. The apparatus of claim 1, wherein the near field communication module comprises a field detector.

9. The device of claim 8, wherein the field detector of the near field communication module is activated when the near field communication module is in the low power mode, and wherein the power supply circuit is activated by the control circuit.

10. The device of claim 8, wherein the near field communication module further comprises a comparison circuit configured to compare a frequency of an electric field detected by the field detector to a reference frequency.

11. The apparatus of claim 10, wherein the comparison circuit is a state machine.

12. The device of claim 10, wherein an alarm signal is generated when the near field communication module is in the low power mode and when the comparison circuit determines that the frequency of the field detected by the field detector is substantially equal to the reference frequency.

13. The apparatus of claim 12, wherein substantially equal is satisfied if within an error tolerance on the order of 10%.

14. The device of claim 12, further comprising circuitry to power a processor configured to receive the alert signal.

15. The device of claim 14, wherein the circuit for powering comprises a voltage regulator configured to regulate an internal supply voltage and communicate the supply voltage to the near field communication module.

16. The apparatus of claim 1, wherein the power supply circuit comprises a reference voltage generation circuit.

17. The apparatus of claim 16, wherein the reference voltage generation circuit is a bandgap circuit.