CN117353405A - Electronic device power supply - Google Patents

Abstract

The present disclosure relates to electronic device powering. According to one embodiment, a circuit for managing power of an electronic module includes: a first state machine configured to receive a first command to disable the module and verify that the first command remains the same for a first minimum period of time; and a second state machine configured to cut power to the first portion of the module when the second state machine receives a second command from the first state machine indicating that the first command remains the same for the first minimum period of time. The first portion of the module is configured to be powered from the battery via a first supply voltage.

Description

Electronic device power supply

Cross Reference to Related Applications

This application claims the priority benefit of french patent application No.2206729 filed at 2022, 7, 4, which is incorporated herein by reference to the maximum extent allowed by law.

Technical Field

The present disclosure relates generally to electronic systems and devices, and power supplies for such systems and devices.

Background

The most sophisticated electronic devices such as computers, smart phones and tablet computers currently have a variety of functions that can be implemented by different modules and circuits included in these devices.

As new functions increase, the power management of these circuits and modules becomes more and more complex.

It is desirable to be able to at least partially improve certain aspects of known electronic devices, and more particularly to improve their power management.

Disclosure of Invention

One embodiment provides a circuit for managing power of an electronic module, the circuit comprising:

-a first state machine configurable to receive a first command for disabling the module, and the first state machine may be configured to verify that the first command remains the same for a first minimum period of time; and

a second state machine configured to power off at least a first portion of the module when the second state machine receives a second command from the first state machine, the second command indicating that the first command has remained the same for a first minimum period of time,

the at least a first portion of the module is powered by a first supply voltage from a battery.

Another embodiment provides a method of powering an electronic module including circuitry for managing power to the electronic module, the method comprising:

-a first state machine configurable to receive a first command for disabling the module and configured to verify that the first command remains the same for a first minimum period of time; and

a second state machine configured to power off at least a first portion of the module when the second state machine receives a second command from the first state machine, the second command indicating that the first command has remained the same for a first minimum period of time,

the at least a first portion of the module is powered with a first supply voltage from a battery.

According to an embodiment, the first disable command corresponds to a first state of a first signal for the control module.

According to an embodiment, the first control signal is obtained from the second signal for controlling the module and from a third signal indicative of a state of the second supply voltage of the module.

According to an embodiment, when the first control signal switches to the first state, the first state machine is configured to count the time the first signal remains in the first state.

According to an embodiment, upon receiving the second command, the second state machine is configured to electrically isolate the first portion of the module from other circuitry.

According to an embodiment, upon receiving the second command, the second state machine is configured to operate the power supply of at least a second portion of the module different from the first portion.

According to an embodiment, the first state machine is configured to pass the second command regardless of the operational state of the first module.

According to an embodiment, the management circuit further comprises a wake-up circuit configured to activate the module upon receipt of the third activation command.

According to an embodiment, the third start command is generated when the first signal for the control module switches to a second state different from the first state.

Another embodiment provides an electronic module comprising the aforementioned power management circuit.

According to one embodiment, the electronic module is a secure element.

According to an embodiment, the electronic module is configured to enable near field communication.

Another embodiment provides an electronic device comprising a battery and the aforementioned electronic module.

Drawings

The foregoing and other features and advantages will be described in detail in the remainder of the disclosure of the specific embodiments presented by way of illustration and not limitation with reference to the accompanying drawings wherein:

fig. 1 very schematically shows an example of an electronic device in the form of a block;

fig. 2 very schematically shows, in block form, different states of a circuit or a module of the device of fig. 1;

fig. 3 very schematically shows an embodiment of an electronic device in block form;

FIG. 4 very schematically illustrates in block form an embodiment of a power management circuit included in the embodiment of FIG. 3;

FIG. 5 shows a block diagram illustrating the operation of the device of FIG. 3;

FIG. 6 shows a timing diagram illustrating the operation of the apparatus of FIG. 3; and

fig. 7 shows other timing diagrams illustrating the operation of the device of fig. 3.

Detailed Description

Like features are denoted by like reference numerals throughout the various figures. In particular, structural and/or functional features common in the various embodiments may have the same reference numerals and may be provided with the same structural, dimensional and material characteristics.

For clarity, only the steps and elements useful for understanding the embodiments described herein are shown and described in detail. In particular, the details of the circuitry of the embodiments described below are not fully described and are within the ability of those skilled in the art.

Unless otherwise indicated, when referring to two elements being connected together, this means that there is no direct connection of any intermediate element other than a conductor, and when referring to two elements being connected together, this means that the two elements may be connected or they may be coupled via one or more other elements.

In the following disclosure, when referring to absolute positional qualifiers, such as the terms "front", "rear", "top", "bottom", "left", "right", etc., or relative positional qualifiers, such as the terms "upper", "lower", etc., or orientation qualifiers, such as "horizontal", "vertical", etc., reference is made to the orientation of the drawings unless otherwise indicated.

Unless otherwise indicated, the expressions "about", "substantially" and "on the order of …" mean within 10%, preferably within 5%.

Some embodiments relate to electronic devices that reliably manage their power supply, for example, to consume less energy.

Fig. 1 very schematically shows an example of an electronic device 100 in the form of a block.

The electronic device 100 comprises a processor 101 (CPU) adapted to implement different types of processing of data stored in memory and/or transferred by other circuits and/or modules of the device 100.

The electronic device 100 also includes different types of memory 102 (MEM), such as ROM, volatile memory, and/or nonvolatile memory. Each memory is adapted to store a different type of data.

The electronic device 100 further comprises a power supply circuit 103 (PS). The circuit 103 manages the power supply of the different circuits and modules of the device 100. The circuit 103 comprises, for example, a battery charging device, a voltage adaptation circuit, e.g. a voltage regulator, etc.

The electronic device 100 may further comprise a circuit 104 (NFC) adapted to enable near field communication, or a near field communication module 104, or an NFC module 104. The NFC module 104 includes, for example, an oscillation/resonance circuit, a data transmission and reception circuit, a data conversion circuit, a power supply control circuit, and the like.

The electronic device 100 also includes circuitry or modules 105 (FCT) adapted to implement the different functions of the device 105. The circuit 35 is variable and may include measurement circuitry, data analysis circuitry, sensors, and the like. According to an example, the circuit or module 105 may comprise a secure element adapted to manage critical data or secret data.

The electronic device 100 also includes input and output circuitry 106 (I/O) of the device 100. The circuit 106 includes, for example, a connector, a display device, etc., that enables the device 100 to transmit and receive data.

The electronic device 100 also includes one or more communication buses 107 adapted to couple together two or more circuits or modules of the device 100. A single bus 107 is shown in fig. 1. Bus(s) 100 may enable data and/or command signals and energy to be transferred between two or more circuits or modules of device 100.

Fig. 2 very schematically shows in block form a module 200 of the device 100 described in connection with fig. 1 and its different modes of operation.

Module 200 may be a different module or circuit of device 100. According to one example, module 200 is an NFC module of the type of module 104 described in connection with fig. 1. According to another example, the module 200 is one of the circuits 105 described with respect to fig. 1. According to one example, the module 200 is one of the circuits 106 described with respect to fig. 1.

The module 200 has a plurality of modes of operation, each having a different power mode.

The first mode of operation of the module 200 is an active mode 201 (ACT) or a full power mode in which the module 200 is powered to enable all of its functions, in other words, all of the circuits and components of the module 200 may be powered to operate. During this mode of operation, the power consumption of module 200 may be greatest.

The second mode of operation of the module 200 is a low power consumption mode 202 (low P), wherein the module 200 is powered only to implement a small number of functions, thereby saving energy. In other words, during this mode of operation, all circuits and components of the module cannot be powered at the same time. According to another example, during this mode, the clock frequency of the processor(s) of module 200 is reduced. According to one example, module 200 may include a plurality of different low power modes that enable different functions of module 200.

The third mode of operation of the module 200 is a very low power consumption mode 203 (HIB) or sleep mode, wherein the module 200 is only powered to implement a very small number of functions. The extremely low power consumption mode 203 is a variation of the low power consumption mode 202. During this mode, module 200 reduces its power consumption as much as possible by implementing only a very small number of functions. According to one example, during this mode of operation, the module only implements a function that enables it to "wake up", i.e. only implements a function that enables it to switch to another mode of operation. According to another example, during this mode of operation, the module implements only the functionality that enables it to "wake up" and the functionality that consumes little energy.

The fourth mode of operation of module 200 is a disable mode 204 (DIS) or a disable mode, wherein module 200 is powered only to implement a very small number of functions, all of its primary functions are disabled compared to the very low power consumption mode, and none of its functions are enabled except for the function that enables it to "wake up". In practice, during the disabled mode 204, the module 200 is disconnected from its energy source, such as the battery of the device 100. According to a variant, this functionality may be maintained during the disabled mode if the module 200 is used as an intermediary for powering other circuits or modules.

Fig. 3 very schematically shows in block form an embodiment of an electronic device 300 of the type of device 100 described in connection with fig. 1, including an embodiment of an electronic module 301 (MOD 1) of the type of module 200 described in connection with fig. 2.

Only a portion of the apparatus 300 is shown in fig. 3. The part comprises:

-a module 301;

-a power supply circuit 302;

-a processor 303;

-two electronic modules 304 (MOD 2) and 305 (MOD 5); an electrical isolation circuit 306 (ISO).

The power supply circuit 302 includes a battery 3021 (BAT) and a control circuit 3022 (CMD). The power supply module delivers the power supply voltage to the different modules of the device 300 via the control circuit 3022 or directly from the battery. More specifically, battery 3021 directly delivers supply voltage VBAT, and control circuitry 3022 delivers at least one input/output supply voltage VIO via a supply rail. The voltage VIO is a supply voltage whose state depends on the operating state of the device 300. According to one example, when device 300 is off, voltage VIO is in a low state.

As previously described, module 301 is of the type of module 200 described in connection with fig. 2. According to an embodiment, the module 301 is adapted to implement at least one function, for example two functions in the case of fig. 3. Further, according to an embodiment, module 301 receives supply voltage VBAT directly from battery 3021 of power circuit 302 without using control circuit 3022 as an intermediary. The module 301 also receives an input/output supply voltage VIO via a supply rail. Thus, module 301 comprises:

-a first circuit 3011 (FCT 1) implementing a first function;

-a second circuit 3012 (FCT 2) implementing a second function; and

power management circuitry 3013 (PSMANAG).

According to an embodiment, the first function is the primary function of the module 301, and is not powered when the module 301 is in a disabled mode of the type of mode 204 described with respect to fig. 2. The first circuit 3011 receives the supply voltage vbat_fct1 and the control signal fct1_en from the circuit 3013.

Furthermore, according to one example, the first functionality is adapted to exchange data and/or energy with one or more modules of the device 300 (e.g., module 305 in fig. 3). When module 301 is in the disabled mode, module 301, and in particular circuit 3011, is electrically isolated from module 305 by isolation circuitry 306. Thus, when the module 301 is in the disabled mode, the first function is not powered and the isolation circuit 306 is activated.

According to one example, the second function is an auxiliary function of the module 301, and is still powered when the module 301 is in a disabled mode of the type of mode 204 described with respect to fig. 2. The second circuit 3012 receives the supply voltage vbat_fct2 and the control signal fct2_en from the circuit 3013. According to an embodiment, the second function may enable powering of one or more other modules or circuits of the device 300 with energy. In fig. 3, the second functionality exchanges data and/or energy with module 304.

According to one embodiment, the power management circuit 3013 directly receives the supply voltage VBAT from the battery 3021 of the power circuit 302 and the voltage VIO from the control circuit 3022 of the power circuit 302. The circuit 3013 also receives a signal mod1_en for the control module 301 from, for example, the processor 303. The control signal mod1_en is a signal for enabling the module 301 and more specifically enabling the disabling of the module 301. In other words, when the enable signal is in a first state (e.g., a high state), the module 301 is activated and in a low power consumption mode or in an extremely low power consumption mode (e.g., modes 201, 202, or 203 described with respect to fig. 2), and when the enable signal is in a second state (e.g., a low state), the module 301 enters a disabled mode of the type described with respect to fig. 2, regardless of the mode of operation in which the module 301 was previously in. The circuit 3013 thus enables management of the power supplies of the different functionalities of the module 301 according to the state of the control signal mod1_en.

And, the communication bus that transmits the control signal mod1_en is supplied with the power supply voltage VIO. If the supply voltage VIO is no longer able to supply the control signal mod1_en, for example if the supply voltage VIO is in a low state, the control signal mod1_en is also in a low state. The power management circuit 3013 may include one or more circuits that enable distinguishing between a low state of the signal mod1_en from a command or a low state from the power supply voltage VIO. Such a circuit is described in connection with fig. 4.

Examples of embodiments of the circuit 3013 and their operation are described in detail in fig. 4-7.

Fig. 4 very schematically shows in block form a circuit 400 of the type of circuit 3013 described in connection with fig. 3, and a circuit 450 (FCT) of the type of circuit 3011 described in connection with fig. 3.

As described in connection with fig. 3, circuit 400 is a circuit for managing power to an electronic module of an electronic device. The electronic module receives a supply voltage VBAT provided by a battery and an input/output supply voltage VIO provided by a control circuit of the power supply circuit. The voltages VBAT and VIO are the same as those described in connection with fig. 3. Furthermore, the electronic module is adapted to receive the control signal mod1_en described in relation to fig. 3. In the example of fig. 4, the control signal mod1_en includes two states, in which:

-a high state indicating that the module comprising the circuit 400 is in an active mode, a low power mode or an ultra low power mode; and

a low state, indicating that the module comprising the circuit 400 is in a disabled state, or that the supply voltage VIO cannot supply the communication bus carrying the voltage mod1_en.

Those skilled in the art will be able to adapt the circuit 400 with a control signal mod1_en comprising the following two states:

-a low state indicating that the module comprising the circuit 400 is in an active mode, a low power mode or an ultra low power mode; and

a high state, indicating that the module comprising circuit 400 is in a disabled state, or that the supply voltage VIO cannot supply the communication bus carrying voltage mod1_en.

The circuit 400 includes a connection rail 401 (I/O PS) that receives the supply voltage VIO and the control signal mod1_en. Connection rail 401 is powered by a supply voltage VIO delivered by a supply rail of a power supply circuit of an electronic device that includes modules including circuit 400.

The circuit 400 further comprises a voltage detector circuit 402 (VOLT DETECT) adapted to DETECT the presence or absence of the supply voltage VIO. For this purpose, the circuit 402 receives the supply voltage VIO and outputs an information signal vio_en indicating the presence or high enough of the supply voltage VIO via a first state to power the connection track 401, and to power the module comprising the circuit 400, and indicating the absence or not high enough of the supply voltage VIO via a second state to power the connection track 401.

The circuit 400 further comprises a circuit 403 (mod1_en_clamp) adapted to verify the state of the control signal mod1_en according to the state of the signal vio_en. To this end, the circuit 403 receives the signals mod1_en and vio_en, and outputs an information signal mod1_en_clamp. The information signal mod1_en_clamp includes a high state indicating that a module including the circuit 400 receives the power supply voltage VIO and is in an active mode, a low power mode, or an ultra-low power mode. The information signal mod1_en_clamp also includes a low state indicating that the module is in a disabled mode and/or does not receive the supply voltage VIO. The circuit 403 may also enable determination of whether the signal mod1_en is in a low state due to the supply voltage VIO being in a low state, or whether the signal mod1_en is in a low state due to a command being sent from the processor.

The circuit 400 also includes a first state machine 404 (fsm1_mod1_en) that receives the information signal mod1_en_clamp and outputs the request signal dis_req. The role of state machine 404 is to verify that the request from the processor to switch the module to the disabled state has a sufficiently long duration. In other words, state machine 404 verifies that signal mod1_en_clamp remains in the low state for a sufficient time after it switches to the low state, i.e., at least for a minimum period of time. To this end, at each falling edge of the signal mod1_en_clamp, the state machine 404 starts a counter. If the value of the counter exceeds the threshold value in the case where the signal mod1_en_clamp does not exhibit a rising edge, i.e. in the case where the signal mod1_en does not exhibit a rising edge or in the case where the signal vio_en does not exhibit a falling edge, the module has to switch to the disabled mode. Conversely, if the signal mod1_en_clamp exhibits a rising edge, i.e. if one of the signals mod1_en and vio_en already exhibits a rising or falling edge before the value of the counter reaches the threshold value, the module must not switch to the disabled mode. An advantage of this state machine is that it can avoid a "false" command that causes the module to switch to disabled mode. The state machine provided signal dis_req indicates whether the module has to switch to disabled mode.

The circuit 400 further includes an edge detection circuit 405 (mod1_edge_detect), which edge detection circuit 405 receives the signal mod1_en_clamp and delivers an output alarm signal indicating a rising edge mod1_en_r and a falling edge mod1_en_f.

The circuit 400 also includes a wake-up circuit 406 (WUP) that receives the rising and falling edge alarm signals mod1_en_r and mod1_en_f and delivers as output a wake-up signal wup_req. The circuit 406 enables a wake-up command to be sent when the signal mod1_en_clamp exhibits a rising or falling edge.

The circuit 400 further includes a second state machine 407 that receives signals dis_req and wup_req and passes signal fct1_en. The state machine 407 is activated by a wake-up signal wup_req. The state machine 407 is used to start or stop the power supply of the module according to the command transmitted by the signal dis_req. The state machine 407 is also used to start or stop the electronic device isolation circuit(s).

Finally, the circuit 400 also includes a power supply circuit 408 (INT PWR SUPP) adapted to transmit the battery supply voltage VBAT to the circuit 450 when the state machine 407 requires the battery supply voltage VBAT, or to stop supplying power at the supply voltage VBAT. To this end, the circuit 408 passes the voltage VBAT and the signal fct1_en and outputs the signal vbat_fct1. The circuit 400 may comprise, for example, a regulator capable of adapting the amplitude of the voltage VBAT.

The circuit 450 may include a reset circuit 451 that receives the signal mod1_en_clamp.

Fig. 5 shows a block diagram illustrating the operation of the circuit 400 described in connection with fig. 4. More specifically, fig. 5 illustrates the operation of the circuit 400 when the module comprising the circuit 400 switches from an active mode, from a low power mode, or from an ultra low power mode to a disabled mode. Fig. 5 also illustrates the operation of the circuit 400 when the module switches from the disabled mode to the active mode, the low power mode, or the very low power mode.

It should be noted that in fig. 5, the power supply voltage VIO is maintained in a high state. The case where the power supply voltage VIO is switched to the low state is described with respect to fig. 6 and 7.

In an initial step 501 (first state), the module is in an active mode, a low power mode or an ultra low power mode, i.e. a mode in which at least a part of the circuitry and/or functions of the module are powered. The control signal mod1_en is in a high state.

At step 502 (mod1_enf), the control signal mod1_en presents a falling edge and thus switches from a high state to a low state. In other words, the processor or circuit that passes the control signal mod1_en indicates that the module must switch to the disabled state. It is assumed that voltage VIO is present.

At step 503 (wup+rst+start COUNTER), circuit 403 passes the signal mod1_en_clamp exhibiting the falling edge to circuit 405, state machine 404, and to circuit 451 for reset circuit 450.

The circuit 405 detects this falling edge and informs its circuit 406 via a signal mod1_en_f. Circuitry 406 then sends a wake-up request to state machine fsm2_power via signal wup_req. According to an example, circuitry 406 may also send the wake-up request to other circuitry of the device that includes the module.

State machine 404 receives signal mod1_en_clamp and starts a counter when a falling edge occurs. As long as the signal mod1_en_clamp does not exhibit a falling edge, the value C of the counter increases.

The reset circuit 451 receives the signal mod1_en_clamp, and according to one example, resets the function realized by the circuit 450.

At step 504 (C > CMAX), if the signal mod1_en_clamp exhibits a rising edge before the value C exceeds the threshold CMAX (output N), i.e., the signal mod1_en exhibits a rising edge or if the signal vio_en exhibits a falling edge, the next step is step 505 (WUP- > ACT). In contrast, if the value C of the counter of state machine 404 exceeds the threshold value CMAX and the signal MOD1_EN_CLAMP does not exhibit a rising edge, i.e., the signal MOD1_EN does not exhibit a rising edge, or the signal VIO_EN does not exhibit a falling edge (output Y), then the next step is step 506 (ISO).

In step 505, the signal mod1_en_clamp is not held in a low state for a long enough time to consider a command for switching to a disabled mode. The circuit 405 detects the rising edge of the signal mod1_en_clamp and informs the circuit 406 via the signal mod1_en_r, and the circuit 406 is then responsible for waking up the useful circuits of the module.

In step 506, the signal mod1_en_clamp has been in the low state for a long enough time to consider a command for switching to the disabled mode. State machine 404 sends a request to state machine 407 via signal dis_req to set to disabled mode.

At step 507 (DIS), state machine 407 receives the request and turns off power to circuit 450. To this end, state machine 407 generates and sends a signal fct1_en to circuit 408. According to one example, the state machine 407 is adapted to pass a signal of the type fct1_en for each function implemented by the module. If the function of the second function type of circuit 3012 must remain powered during the disabled mode, state machine 407 requests it from circuit 408.

At step 550 (mod1_en_r), the module remains in the disabled state for a longer period of time and receives a command to switch to the active mode, the low power mode, or the very low power mode. In other words, the signal mod1_en has remained in a certain state for a while, and a rising edge is presented at step 550. Still assume that voltage VIO still exists.

In step 551 (WUP- > ACT), the module has entered an active state. Due to the presence of the voltage VIO, the signal mod1_en_clamp also presents a rising edge that is detected by the circuit 405. The wake-up circuit 406 receives this information and then wakes up the state machine 407 and all circuits for the module to start up.

Fig. 6 and 7 include 6 timing diagrams (a), (B), (C), (D), (E), and (F) that illustrate more precise examples of the operation of the modules comprising circuit 400, and in particular illustrate the different hardware and software steps implemented during the transition from active mode to inactive mode.

It is contemplated that the module includes different states, wherein:

an active state ACT corresponding to an active mode of the module, or a low power mode of the module, or an extremely low power mode;

-a hardware start state hw_b during which the module starts its circuits and components;

-a software start state sw_b during which the module starts the software it implements;

-a reset state RST during which the module is restarted;

-a disable state DIS corresponding to a disable mode of the module.

Each of the timing charts (a), (B), (C), (D), (E), and (F) includes a graph representing a temporal change of the input/output power supply voltage VIO, a graph representing a temporal change of the signal mod1_en or the voltage mod1_en, and an axis showing different states of the module during the changes of the voltages VIO and mod1_en.

The timing diagram (a) shows a case where a disable request, that is, a request to switch to the disable mode is sent to the module. Further, the timing chart (a) shows a case where the disable request is long enough to be considered.

At an initial time tA0, the module is in the active state ACT, and both voltages VIO and mod1_en are in a high state.

At time tA1, which is subsequent to time tA0, signal mod1_en exhibits a falling edge and switches to a low state. The voltage VIO remains in a high state. As previously described, the circuit 451 of the circuit 450 for resetting the module is activated and resets the function of the circuit 450. The module is then in the reset state RST. During this state RST, state machine 404 starts its counter. In the case of timing diagram (a), the value C of the counter exceeds the threshold CMAX, and thus the module switches to the disabled state DIS.

At time tA2, which is subsequent to time tA1, voltage VIO exhibits a falling edge and switches to a low state. The signal mod1_en remains in a low state. The module is still in disabled mode.

At time tA3, which is subsequent to time tA2, voltage VIO exhibits a rising edge and switches to a high state. The signal mod1_en remains in a low state. The module switches from the disabled state DIS to the hardware enabled state hw_b. At the end of state hw_b, the circuitry of the module, in particular the state machine 404, is started and it is detected that the signal mod1_en is still in a low state. The state machine 404 then starts its counter and the module toggles the reset bit state RST. The value C of the counter exceeds the threshold CMAX again, so the module switches to the disabled state DIS.

At time tA4 after time tA3, signal mod1_en exhibits a rising edge and switches to a high state. The voltage VIO remains in a high state. The module switches to the hardware start state hw_b, then to the software start state and finally to the active state.

The timing diagram (B) shows the case where a disable request, i.e., a request to switch to the disable mode, is sent to the module. Further, the timing chart (B) shows a case where the disable request is not long enough to be considered.

At an initial time tB0, the module is in the active state ACT, and both voltages VIO and mod1_en are in the high state.

At time tB1 after time tB0, the signal mod1_en exhibits a falling edge and switches to a low state. The voltage VIO remains in a high state. As previously described, the module is then in the reset state RST. During this state RST, state machine 404 starts its counter. In the case of the timing chart (B), the value C of the counter does not reach the threshold CMAX.

At time tB2 after time tB1, the voltage VIO exhibits a falling edge and switches to a low state. The signal mod1_en remains in a low state. Then, the module switches to a software start-up state, and then switches to a state of the OS to be defined when its software has been started up. Here, the software of the module and the software of the device comprising the module define what may happen.

At time tB3 after time tB2, voltage VIO exhibits a rising edge and switches to a high state. The signal mod1_en remains in a low state. The module switches from the disabled state DIS to the hardware enabled state hw_b. At the end of state hw_b, the circuitry of the module is started, in particular state machine 404 is started and signal mod1_en is detected as still being in a low state. The state machine 404 then starts its counter and the module toggles the reset bit state RST. The value C of the counter does not reach the threshold CMAX.

At time tB4 after time tB3, the signal mod1_en exhibits a rising edge and switches to a high state. The voltage VIO remains in a high state. The module switches to the software start state sw_b and then to the active state.

The timing diagram (C) shows a variation of the case of the timing diagram (a) in which a disable request, i.e., a request to switch to a disabled state, is sent to the module since the power rail delivering the power supply voltage VIO is turned off. Further, the timing chart (C) shows a case where the disable request is long enough to be considered.

At an initial time tC0, the module is in an active state ACT, and both voltages VIO and mod1_en are in a high state.

At time tC1 after state tC0, signal mod1_en exhibits a falling edge and switches to a low state. The voltage VIO remains in a high state. As previously described, the module is then in the reset state RST. During this state RST, state machine 404 starts its counter. In the case of timing diagram (C), the value C of the counter exceeds the threshold CMAX, and thus the module switches to the disabled state DIS.

At time tC2 after state tC1, voltage VIO exhibits a falling edge and switches to a low state. The signal mod1_en remains in a low state. As detected by circuit 403, signal mod1_en is in a low state because the supply voltage is in a low state, rather than because the processor requires the module to switch to a disabled state. Thus, the circuit 403 concludes that the circuit 450 must be restarted. Thus, the module switches to the hardware boot state hw_b, then to the software boot state sw_b, and finally to a software state to be defined as OS, for example, a low power consumption mode or an extremely low power consumption mode.

At time tC3 after state tC2, voltage VIO exhibits a rising edge and switches to a high state. The signal mod1_en remains in a low state. The circuitry of the module is enabled and state machine 404 detects that signal mod1_en is still in a low state. The state machine 404 then starts its counter and the module toggles the reset bit state RST. The value C of the counter exceeds, for example, the threshold CMAX, so the module switches to the disabled state DIS.

At time tC4 after state tC3, signal mod1_en exhibits a rising edge and switches to a high state. The voltage VIO remains in a high state. The module switches to the hardware start-up state hw_b, then to the software start-up state and finally to the active state.

The timing diagram (D) shows a variation of the case of the timing diagram (B) in which a disable request, i.e., a request to switch to a disabled state, is sent to the module since the power rail delivering the power supply voltage VIO is turned off. Further, the timing chart (D) shows a case where the disable request is not long enough to be considered.

At an initial time tD0, the module is in the active state ACT, and both voltages VIO and mod1_en are in the high state.

At time tD1 after time tD0, signal mod1_en exhibits a falling edge and switches to a low state. The voltage VIO remains in a high state. As previously described, the module is then in the reset state RST. During this state RST, state machine 404 starts its counter. In the case of the timing chart (D), the value C of the counter does not reach the value CMAX.

At time tD2 after time tD1, voltage VIO exhibits a falling edge and switches to a low state. The signal mod1_en remains in a low state. Then, the module switches to a software start-up state, and then switches to a state of the OS to be defined when its software has been started up.

At time tD3 after state tD2, voltage VIO exhibits a rising edge and switches to a high state. The signal mod1_en remains in a low state. The module switches from the disabled state DIS to the hardware enabled state hw_b. At the end of state hw_b, the circuitry of the module is started, in particular state machine 404 is started and signal mod1_en is detected as still being in a low state. The state machine 404 then starts its counter and the module toggles the reset bit state RST. The value C of the counter does not reach the threshold CMAX.

At time tD4 after time tD3, signal mod1_en exhibits a rising edge and switches to a high state. The voltage VIO remains in a high state. The module switches to the software start state sw_b and then to the active state.

The timing diagram (E) shows the start-up sequence of the modules, i.e. the start-up of the power supply VIO, and then switching from the disabled state to the active state.

At an initial time tE0, the voltage VI0 and the signal mod1_en are in a low state. The module is in the disabled state DIS.

At time tE1 after time tE0, voltage VIO exhibits a rising edge and switches to a high state. The signal mod1_en remains in a low state. The module switches to the hardware start state hw_b. At the end of state hw_b, the circuitry of the module is started, in particular state machine 404 is started and signal mod1_en is detected as still being in a low state. The state machine 404 then starts its counter and the module toggles the reset bit state RST. The value C of the counter does not reach the threshold CMAX and the module switches to the disabled state DIS.

At time tE2 after time tE1, signal mod1_en exhibits a rising edge and switches to a high state. The voltage VIO remains in a high state. The module may start up and then switch to the hardware start-up state hw_b, then to the software start-up state and finally to the active state.

The timing diagram (F) shows a module reset sequence, i.e., switching from active state ACT to inactive state DIS and then to active state ACT.

At an initial time tF0, the voltage VI0 and the signal mod1_en are in a high state. The module is in active state ACT.

At time tF1 after state tF0, signal mod1_en exhibits a falling edge and switches to a low state. The voltage VIO remains in a high state. The circuit 451 of the circuit 450 for the reset module activates and resets the function of the circuit 450 as previously described in connection with fig. 4 and 5. The module is then in the reset state RST. During this state RST, state machine 404 starts its counter. In the case of timing diagram (F), the value C of the counter exceeds the threshold CMAX, so the module switches to the disabled state DIS.

At time tF2 after time tF1, signal mod1_en exhibits a rising edge and switches to a high state. The voltage VIO remains in a high state. The module may start up and then switch to the hardware start-up state hw_b, then to the software start-up state sw_b, and finally to the active state ACT.

Various embodiments and modifications have been described. Those skilled in the art will appreciate that certain features of these various embodiments and variations may be combined and that other variations will occur to those skilled in the art.

Finally, based on the functional indications given above, the practical implementation of the described embodiments and variants is within the reach of a person skilled in the art.

Claims (20)

1. A circuit for managing power of an electronic module, the circuit comprising:

a first state machine configured to receive a first command to disable the module and configured to verify that the first command remains the same for a first minimum period of time; and

a second state machine configured to shut off the power to a first portion of the module when the second state machine receives a second command from the first state machine, the second command indicating that the first command has remained the same for the first minimum period of time, wherein the first portion of the module is configured to be powered from a battery via a first power supply voltage.

2. The circuit of claim 1, wherein the first disable command corresponds to a first state of a first signal for controlling the module.

3. The circuit of claim 2, wherein the first signal is configured to be obtained from a second signal for controlling the module and from a third signal indicative of a state of a second supply voltage of the module.

4. The circuit of claim 2, wherein when the first signal switches to the first state, the first state machine is configured to measure a time that the first signal remains in the first state.

5. The circuit of claim 1, wherein the second state machine is configured to electrically isolate the first portion of the module from other circuits of the module upon receipt of the second command.

6. The circuit of claim 1, wherein the second state machine is configured to allow the power source to provide power to a second portion of the module different from the first portion upon receipt of the second command.

7. The circuit of claim 1, wherein the first state machine is configured to provide the second command regardless of an operational state of the module.

8. The circuit of claim 1, wherein the circuit further comprises a wake-up circuit configured to activate the module upon receipt of an activation command.

9. The circuit of claim 8, wherein:

wherein the first disable command corresponds to a first state of a first signal for controlling the module; and

the circuit is configured to generate the start command when the first signal of the module switches to a second state different from the first state.

10. A method of powering an electronic module, the electronic module including circuitry for managing power to the electronic module, the method comprising:

powering a first portion of the module from a first supply voltage of a battery;

receiving, by a first state machine, a first command to disable the module;

verifying, by the first state machine, that the first command remains the same for a first minimum period of time;

receiving, by a second state machine, a second command from the first state machine, the second command indicating that the first command has remained the same for the first minimum period of time; and

in response to receiving the second command, the power supply to the first portion of the module is cut off by the second state machine.

11. The method of claim 10, wherein the first disable command corresponds to a first state of a first signal for controlling the module.

12. The method of claim 11, further comprising obtaining the first signal from a second signal for controlling the module and from a third signal indicative of a state of a second supply voltage of the module.

13. The method of claim 11, further comprising counting, by the first state machine, a time that the first signal remains in the first state when the first signal switches to the first state.

14. The method of claim 10, further comprising electrically isolating, by the second state machine, the first portion of the module from other circuitry of the module upon receipt of the second command.

15. The method of claim 10, further comprising: upon receiving the second command, the power supply is allowed by the second state machine to provide power to a second portion of the module different from the first portion.

16. The method according to claim 10, wherein:

the first disable command corresponds to a first state of a first signal for controlling the module; and is also provided with

The method further comprises the steps of:

generating a start command when the first signal of the module switches to a second state different from the first state; and

a wake-up circuit is used to start the module upon receipt of the start-up command.

17. An electronic module, comprising:

a first circuit portion including an electronic circuit; and

a power management circuit comprising:

a first state machine configured to receive a first command to disable the module and configured to verify that the first command remains the same for a first minimum period of time, an

A second state machine configured to cut off power to the first circuit portion when the second state machine receives a second command from the first state machine, the second command indicating that the first command has remained the same for the first minimum period of time, the first circuit portion being powered by a first power supply voltage from a battery.

18. The module of claim 17, wherein the first circuit portion comprises a secure element.

19. The module of claim 18, further comprising a second circuit portion different from the first circuit portion, wherein the second circuit portion comprises near field communication circuitry.

20. The module of claim 17, further comprising the battery.