JP2983726B2 - Substrate voltage generation circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a substrate voltage generating circuit for applying a negative voltage to a substrate so that a semiconductor element on the substrate operates stably.

[0002]

2. Description of the Related Art Recently, semiconductor devices in which various elements are formed on a semiconductor substrate have been increasingly used. The voltage applied to the substrate in the semiconductor device is important for determining various characteristics of the entire semiconductor device. For example, it affects the threshold value and other transistor characteristics of the N-channel MOS transistor on the substrate. Also, dynamic
In a random access memory, the data retention time of a memory cell on a substrate is greatly affected.

First, a conventional substrate voltage generating circuit for applying a negative voltage to a semiconductor substrate will be described with reference to FIGS.

FIG. 12 is a circuit diagram showing a conventional example of a substrate voltage generating circuit. In the figure, VCC is the power supply voltage, VSS
Is a ground voltage, VBB is a substrate voltage, Qp101 to Qp224 are P-channel MOS transistors, Qn101 to Qn212 are N-channel MOS transistors, N101 to N222 are node names,
BBE is a control signal, and C221 and C222 are capacitors.

This substrate voltage generating circuit is formed on the same substrate as various semiconductor elements whose operation is to be guaranteed. The substrate voltage generating circuit is roughly divided into two parts, a substrate voltage detecting unit 10 and a substrate voltage generating unit 20. Consisting of parts. The substrate voltage detection unit 10 includes a first voltage detection circuit 11 that sets -3V as a detection set voltage, and a second voltage detection circuit 12 that sets -2V as a detection set voltage. The substrate voltage generation section 20 includes an oscillation circuit 21 and a voltage generation circuit 22.

FIG. 14 is a waveform diagram of the substrate voltage VBB and the signal of each node of the conventional substrate voltage generating circuit having the above configuration. The operation of the conventional substrate voltage generation circuit will be described with reference to FIG. However, when the substrate voltage VBB becomes deeper (lower) than -3V, the output voltage of the output node N111 becomes the logic voltage "L". When the negative substrate voltage VBB becomes shallower (higher) than -3V, the first voltage detection circuit 11 outputs. Node N
111 becomes the logic voltage “H”. Similarly, in the second voltage detection circuit 12, when the substrate voltage VBB becomes deeper (lower) than -2V, the output node N121 becomes the logic voltage "L", and when the negative substrate voltage VBB becomes shallower (higher) than -2V. The output node N121 is at the logic voltage "H".

Now, as shown in FIG. 14, the substrate voltage VBB
Even if the voltage drops from 0V equal to the ground voltage VSS, the substrate voltage detector 10 outputs the output nodes N111 and N111 of the first and second voltage detecting circuits 11 and 12 for a period (period) which is shallower (higher) than -2V. N121 is a logic voltage "H", and the output node N111 of the first voltage detection circuit 11 is a P-channel MOS transistor Qp101 connected to the gate.
Is off, an N-channel MOS transistor Q having an output node N121 of the second voltage detection circuit 12 connected to the gate.
n101 is turned on. Therefore, the node N101 at the connection point between the two MOS transistors Qp101 and Qn101 is at the logic voltage "L", and the output node N102 of the substrate voltage detector 10 is at the logic voltage "H". Next, when the substrate voltage VBB further falls and falls within the range of -2 V to -3 V (period), the output node N121 of the second voltage detection circuit 12 changes from the logic voltage "H" to the logic voltage "L". The N-channel MOS transistor Qn101 whose output node N121 is connected to the gate is turned off, but the output node N102 of the substrate voltage detector 10 is turned off.
Holds the logic voltage “H”. Further, when the substrate voltage VBB falls and becomes deeper (lower) than -3 V (period), the output node N111 of the first voltage detection circuit 11 becomes the logic voltage "H".
To the logic voltage "L", and the output node N111 is connected to the gate of the P-channel MOS transistor Qp101.
Is turned on, so that the P-channel MOS transistor Q
The node N101 at the connection point between the p101 and the N-channel MOS transistor Qn101 which has already been turned off has the logic voltage "H", and the output node N102 of the substrate voltage detector 10 has the logic voltage "L".

Next, the substrate voltage VBB starts to rise and becomes -3 V
The output node N of the first voltage detection circuit 11 during a period (period) that is deeper (lower) than -2 V even if it becomes shallower (higher).
111 changes from the logic voltage "L" to the logic voltage "H", and the output node N111 is connected to the gate of the P-channel type MO.
The S transistor Qp101 turns off, but the output node N102 of the substrate voltage detector 10 holds the logic voltage "L". Finally, when the substrate voltage VBB further rises and becomes shallower (higher) than -2 V (period), the second voltage detecting circuit 12
The output node N121 changes from the logic voltage "L" to the logic voltage "H", the N-channel MOS transistor Qn101 whose output node N121 is connected to the gate turns on, and the N-channel MOS transistor Qn101 has already turned off. The node N101 at the connection point with the P-channel type MOS transistor Qp101 has the logic voltage "L", and the output node N102 of the substrate voltage detector 10 returns to the logic voltage "H".

As described above, the substrate voltage detecting section 10 changes the logic voltage of the output node N102 with hysteresis in accordance with the change in the voltage of the substrate.

On the other hand, the oscillation circuit 2 in the substrate voltage generator 20
1 operates when the control signal BBE is at the logic voltage "H" and outputs a pulse signal of a constant frequency from the output node N211. The control signal BBE is always kept at the logic voltage “H” during the operation of the semiconductor device to which the present substrate voltage generating circuit is applied. Output node N211 of oscillation circuit 21
Is connected to a first input node N221 of an input NAND gate of the voltage generation circuit 22, and an output node N102 of the substrate voltage detection unit 10 is connected to a second input node N222 of the input NAND gate. Thereby, the voltage generation circuit 2
2 outputs a negative voltage as a voltage to be applied to the substrate, that is, a substrate voltage VBB when the output node N102 of the substrate voltage detecting unit 10 is at the logical voltage "H", while the output node N102 is at the logical voltage "L". ", The output function of the substrate voltage is stopped.

FIG. 13 is a diagram showing the relationship between the power supply voltage VCC and the substrate voltage VBB showing the static characteristics of the above substrate voltage generating circuit. L1 in the figure is a relationship line between the positive power supply voltage VCC and the negative substrate voltage VBB when it is assumed that the voltage generation circuit 22 is always operating. As described above, the voltage generation circuit 22 actually outputs the output node N10 of the substrate voltage detection unit 10.
When the substrate voltage VBB changes in the direction of becoming deeper (lower) under the control by the logic voltage of 2, the operation stops when the voltage becomes deeper (lower) than -3 V, and the substrate voltage VBB becomes shallower (higher). When the voltage changes in a certain direction and the voltage becomes shallower (higher) than -2 V, it is restarted and the substrate voltage VBB is made deeper (lower). Therefore, the change of the actual substrate voltage VBB is limited as shown by the solid line and hatching in FIG. That is, when the power supply voltage VCC is in the range of 3.7 V or more, the actual substrate voltage VBB is from -2 V to -3 V
The voltage value is between

[0012]

In the above conventional substrate voltage generating circuit, the negative substrate voltage VBB is deeper (lower) than -3V.
In this case, the function of the voltage generation circuit 22 is stopped through the control by the substrate voltage detection unit 10, so that there is a problem in the following dynamic characteristics.

That is, if a large current suddenly flows through the substrate for some reason in a state where the function of the voltage generation circuit 22 is stopped, the restart of the voltage generation circuit 22 by the substrate voltage detection unit 10 cannot be completed in time. That is, the voltage of the substrate becomes too shallow (high). For example, if the substrate voltage VBB rises to near 0V, the substrate voltage generating circuit itself cannot operate, or even if it operates, the negative voltage applied to the substrate is too shallow (too high). The threshold value of the N-channel MOS transistor decreases, the substrate current consumed by the entire semiconductor device increases, and the voltage generation circuit 22 cannot supply such a substrate current. Therefore, the substrate voltage VBB cannot be deepened (lowered) again, and a normal stable operation of the entire semiconductor device cannot be guaranteed.

An object of the present invention is to improve the dynamic characteristics of a substrate voltage generation circuit so that the substrate voltage does not become too shallow (high) even when a large current suddenly flows through the substrate.

[0015]

In order to achieve the above object, the present invention provides a plurality of voltage generating circuits for outputting negative voltages different from each other, and the plurality of voltage generating circuits are provided in accordance with a voltage change of a substrate. In which one of the voltage generating circuits is operated.

More specifically, the invention of claim 1 is
As shown in FIG. 1 or FIG. 7, a substrate voltage for outputting a negative voltage as a voltage VBB to be applied to the substrate in order to apply a negative voltage to the substrate so that the semiconductor element on the substrate operates stably. In a substrate voltage generation circuit including a generation unit 20 and a substrate voltage detection unit 10 for controlling the operation of the substrate voltage generation unit 20 according to a change in the voltage of the substrate, the substrate voltage generation unit 20 is the same. Are different from each other with respect to the positive power supply voltage VCC (for example, a straight line L in FIG. 2).
1 and L2, and a plurality of voltage generating circuits 22 and 23 for outputting the substrate voltage VBB). The substrate voltage detecting section 10 generates the plurality of voltage generating circuits according to a change in the voltage of the substrate. The circuit has a function of selecting one of the circuits 22 and 23 and outputting a negative voltage as the voltage VBB to be applied to the substrate to the selected voltage generating circuit.

In the second aspect of the present invention, as shown in FIGS. 1 to 3, in the first aspect of the present invention, the substrate voltage generator 20 is provided with a negative voltage (for example, represented by a straight line L1 in FIG. 2). A first voltage generating circuit 22 for outputting the substrate voltage VBB and a negative voltage which is shallower with respect to the same positive power supply voltage VCC than the negative voltage output by the first voltage generating circuit 22 (for example, in FIG. And a second voltage generating circuit 23 for outputting a substrate voltage VBB represented by a straight line L2 of the following formula. 3V), and a second negative setting voltage shallower than the first negative setting voltage of the first voltage detecting circuit 11 for detecting whether or not the negative voltage becomes deeper than 3V). (For example, -2 V), the voltage of the substrate becomes a shallower negative voltage. The second to detect whether
And the voltage detection circuit 12 of FIG. In addition, the first voltage detection circuit 11 detects that when the negative voltage of the substrate changes in the direction to become deeper, the voltage becomes deeper than the first negative set voltage. In this case, the function of the first voltage generation circuit 22 is stopped, and the second voltage generation circuit 23 outputs a negative voltage as the voltage VBB to be applied to the substrate. Further, the second voltage detection circuit 12 detects that when the negative voltage of the substrate changes to a shallower direction, the voltage has become a shallower negative voltage than the second negative set voltage. In this case, the function of stopping the function of the second voltage generating circuit 23 and outputting the negative voltage as the voltage VBB to be applied to the substrate to the first voltage generating circuit 22 is provided. is there.

According to a third aspect of the present invention, as shown in FIG. 4, in the second aspect of the present invention, the first voltage generating circuit 22 outputs a substrate voltage VBB represented by, for example, a straight line L1. Then, the second voltage generating circuit 23 outputs a negative voltage corresponding to the first negative set voltage (for example, −3 V) of the first voltage detecting circuit 11 by the first voltage generating circuit 22. The second voltage detection circuit 12 is connected to the same positive power supply voltage as the positive power supply voltage VCC (for example, 3.7 V) at the time.
Has a function of outputting a negative voltage (for example, a substrate voltage VBB represented by a straight line L2) deeper than the second negative set voltage (for example, -2 V).

According to a fourth aspect of the present invention, in the first aspect of the present invention, as shown in FIGS. 5 and 6, each of the plurality of voltage generating circuits 22 and 23 includes This configuration employs a configuration further including an oscillation circuit 21 that outputs a variable frequency pulse signal for changing the current driving capability. In addition, the oscillation circuit 21 uses the substrate voltage detection unit 10 to generate the plurality of voltage generation circuits 22 and 2.
When a voltage generating circuit (for example, the second voltage generating circuit 23) for outputting a shallow negative voltage among the three voltage generating circuits 3 is selected, the pulse is increased so as to increase the current driving capability of the selected voltage generating circuit 23. When another voltage generating circuit (for example, the first voltage generating circuit 22) for increasing the frequency of the signal and outputting a negative voltage deeper than the voltage generating circuit 23 is selected, the selected voltage generating circuit is selected. It has a function of lowering the frequency of the pulse signal so as to reduce the current driving capability of the other voltage generating circuit 22.

According to a fifth aspect of the present invention, as shown in FIGS. 7 to 9, in the second aspect of the present invention, the substrate voltage generator 20 includes a negative voltage output from the second voltage generator 23. For example, the substrate voltage VBB represented by the straight line L2 in FIG. 8)
And a third voltage generating circuit 24 for outputting a shallow negative voltage (for example, a substrate voltage VBB represented by a straight line L3 in FIG. 8) for the same positive power supply voltage VCC. Is a negative voltage which is deeper than a third negative set voltage (for example, -3.5 V) in which the voltage of the substrate is deeper than a first negative set voltage (for example, -3 V) of the first voltage detection circuit 11. The third embodiment employs a configuration further including third voltage detection circuits 13 for detecting whether or not the voltage has become zero. Moreover, the third voltage detection circuit 13 detects that the voltage has become deeper than the third negative set voltage when the negative voltage of the substrate changes in a direction to become deeper. In this case, the function of the second voltage generation circuit 23 is stopped, a negative voltage as the voltage VBB to be applied to the substrate is output to the third voltage generation circuit 24, and the negative voltage of the substrate is When it is detected that the voltage has become shallower than the third negative set voltage when the voltage changes to a shallower direction, the third voltage generating circuit 2
Voltage VBB to stop the function of No. 4 and to apply to the substrate
And a function of outputting the negative voltage to the second voltage generation circuit 23.

According to a sixth aspect of the present invention, in the first aspect of the present invention, the substrate voltage detecting section 10 is provided with the configuration shown in FIGS.
As shown in FIG. 1, when a specific control signal LT is supplied, a specific voltage generating circuit (for example, FIG. The substrate voltage V represented by the straight line L1 in FIG.
The first voltage generation circuit 22) that outputs BB is selected, and a function of outputting a negative voltage as the voltage VBB to be applied to the substrate to the selected voltage generation circuit 22 is adopted.

[0022]

According to the first aspect of the present invention, any one of the plurality of voltage generating circuits 22 and 23 is selected by the substrate voltage detecting section 10 in accordance with the voltage change of the substrate, and the selected voltage generating circuit is selected. The circuit outputs a negative voltage as a voltage VBB to be applied to the substrate.
One of 2, 23 is always operating. Therefore, even when a large current suddenly flows through the substrate for some reason, the voltage of the substrate becomes too shallow (high) because the voltage generating circuit operating at that time responds to the change in the substrate current. Nothing.

According to the second aspect of the present invention, when the negative voltage of the substrate changes in a direction to become deeper, the voltage becomes deeper than the first negative set voltage (eg, -3 V). When the first voltage detection circuit 11 detects that the voltage has become low, a deep negative voltage (for example, the substrate voltage V represented by a straight line L1 in FIG. 2) is detected.
BB) is stopped, and at the same time, the second voltage for outputting a shallow negative voltage (eg, a substrate voltage VBB represented by a straight line L2 in FIG. 2) is stopped. The generation circuit 23 is activated. Conversely, when the negative voltage of the substrate changes in a direction to become shallower, the second voltage detection circuit 12 determines that the voltage has become shallower than the second negative set voltage (for example, -2 V). Upon detection, the function of the operating second voltage generating circuit 23 is stopped, and at the same time, the first voltage generating circuit 22 for outputting a deep negative voltage is activated. That is, since one of the first and second voltage generating circuits 22 and 23 always operates, the substrate voltage VBB rises (rises) even when a large current suddenly flows through the substrate for some reason. Not only is suppressed, but also the voltage of the substrate can always be kept between the first negative set voltage and the second negative set voltage.

Further, according to the third aspect of the present invention, the first voltage generating circuit 22 supplies the first negative set voltage (eg, -3 V).
For a positive power supply voltage higher than the positive power supply voltage VCC (for example, 3.7 V) when outputting a negative voltage corresponding to the above, both the output voltages of the first and second voltage generation circuits 22 and 23 are set to the second voltage. (Eg, -2 V), the effect of suppressing the floating (rising) of the substrate voltage is increased.

According to the fourth aspect of the present invention, in the oscillation circuit, a voltage generation circuit (for example, the second voltage generation circuit) for outputting a shallow negative voltage is selected by the substrate voltage detection unit. In this case, the current driving capability of the selected voltage generating circuit 23 is increased by increasing the frequency of the output pulse signal. Thereby, the effect of suppressing the rise (rise) of the substrate voltage is increased. On the other hand, when another voltage generating circuit for outputting a deep negative voltage (for example, the first voltage generating circuit 22) is selected, the frequency of the output pulse signal is lowered to thereby select the other selected voltage generating circuit. The current driving capability of the voltage generation circuit 22 is reduced. Thereby, useless power consumption is suppressed.

According to the fifth aspect of the present invention, the third voltage detecting circuit 13 includes a third negative setting voltage (for example, -3 V) whose substrate voltage is deeper than the first negative setting voltage (for example, -3 V). -3.5 V), and it is always checked whether the voltage becomes deeper than that of the third negative set voltage. If the substrate voltage becomes deeper than the third negative set voltage, the voltage to be operated is generated. The circuit is switched from the second voltage generating circuit 23 to the third voltage generating circuit 24. Conversely, when the voltage of the substrate becomes a negative voltage which is shallower than the third negative set voltage, a voltage to be operated is generated. The circuit is switched from the third voltage generation circuit 24 to the second voltage generation circuit 23. That is, two voltage detection circuits 1
1 and 12 and two voltage generating circuits 22 and 23 compared to the case of the invention of claim 2,
2, 23, 24, ie, the substrate voltage VBB is
The three voltage detection circuits 11, 12, and 13 are finely controlled. In addition, since one of these three voltage generating circuits 22, 23, 24 always operates, even if a large current suddenly flows through the substrate for some reason, any of the operating voltage generating circuits Reduces the voltage of the substrate in response to the change in the substrate current. Therefore, the voltage of the substrate does not become too shallow (high).

According to the sixth aspect of the present invention, when a specific control signal LT is supplied to the substrate voltage detecting section 10, a plurality of voltage generating circuits 2 are provided regardless of the magnitude of the substrate voltage.
A specific voltage generating circuit (e.g., a first voltage generating circuit 22 that outputs a deep (low) substrate voltage VBB represented by a straight line L1 in FIG. 11) is selected from among the voltage generating circuits 2 and 23, and the selected voltage generating circuit is selected. The circuit 22 outputs a negative voltage as the voltage VBB to be applied to the substrate. This makes it possible to perform a reliability acceleration test of the semiconductor device.

[0028]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in more detail with reference to the illustrated embodiments.

First, a substrate voltage generating circuit according to a first embodiment of the present invention will be described with reference to FIGS.

FIG. 1 is a circuit diagram showing a substrate voltage generating circuit according to a first embodiment of the present invention. In the figure, VCC is the power supply voltage, VSS is the ground voltage, VBB is the substrate voltage, Qp101 to Qp
p236 is a P-channel MOS transistor, Qn101 to Qn2
12 is an N channel type MOS transistor, N101 to N232
Is a node name, BBE is a control signal, and C221 to C232 are capacities.

The substrate voltage generation circuit is roughly divided into two parts, a substrate voltage detection unit 10 and a substrate voltage generation unit 20. Among them, the substrate voltage detection unit 10 includes a first voltage detection circuit 11 that sets -3V as a set voltage for detection, and a -2V
And a second voltage detection circuit 12 for setting the two output nodes N having opposite logic voltages to each other.
102 and N103. On the other hand, the substrate voltage generator 20
An oscillating circuit 21, a first voltage generating circuit 22 for outputting a deep negative voltage, and a shallow negative voltage for the same power supply voltage VCC as compared to the negative voltage output from the first voltage generating circuit 22. And a second voltage generating circuit 23 for outputting. The output node N211 of the oscillation circuit 21 is connected to the first
The first input node N221 of the input NAND gate of the voltage generation circuit 22 and the input NAND of the second voltage generation circuit 23
The first output node N102 of the substrate voltage detecting unit 10 is connected to the second input node N222 of the input NAND gate of the first voltage generating circuit 22 and is connected to the first input node N231 of the substrate. The second output node N103 of the voltage detector 10 is connected to the second input node N232 of the input NAND gate of the second voltage generator 23.

FIG. 3 shows a first embodiment of the present invention having the above configuration.
FIG. 8 is a waveform diagram of a substrate voltage VBB of the substrate voltage generation circuit of the embodiment and signals at respective nodes. 14 is different from the waveform diagram of FIG. 14 described above only in that a signal having a logic voltage in a phase opposite to that of the signal at the first output node N102 is output from the second output node N103 in the substrate voltage detecting unit 10. Therefore, a detailed description of the operations of the first and second voltage detection circuits 11 and 12 will be omitted.

On the other hand, the oscillation circuit 2 in the substrate voltage generator 20
1 is that the control signal BBE is always held at the logic voltage "H" during the operation of the semiconductor device, so that a pulse signal of a constant frequency is supplied to both the first and second voltage generating circuits 22 and 23 through the output node N211. give. Moreover, in this embodiment,
When the first voltage detection circuit 11 detects that the voltage has become deeper (lower) than −3 V when the negative voltage of the substrate changes in the direction of becoming deeper (lower), the substrate voltage detector 1
0, the first output node N102 is at the logic voltage "L" (the second output node N103 is at the logic voltage "H").
At the same time as the function of the voltage generating circuit 22 is stopped, the second voltage generating circuit 23 starts outputting a shallow negative voltage as the voltage VBB to be applied to the substrate. On the other hand, when the second voltage detection circuit 12 detects that the voltage has become shallower (higher) than −2 V when the negative voltage of the substrate changes in the direction of becoming shallower (higher). Is that when the first output node N102 of the substrate voltage detector 10 is at the logic voltage "H" (the second output node N103 is at the logic voltage "L"), the function of the second voltage generation circuit 23 stops. At the same time, the first voltage generation circuit 22 starts outputting a deep negative voltage as the voltage VBB to be applied to the substrate.

FIG. 2 is a diagram showing the relationship between the power supply voltage VCC and the substrate voltage VBB showing the static characteristics of the substrate voltage generating circuit of this embodiment. In the figure, L1 is a relational line between the power supply voltage VCC and the substrate voltage VBB assuming that the first voltage generation circuit 22 is always operating, and L2 is the second voltage generation circuit 23.
Power supply voltage VCC assuming that
5 is a relational line between the voltage and the substrate voltage VBB. As described above, in practice, when the negative voltage of the substrate changes in the direction of becoming deeper (lower), if the voltage becomes deeper (lower) than -3V, the substrate voltage V
The voltage generating circuit for generating BB is switched from the first voltage generating circuit 22 to the second voltage generating circuit 23, and when the negative voltage of the substrate changes in a direction to become shallow (high), the voltage becomes -2V. When the voltage becomes shallower (higher), the voltage generating circuit that generates the substrate voltage VBB is switched from the second voltage generating circuit 23 to the first voltage generating circuit 22, so that the actual substrate voltage VBB is indicated by a solid line and hatching in FIG. As shown, when the change is limited and the power supply voltage VCC is in the range of 3.7 V or more and 5.0 V or less, the substrate voltage VBB takes a voltage value between -2 V and -3 V.

Moreover, according to the first embodiment, one of the first and second voltage generating circuits 22 and 23 always operates, so that the substrate is suddenly mounted for some reason. Even when a large current flows, the rise (rise) of the voltage of the substrate is suppressed.

Next, a substrate voltage generating circuit according to a second embodiment of the present invention will be described with reference to FIG.

In the second embodiment, the negative output voltage of the second voltage generating circuit 23 is made deeper (lower) in the substrate voltage generating circuit shown in the same circuit diagram as that of FIG. . FIG. 4 is a relationship diagram between the power supply voltage VCC and the substrate voltage VBB showing the static characteristics of the substrate voltage generation circuit of the present embodiment. In the figure, L1 is a relational line between the power supply voltage VCC and the substrate voltage VBB assuming that the first voltage generation circuit 22 is always operating, and L2 is the second voltage generation circuit 23.
Power supply voltage VCC assuming that
And the substrate voltage VBB. The second voltage generating circuit 23 of the present embodiment is different from the first voltage generating circuit 22 in that the straight line L
1 above, the set voltage of the first voltage detection circuit 11 is −3 V
The power supply voltage VCC (3.7) when outputting a negative voltage corresponding to
For the same power supply voltage as V), a setting is made such that a negative voltage deeper than the set voltage -2 V of the second voltage detection circuit 12 is output on the straight line L2.

According to the second embodiment having the above configuration, the output voltage of each of the first and second voltage generating circuits 22 and 23 is -2 in the range of the power supply voltage VCC of 3.7 V or more.
Since the negative voltage is deeper than V, the effect of suppressing the floating (rising) of the substrate voltage when a large current suddenly flows through the substrate is large.

Next, a substrate voltage generating circuit according to a third embodiment of the present invention will be described with reference to FIGS.

FIG. 5 is a circuit diagram showing only the oscillation circuit in the substrate voltage generation circuit according to the third embodiment of the present invention. In this embodiment, the oscillation circuit 21 in the substrate voltage generation unit 20 shown in FIG. FIG.
Is replaced by an oscillation circuit 21 shown in FIG. In FIG. 5, VCC is the power supply voltage, VSS is the ground voltage, and Qp511 to Qp5.
32 is a P-channel type MOS transistor, Qn511 to Qn532
Is an N-channel MOS transistor, N501 to N511 are node names, and BBE is a control signal. The output node N511 of the oscillation circuit 21 in the figure is connected to the first input node N221 of the input NAND gate of the first voltage generation circuit 22 and the second input node N221 in the same manner as the output node N211 of the oscillation circuit of FIG. It is commonly connected to a first input node N231 of the input NAND gate of the voltage generation circuit 23.

The oscillation circuit 21 of FIG. 5 operates while the control signal BBE is maintained at the logic voltage "H" during the operation of the semiconductor device to which the present substrate voltage generation circuit is applied, and operates at the output node N511.
Output a pulse signal. In addition, when the control node N502 is at the logic voltage "L", the inverted control node N503 is at the logic voltage "H", and the P-channel type M
Both the OS transistor Qp511 and the N-channel type MOS transistor Qn511 are turned on, and the P-channel type
Since both the S-transistor Qp521 and the N-channel MOS transistor Qn521 are turned off, an oscillating circuit corresponding to a circuit in which five stages of negative circuits are connected in a ring shape is obtained.
On the other hand, when the control node N502 is at the logic voltage "H", the inversion control node N503 is at the logic voltage "L", and both the upper P-channel MOS transistor Qp511 and the N-channel MOS transistor Qn511 are off, and the lower Since both the P-channel MOS transistor Qp521 and the N-channel MOS transistor Qn521 are turned on, an oscillation circuit corresponding to a circuit in which seven stages of NOT circuits are connected in a ring shape is obtained, and the oscillation frequency is reduced.

FIG. 6 shows the oscillation circuit 2 of FIG. 5 described above.
FIG. 6 is a waveform diagram of signals at one control node N502 and an output node N511 for outputting a pulse signal. As shown in the figure, when the control node N502 is at the logic voltage "H", a pulse signal having a lower frequency is output from the output node N511 as compared with the case where the logic voltage is at the "L" level.

The control node N502 of the oscillation circuit 21
Is the first output node N of the substrate voltage detection unit 10 in FIG.
Connected to 102. As a result, the logic voltage of the first output node N102 of the substrate voltage detection unit 10 is set to "L" (the logic voltage of the second output node N103 is "H") to output a shallow negative voltage. When operating the voltage generation circuit 23, the oscillation frequency of the oscillation circuit 21 is increased, and the current driving capability of the second voltage generation circuit 23 is increased. Thereby, the effect of suppressing the floating (rising) of substrate voltage VBB is increased. Conversely, the logic voltage at the first output node N102 of the substrate voltage detector 10 is set to "H" (the logic voltage at the second output node N103 is "L") to output a deep negative voltage. When the first voltage generation circuit 22 is operated, the oscillation frequency of the oscillation circuit 21 is lowered and the current driving capability of the first voltage generation circuit 22 is reduced, so that wasteful power consumption is suppressed. .

Next, a substrate voltage generating circuit according to a fourth embodiment of the present invention will be described with reference to FIGS.

FIG. 7 is a circuit diagram showing a substrate voltage generating circuit according to a fourth embodiment of the present invention. In this substrate voltage generation circuit, a third voltage detection circuit 13 that sets the detection voltage to −3.5 V is added to the substrate voltage detection unit 10 in the configuration of FIG. 1 described above (first embodiment). In addition, a third voltage generating circuit 24 for outputting a shallow negative voltage with respect to the same power supply voltage VCC as compared with the negative voltage output by the second voltage generating circuit 23 is added to the substrate voltage generating section 20. It is. In the substrate voltage detector 10 in FIG. 7, Qp131 is a P-channel MOS transistor, and Qn131 to Qn134 are N
Channel type MOS transistors, N104 to N106, N13
1 is the node name, which is newly introduced. Further, in the substrate voltage generator 20 in FIG.
Qp241 to Qp248 are P-channel MOS transistors, N
241 and N242 are node names, and C241 and C242 are capacitances, which are newly introduced for the third voltage generation circuit 24. The same reference numerals as those in FIG. 1 represent the same components.

In the substrate voltage generating circuit of the present embodiment, the output node N 211 of the oscillation circuit 21 is connected to the first NAND gate of each of the input NAND gates of the first to third voltage generating circuits 22, 23 and 24.
Are commonly connected to the input nodes N221, N231 and N241. Also, the signals of the first and second output nodes N102 and N103 of the substrate voltage detecting section 10 based on the outputs of the first and second voltage detecting circuits 11 and 12 are output from the third voltage detecting circuit 1
3 and the third to fifth output nodes N104 and N105 of the substrate voltage circuit 10.
, N106. Then, the substrate voltage detecting unit 1
0 is the third output node N104 of the first voltage generation circuit 22.
The second output node N105 of the substrate voltage detection unit 10 is connected to the second input node N222 of the input NAND gate of the input NAND gate, and the second input node N232 of the input NAND gate of the second voltage generation circuit 23 is connected to the second input node N232 of the input NAND gate. The fifth output node N106 of the detector 10 is connected to the second input node N242 of the input NAND gate of the third voltage generator 24.

FIG. 9 shows a fourth embodiment of the present invention having the above configuration.
FIG. 8 is a waveform diagram of a substrate voltage VBB of the substrate voltage generation circuit of the embodiment and signals at respective nodes. The operation of the substrate voltage generating circuit according to the present embodiment will be described with reference to FIG. However,
The third voltage detection circuit 13 detects that the substrate voltage VBB is -3.5 V
When the depth goes deeper (lower), the output node N131 becomes the logic voltage "L", and when the negative substrate voltage VBB becomes shallower (higher) than -3.5V, the output node N131 becomes the logic voltage "H".

As shown in FIG. 9, even when the substrate voltage VBB falls from 0 V, the substrate voltage detector 10 detects the first to third voltage detections (period) during a period (period) shallower (higher) than -2 V. The output nodes N111, N121,.
N131 is a logic voltage "H", and the output node N111 of the first voltage detection circuit 11 is connected to the gate of P1.
The channel type MOS transistor Qp101 is turned off, and the N-channel type MOS transistor Qn101 having the gate connected to the output node N121 of the second voltage detecting circuit 12 is turned on. Therefore, both MOS transistors Qp101, Qn101
Is the logic voltage "L", the first output node N102 of the substrate voltage detector 10 is the logic voltage "H", and the second output node N103 is the logic voltage "L". As a result, the logic voltages of the third to fifth output nodes N104, N105, N106 of the substrate voltage detector 10 are
They are "H", "L", and "L", respectively. next,
When the substrate voltage VBB further falls and falls within the range of -2 V to -3 V (period), the output node N121 of the second voltage detection circuit 12 changes from the logic voltage "H" to the logic voltage "L", and the output node N121. Is an N-channel type M connected to the gate
Although the OS transistor Qn101 turns off, the first and second output nodes N102 and N103 of the substrate voltage detector 10 hold the logic voltages "H" and "L", respectively. Third to fifth output nodes N104 and N105
, N106 hold logic voltages "H", "L", "L", respectively. Next, the substrate voltage VBB further decreases to -3V to-
In the range of 3.5 V (period-1), the output node N111 of the first voltage detection circuit 11 changes from the logic voltage "H" to the logic voltage "L", and the output node N111 is connected to the P-channel connected to the gate. Since the p-type MOS transistor Qp101 is turned on, the p-channel MOS transistor Qp101 and the n-channel MOS transistor Qn1 already turned off
The node N101 at the connection point with 01 becomes a logic voltage "H",
The first output node N102 of the substrate voltage detector 10 has a logic voltage "L", and the second output node N103 has a logic voltage "H". Therefore, the third to fifth output nodes N104, N105, N106 of the substrate voltage detector 10 are at the logic voltages "L", "H", "L", respectively. Further, when the substrate voltage VBB falls and becomes deeper (lower) than -3.5 V (period-
2) Since the output node N131 of the third voltage detection circuit 13 changes from the logic voltage "H" to the logic voltage "L", the third to fifth output nodes N104, N105,
The logic voltages of N106 are logic voltages "L", "L",
It becomes "H".

Next, the substrate voltage VBB starts to rise and -3.
In the range of 5 V to -3 V (period-3), the output node N131 of the third voltage detection circuit 13 changes from the logic voltage "L" to the logic voltage "H". The logic voltages of the fifth output nodes N104, N105 and N106 are "L", "H" and "L", respectively. Substrate voltage V
-2 even if BB rises further and becomes shallower (higher) than -3V
During the period (period) deeper (lower) than V, the output node N111 of the first voltage detection circuit 11 changes from the logic voltage "L" to the logic voltage "H", and the output node N111 is connected to the gate of the P-channel type. The MOS transistor Qp101 turns off, but the first to second output nodes N102 and N103 of the substrate voltage detector 10 hold the logic voltages "L" and "H", respectively. N104, N105, N
106 holds the logic voltages "L", "H" and "L", respectively. Finally, when the substrate voltage VBB further rises and becomes shallower (higher) than -2 V (period), the second voltage detecting circuit 12
The output node N121 changes from the logic voltage "L" to the logic voltage "H", the N-channel MOS transistor Qn101 whose output node N121 is connected to the gate turns on, and the N-channel MOS transistor Qn101 has already turned off. Since the node N101 at the connection point with the P-channel MOS transistor Qp101 attains the logic voltage "L", the first output node N102 of the substrate voltage detector 10 has the logic voltage "H", and the second output node N103 has the logic voltage "H". The logic voltage becomes “L”. Therefore, the logic voltages of the third to fifth output nodes N104, N105, N106 of the substrate voltage detector 10 return to "H", "L", and "L", respectively.

As described above, the substrate voltage detector 10 of this embodiment has the third to fifth output nodes N104, N105, N105 with a partial hysteresis in response to a change in the substrate voltage.
Change the logic voltage of 106.

On the other hand, the oscillation circuit 2 in the substrate voltage generation unit 20
1 is that the control signal BBE is always held at the logic voltage "H" during the operation of the semiconductor device, so that a pulse signal of a constant frequency is supplied to any of the first to third voltage generating circuits 22 to 24 through the output node N211. give. Moreover, in the present embodiment, when the negative voltage of the substrate changes in a direction to become deeper (lower), the voltage becomes deeper (lower) than -3V.
When the detection circuit 11 detects the
Since the third output node N104 of 0 changes to the logic voltage "L" and the fourth output node N105 changes to the logic voltage "H", the function of the first voltage generation circuit 22 stops and the second Starts outputting a shallow negative voltage as the voltage VBB to be applied to the substrate. When the third detection circuit 13 detects that the voltage has become deeper (lower) than -3.5 V when the negative voltage of the substrate changes in a direction to become deeper (lower), the substrate voltage is detected. Since the fourth output node N105 of the unit 10 changes to the logic voltage "L" and the fifth output node N106 changes to the logic voltage "H", the function of the second voltage generation circuit 23 stops, and Voltage V to be applied to the substrate by the voltage generation circuit 24 of No. 3
Start output of a shallower negative voltage as BB. On the other hand, when the third detection circuit 13 detects that the voltage has become shallower (higher) than -3.5 V when the negative voltage of the substrate changes in the direction of becoming shallower (higher). Means that the fifth output node N106 of the substrate voltage detecting unit 10 has the logic voltage "L"
At the same time, the fourth output node N105 changes to the logic voltage "H", so that the function of the third voltage generating circuit 24 is stopped, and at the same time, the voltage VBB to be applied to the substrate by the second voltage generating circuit 23 is applied. Start output of deep negative voltage. When the second detection circuit 12 detects that the voltage becomes shallower (higher) than -2 V when the negative voltage of the substrate changes in a direction to become further shallower (higher), the substrate voltage detector 10 At the same time as the fourth output node N105 changes to the logic voltage "L".
Therefore, the function of the second voltage generation circuit 23 is stopped, and at the same time, the output of the deeper negative voltage as the voltage VBB to be applied to the substrate by the first voltage generation circuit 22 is started.

FIG. 8 is a diagram showing the relationship between the power supply voltage VCC and the substrate voltage VBB showing the static characteristics of the substrate voltage generating circuit of this embodiment. In the figure, L1 is a relational line between the power supply voltage VCC and the substrate voltage VBB assuming that the first voltage generation circuit 22 is always operating, and L2 is the second voltage generation circuit 23.
Power supply voltage VCC assuming that
L3 is a relational line between the power supply voltage VCC and the substrate voltage VBB assuming that the third voltage generating circuit 24 is always operating. As described above, in practice, the voltage generating circuit that generates the substrate voltage VBB in accordance with the voltage of the substrate includes the first to third voltage generating circuits 22 and 2.
Since the switching is finely performed between 3 and 24, the change of the actual substrate voltage VBB is limited as shown by the solid line and hatching in FIG.

Moreover, according to the fourth embodiment, any one of the first to third voltage generating circuits 22, 23, and 24 always operates, so that the substrate may be mounted on the substrate for some reason. Even when a large current suddenly flows, the rise (rise) of the voltage of the substrate is suppressed.

Next, a substrate voltage generating circuit according to a fifth embodiment of the present invention will be described with reference to FIGS.

FIG. 10 is a circuit diagram showing only the substrate voltage detecting section in the substrate voltage generating circuit according to the fifth embodiment of the present invention. In this embodiment, the substrate voltage detecting section 10 shown in FIG. This is replaced with the substrate voltage detection unit 10 shown in FIG. FIG.
In the above, LT is a newly introduced special control signal, and when the control signal LT is applied, the first output node N102 of the substrate voltage detector 10 is unconditionally set to the logic voltage "H", The second output node N103 is unconditionally set to the logic voltage "L".

For example, a test mode signal for the reliability of the semiconductor device is given as a specific control signal LT for the substrate voltage detecting section 10. When the specific control signal LT becomes the logic voltage "H", the first voltage generating circuit 22 for outputting a deep negative voltage is unconditionally activated, and a large voltage is applied to elements such as transistors on the substrate. Becomes That is, severe conditions can be imposed as compared with the normal operation of the semiconductor device, which is effective as an acceleration test of the reliability of the semiconductor device.

[0057]

As described above, according to the first aspect of the present invention, a plurality of voltage generating circuits 22 and 23 for outputting mutually different negative voltages are provided, and the voltage generating circuits 22 and 23 are provided in accordance with a change in the voltage of the substrate. Since the configuration for operating any one of the plurality of voltage generating circuits 22 and 23 is employed, even if a large current suddenly flows through the substrate due to some cause, the operating voltage generating circuit is configured to operate the substrate current. In response to the change of the substrate voltage, the rise (rise) of the substrate voltage is suppressed. That is, the dynamic characteristics of the substrate voltage generation circuit are improved, and a great effect that a normal stable operation of the entire semiconductor device can be guaranteed can be obtained.

According to the second aspect of the present invention, two voltage generating circuits 22 and 23 having different output voltages are provided, and one of the two voltage generating circuits 22 and 23 has a different set voltage. Since the configuration in which the operation is performed under the control of the two voltage detection circuits 11 and 12 is employed, even when a large current suddenly flows through the substrate due to some cause, not only the floating of the substrate voltage is suppressed, but also the voltage of the substrate is reduced. Can always be kept within a predetermined range.

According to the third aspect of the present invention, the output voltage of the second voltage generating circuit 23 for outputting a shallow negative voltage of the first and second voltage generating circuits 22 and 23 is made very shallow. Since the configuration is employed, the effect of suppressing the floating of the substrate voltage is increased.

According to the fourth aspect of the present invention, in the oscillation circuit, a voltage generation circuit (for example, the second voltage generation circuit) for outputting a shallow negative voltage is selected by the substrate voltage detection unit. In this case, while increasing the frequency of the output pulse signal to increase the current driving capability of the selected voltage generating circuit 23, another voltage generating circuit for outputting a deep negative voltage (for example, the first voltage generating circuit 23). When the circuit 22) is selected, a configuration having a function of lowering the frequency of the output pulse signal to reduce the current driving capability of the selected other voltage generating circuit 22 is adopted.
When the voltage generation circuit 23 for outputting a shallow negative voltage is selected, the effect of suppressing the floating of the substrate voltage is increased, and another voltage generation circuit 22 for outputting a deep negative voltage is selected. In this case, power consumption is suppressed.

According to the fifth aspect of the present invention, three voltage generating circuits 22, 23 and 24 having different output voltages are provided.
Any one of the three voltage generating circuits 22 to 24 is connected to three voltage detecting circuits 11, 12, 1 having different set voltages.
Since the configuration of operating under the control of 3 is adopted, even if a large current suddenly flows through the substrate for some reason, the floating of the substrate voltage is suppressed, and the voltage of the substrate can always be kept within a predetermined range. In addition, there is an effect that the substrate voltage is finely controlled.

According to the sixth aspect of the present invention, when a specific control signal LT is applied, the specific voltage of the plurality of voltage generating circuits 22 and 23 is independent of the voltage level of the substrate. Since the configuration in which the substrate voltage detection unit 10 selects the generation circuit is adopted, the substrate voltage V is applied to the specific voltage generation circuit.
When a deep negative voltage is output as BB, there is an effect that a reliability acceleration test of the semiconductor device can be performed.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a substrate voltage generating circuit according to a first embodiment of the present invention.

FIG. 2 is a relationship diagram between a power supply voltage VCC and a substrate voltage VBB showing static characteristics of the substrate voltage generation circuit of FIG.

FIG. 3 is a waveform diagram of a substrate voltage VBB of the substrate voltage generation circuit of FIG. 1 and a signal of each node.

FIG. 4 is a diagram showing the relationship between the power supply voltage VCC and the substrate voltage VBB showing the static characteristics of the substrate voltage generation circuit according to the second embodiment of the present invention.

FIG. 5 is a circuit diagram of an oscillation circuit in a substrate voltage generation circuit according to a third embodiment of the present invention.

FIG. 6 is a waveform diagram of a signal at each node of the oscillation circuit of FIG. 5;

FIG. 7 is a circuit diagram of a substrate voltage generating circuit according to a fourth embodiment of the present invention.

8 is a diagram showing a relationship between a power supply voltage VCC and a substrate voltage VBB showing static characteristics of the substrate voltage generation circuit of FIG. 7;

FIG. 9 is a waveform diagram of a substrate voltage VBB of the substrate voltage generation circuit of FIG. 7 and a signal of each node.

FIG. 10 is a circuit diagram of a substrate voltage detection unit of a substrate voltage generation circuit according to a fifth embodiment of the present invention.

11 is a relationship diagram between a power supply voltage VCC and a substrate voltage VBB showing static characteristics of the substrate voltage generation circuit including the substrate voltage detection unit of FIG.

FIG. 12 is a circuit diagram showing a conventional example of a substrate voltage generation circuit.

FIG. 13 is a relationship diagram between a power supply voltage VCC and a substrate voltage VBB showing static characteristics of the substrate voltage generation circuit of FIG.

FIG. 14 is a waveform diagram of a substrate voltage VBB of the substrate voltage generation circuit of FIG. 12 and signals at respective nodes.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Substrate voltage detection part 11 1st voltage detection circuit 12 2nd voltage detection circuit 13 3rd voltage detection circuit 20 Substrate voltage generation part 21 Oscillation circuit 22 (1st) voltage generation circuit 23 2nd voltage generation circuit 24 Third voltage generating circuit VCC Power supply voltage VSS Ground voltage VBB Substrate voltage Qp101 to Qp532 P-channel type MOS transistor Qn101 to Qn532 N-channel type MOS transistor N101 to N511 Node name BBE, LT Control signal C221 to C242 Capacity L1 to L3 Power supply Relationship line between voltage and substrate voltage

Claims (6)

(57) [Claims] A substrate voltage generator for outputting a negative voltage as a voltage to be applied to the substrate so as to apply a negative voltage to the substrate so that a semiconductor element on the substrate operates stably; A substrate voltage detection circuit for controlling the operation of the substrate voltage generation unit in accordance with the change in the voltage of the substrate voltage generation unit, wherein the substrate voltage generation unit, with respect to the same positive power supply voltage A plurality of voltage generating circuits for outputting different negative voltages from each other, wherein the substrate voltage detecting unit includes one of the plurality of voltage generating circuits according to a change in the voltage of the substrate; And a function of outputting a negative voltage as a voltage to be applied to the substrate to the selected voltage generation circuit. 2. The substrate voltage generation circuit according to claim 1, wherein said substrate voltage generation section includes a first voltage generation circuit for outputting a negative voltage, and a negative voltage output by said first voltage generation circuit. A second voltage generating circuit for outputting a shallow negative voltage with respect to the same positive power supply voltage as compared to the substrate voltage detector, wherein the substrate voltage detection unit is configured such that the substrate voltage is reduced to a first negative set voltage. A first voltage detection circuit for detecting whether the voltage has become deeper than the first voltage detection circuit, and a second negative setting voltage shallower than a first negative setting voltage of the first voltage detection circuit. A second voltage detection circuit for detecting whether or not the voltage of the substrate has become a shallower negative voltage, wherein the first voltage detection circuit has changed in a direction in which the negative voltage of the substrate has increased. The voltage has become deeper than the first negative set voltage. Is detected, the function of the first voltage generation circuit is stopped, and a negative voltage as a voltage to be applied to the substrate is output to the second voltage generation circuit, and the second voltage detection circuit When the negative voltage of the substrate changes in a direction to become shallower, when it is detected that the voltage has become shallower than the second negative set voltage, the second voltage generation is performed. A substrate voltage generation circuit having a function of stopping a function of a circuit and outputting a negative voltage as a voltage to be applied to the substrate to the first voltage generation circuit. 3. The substrate voltage generating circuit according to claim 2, wherein said second voltage generating circuit is configured so that said first voltage generating circuit matches a first negative set voltage of said first voltage detecting circuit. And a function of outputting a negative voltage deeper than a second negative set voltage of the second voltage detection circuit with respect to the same positive power supply voltage when outputting a negative voltage. Substrate voltage generation circuit. 4. The substrate voltage generating circuit according to claim 1, wherein said substrate voltage generating unit outputs a pulse signal of a variable frequency for changing a current driving capability of each of said plurality of voltage generating circuits. A voltage generating circuit for outputting a shallow negative voltage among the plurality of voltage generating circuits by the substrate voltage detecting unit. The frequency of the pulse signal is increased so as to increase the current driving capability of the generation circuit, and when another voltage generation circuit for outputting a deep negative voltage compared to the voltage generation circuit is selected, the selection is made. A substrate voltage generating circuit having a function of lowering the frequency of the pulse signal so as to reduce the current driving capability of another voltage generating circuit. 5. The substrate voltage generating circuit according to claim 2, wherein said substrate voltage generating section outputs a shallow negative voltage with respect to the same positive power supply voltage as compared with a negative voltage output by said second voltage generating circuit. A third voltage generating circuit for performing the operation, wherein the substrate voltage detecting unit is configured to perform the third voltage generating circuit more than a third negative setting voltage in which the voltage of the substrate is deeper than a first negative setting voltage of the first voltage detecting circuit. Third to detect if deep negative voltage
Each of the voltage detection circuits further includes a third voltage detection circuit, wherein the third voltage detection circuit is configured such that when the negative voltage of the substrate changes in a direction to become deeper, the voltage becomes deeper than the third negative set voltage. When it is detected that the voltage has been reached, the function of the second voltage generation circuit is stopped, and a negative voltage as a voltage to be applied to the substrate is output to the third voltage generation circuit, and When it is detected that the negative voltage has become shallower than the third negative set voltage when the negative voltage changes in a direction to become shallower,
A substrate voltage generation circuit having a function of stopping a function of the third voltage generation circuit and outputting a negative voltage as a voltage to be applied to the substrate to the second voltage generation circuit. 6. The substrate voltage generating circuit according to claim 1, wherein said substrate voltage detecting section is configured such that, when a specific control signal is given, said plurality of voltages are applied irrespective of the magnitude of said substrate voltage. A substrate voltage generating circuit having a function of selecting a specific voltage generating circuit among the generating circuits and outputting a negative voltage as a voltage to be applied to the substrate to the selected voltage generating circuit.