JP2982909B2 - Analog / digital converter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to analog / digital (hereinafter, referred to as A / D)
The present invention relates to an A / D converter, and more particularly, to an A / D converter which is high-speed and high-accuracy and can reduce the area when integrated.

[Conventional technology]

A / D converter related to the present invention, James
G. Peterson, "Monolithic Video A / D Converter," IEE Journal of Solid State Circuits, SC Vol. 14, No. 6, 932-93
7, December 1979 (James G. Peterson, “A Monolithic Vi
deo A / D Convertor, "IEEE J. Solid-State Circuits, Vo
l. SC-14, No. 6, pp. 932-937, Dec. 1979).

FIG. 10 shows the configuration of the parallel A / D converter discussed above. This is because two voltage sources V _RT , V _RB (<
V _RT) between the resistor array 7 of the reference voltage generator connected between the voltage comparator 8 provided in parallel a plurality of comparing the magnitude of the reference voltage V _R and the input signal v _i generated as the divided voltage When,
Encoder 2 that outputs a digital value from the comparison result
It is composed of

[Problems to be solved by the invention]

Since the configuration of FIG. 10 according to the prior art is a method of comparing the magnitude of one reference voltage and one input signal, it is easy for various noises to be mixed into the reference voltage or the input signal and cause a comparison error. There was a problem.

As a means to solve this problem, as an example configuration in FIG. 11, the two reference voltages V _r h, the difference between _{V rl ΔV r (= V rh} -V rl)
And the difference Δv _i (= v _ih −V _il ) between the two input signals v _ih and v _il corresponding to the input signal v _i by the fully differential type voltage comparator 1, which is strong against noise and highly accurate. It is known that a simple A / D converter is realized.

However, when the configuration shown in FIG. 11 is adopted, the wiring is complicated because each reference voltage generated from the resistor string is branched into two and input to each voltage comparator as shown in the figure. Therefore, there is a problem that the area is increased when the integrated circuit is formed.

SUMMARY OF THE INVENTION An object of the present invention is to solve the problem in the case of using the above-described fully-differential type voltage comparator in the related art, and to provide an A / D converter which does not cause an increase in area when integrated circuits are provided. Is to do.

[Means for solving the problem]

In order to achieve the above object, according to claim 1 of the present invention, a first resistor string formed by connecting a plurality of resistors in series is connected between two voltage sources having different voltage values, and the same number of resistors are connected. Are connected in series between another two voltage sources, and are arranged in parallel with the first resistor row so that the direction of the voltage drop is opposite to that of the first resistor row. Means for creating a first input voltage that increases in proportion to the difference between the analog input voltage and the fixed reference voltage, a second input voltage that decreases in proportion to the first input voltage, and a first resistor string. The difference between the first reference voltage and the second reference voltage is defined as one of the compressed voltages as a first reference voltage, and one of the voltages divided by the second resistor string as a second reference voltage. , The first input voltage and the second
And a means for obtaining a digital value from an output of the voltage comparator.

According to claim 2, the low-voltage side terminal of the first resistor string and the second
Are electrically connected to the high-voltage side terminals of the resistor string, the voltage source connected to these terminals is removed, the high-voltage side terminal of the first resistor row is connected to the first voltage source, and the second The low voltage side terminal of the resistor string is connected to a second voltage source having a lower voltage value than the first voltage source.

According to a third aspect of the present invention, the first and second resistor rows are arranged close to each other on a plane, and the voltage comparison circuit includes the plurality of voltage comparators on one or both sides of the resistor row on the same plane. The arrangement is arranged in parallel with the resistor array, and an encoder for obtaining a digital value from the output of the voltage comparator is arranged outside the array of voltage comparators in parallel with the array of voltage comparators.

According to a fourth aspect of the present invention, at least two or more combinations of the resistor row, the voltage comparator row, and the encoder are arranged on the same plane so that the resistor rows in each set are parallel and adjacent to each other. An A / D converter having a configuration in which one end of each resistor row in the set is connected by a return wiring formed in a direction perpendicular to the resistor row direction to supply a voltage source to all the resistor rows in the set; I do.

[Action]

According to the circuit configuration of the first aspect, the positions where the first reference voltage and the second reference voltage required for each voltage comparator are generated are close to each other in the two parallel resistor rows. Therefore, it is possible to simplify the connection wiring from the resistor string to the voltage comparator. According to the second aspect, it is not necessary to separately provide a voltage source for the two resistor strings, and a single voltage source can be used as a whole. According to the third and fourth aspects, the integrated circuit area is small.
A large-scale integrated circuit of a parallel A / D converter can be realized.

〔Example〕

One embodiment of the present invention will be described with reference to FIGS.
FIG. 1 shows the configuration of the embodiment, in which a first and a second resistor string 7 for generating two reference voltages V _rh and V _rl input to each fully differential voltage comparator 1 and an analog input signal v a first input voltage v _ih and second input voltages v differential input voltage generation circuit 3 for creating _il against _i, the difference Delta] v _i of the first and second input voltage (= v _ih -v _il ) and the difference ΔV between the first and second reference voltages.
_{It comprises} a plurality of fully differential voltage comparators 1 for comparing the magnitude with _r (= V _rh -V _rl ), and an encoder 2 for outputting a digital value corresponding to the comparison result of these voltage comparators. The first and second resistor rows 7 (in the drawing, the left side is the first,
The right side is referred to as a second side) in which a plurality of resistors are connected in series, and are arranged close to each other on the same plane so as to be parallel to each other. Then, the voltage source at the top terminal of the first resistor string voltage V _RT, the lower terminal is connected to the voltage source voltage value V _RB (V _RJ), The lower terminal of the second resistor string voltage upper terminal to another source value V _RT is connected to another source of voltage V _RB. Each of the voltage comparators 1 includes first and second input voltages v _ih and v _il from the differential input voltage generation circuit 3 and a first voltage generated as a _divided voltage of the first and second resistor strings 7. And the second reference voltage V _rh , V _rl are input. In this case, for example, the voltage comparator 1 at the uppermost position shown in the figure is generated from the voltage dividing point at the uppermost position of the first resistor string. And a second reference voltage generated from the highest voltage dividing point of the second resistor string.

Differential input voltage generating circuit 3, and the analog input voltage v _i,
A circuit for creating a first input voltage _{vi i} that increases in proportion to an increase in a difference from a constant reference voltage and a second input voltage v _il that decreases in proportion to an increase in the difference; the input voltage v _i of the case, the first created, indicating the second input voltage v _ih, a relationship characteristic of the v _il in Figure 2. Input voltage v _i is the reference voltage V
If equal to _RB (V _{RT) is, v ih = V RB, v} il = V RT becomes also, in the case of v _i = V _RT is v _ih = v _RT, v such that _il = V _RB , V _ih increases and v _il decreases linearly in proportion to the increase in input voltage v _i . Therefore, the input voltage v _i = (V
_{At (RT} + V _RB ) / 2, Δv _i (= v _ih −v _il ) changes sign from minus to plus.

FIG. 3 shows an embodiment of the differential input voltage generating circuit 3.
Capacitor C ₁ and switch S ₁ between input and output of differential amplifier 6
Are connected in parallel, and a capacitor C ₂ and a switch S ₂ for AC input of the analog input voltage v _i are connected to a differential amplifier 6.
Is connected in series to each input terminal, and one switch S ₂
One end to the input voltage v _i, the one end of the other switch S ₂ is connected to ground. Also, short-circuiting switch S is connected between the connection end these switches S ₂ and the capacitor C _2. The charge stored in accordance with the input voltage v _i AC input capacitor C ₂ to the differential amplifier 6, mutually codes are different absolute values to the capacitor C ₁ connected between the input and output of the differential amplifier 6 Generate differential voltages v _ih , v _il by distributing equal charges.

FIG. 4 shows an embodiment of the fully differential voltage comparator 1 used in the A / D converter of the present invention. (A) is a circuit configuration diagram, in which a plurality of amplifiers 4 in which a shortening switch SWAZ is connected between the input and output of a differential amplifier 6 and a capacitor C is connected in series to each input terminal are connected in multiple stages, and a first stage capacitor is connected. each of the C end of the reference voltage V _rh and the input voltage v _ih and also the reference voltage V _rl and the input voltage v switches _il switching alternately input ^{_{SW + r, SW + i,}} SW - r, SW - _i is connected. Also,
A latch circuit 5 that outputs a logical value determined from the output of the present amplifier is connected to the final stage amplifier. (B) shows a state diagram of the opening and closing of the switch. First, the switches SWAZ between the inputs and outputs of all the differential amplifiers 6 are closed, and the input and output terminals of each differential amplifier 6 are self-biased. At the same time, reference voltages V _rh and V _rl are input to the first stage, respectively. Then opens switch SWAZ between the input and output of the differential amplifier 6, the first stage input voltage v _ih, v _il are applied _{respectively, ΔV r (= V rh -V} rl)
And the difference between Δv _i (= v _ih −v _il ) is amplified and output.

FIG. 5 shows a circuit configuration diagram of another embodiment of the present invention (corresponding to a case where voltage comparator rows are arranged on both sides of the resistor row in claims 2 and 3). The difference from the embodiment of FIG.
The low voltage side terminal of the first resistor string and the high voltage side terminal of the second resistor string are electrically connected, and the voltage source connected to these terminals is removed. The point is that the voltage comparator row 1 is arranged on both sides, and the encoders 2 are arranged outside the voltage comparator row 1 respectively. With such a circuit configuration, for example, the uppermost voltage comparator 1 on the left and the uppermost voltage comparator 1
As the first and second reference voltages V _rh and V _rl used for the first and second resistance strings, those generated from the highest voltage _{dividing point} of the first and second resistor rows can be used in common. (That is, ΔV _r =
(V _rh −V _rl may have the same absolute value and plus and minus signs), so that the connection wiring from the resistor string to the voltage comparator string can be greatly simplified.

6 to 9 show the arrangement of an embodiment in which the A / D converter of the present invention is integrated, in which parts relating to the input voltage are omitted, and each voltage comparator is a rectangular block. It is shown.

FIG. 6 is an integrated circuit block diagram corresponding to the circuit of FIG. 5, in which two resistor arrays each formed by connecting a large number of unit resistors in series on a straight line are closely arranged in parallel on the same plane. Place, connect one end close to the other, and connect one end of the other end to the voltage source
V _RT , the other end is connected to a voltage source V _RB (<V _RT ), and a fully differential voltage comparator row is arranged in parallel on both outer sides of the resistor row, and further parallel to the outside, An encoder 2 for obtaining a digital value from each voltage comparator output is arranged.

FIG. 7 is a block diagram in the case where the fully differential voltage comparison row and the encoder in the circuit of FIG. 5 are arranged on only one side of the resistance row.

8 and 9 show that when the circuit scale of the resistor array, the voltage comparator array, and the encoder is further increased, two or more combinations of the resistor array, the voltage comparator array, and the encoder are arranged on the same plane. Are arranged in parallel with each other, and one end of each of the resistor rows in an adjacent set is connected to each other by a return wiring formed in a direction perpendicular to the resistor row direction,
In this configuration, the voltage sources V _RT and V _RB are commonly used for each set of resistor strings. Figure 8 is a sixth diagram configuration of those two sets, V _RT, the case of arranging on the same plane to use V _RB common, Figure 9 is a thing of Figure 7 Configuration 2 pairs Similarly, a case is shown in which the voltage sources are commonly used and arranged on the same plane.

〔The invention's effect〕

As described above, according to claim 1 of the present invention, the difference [Delta] V _r of the two reference voltages using a fully differential voltage comparator as a voltage comparator, the two corresponding to the input signal v _i in a / D converter system for comparing the difference Delta] v _i of the input signal, two resistor strings for generating a reference voltage, with the construction arranged parallel to, two criteria used in the voltage comparator The voltage generation positions come close to each other, which makes it possible to greatly simplify the approach wiring from the resistor string to each voltage comparator.

According to the second aspect, in addition to the above effects, there is an advantage that the high-voltage side voltage source and the low-voltage side voltage source can be commonly used for the two resistor strings, and the power supply configuration can be simplified.

According to the third and fourth aspects, when a parallel A / D converter using a fully-differential voltage comparator that is resistant to power supply noise and the like is integrated, an area of the integrated circuit is significantly reduced. There is an effect that can be.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of one embodiment of the present invention, FIG. 2 is a diagram showing input / output characteristics of a differential input voltage generating circuit used in the present invention, and FIG. 3 is a differential diagram used in the present invention. FIG. 4 is a diagram showing one embodiment of an input voltage generating circuit, FIG. 4 is a diagram showing one line of a fully differential voltage comparator used in the present invention, FIG. 5 is a configuration diagram showing another embodiment of the present invention, 6, 7, 8, and 9 are diagrams each showing a circuit arrangement when the A / D converter of the present invention is integrated, and FIGS. 10 and 11 are related to the present invention. FIG. [Explanation of Symbols] 1 ... Completely differential voltage comparator 2 ... Encoder 3 ... Differential input voltage generation circuit 4 ... Amplifier 5 ... Latch circuit 6 ... Differential amplifier 7 ... Resistance string 8 ...... Voltage comparator

──────────────────────────────────────────────────続 き Continuation of the front page (72) Inventor Tatsuharu Matsuura 1-280 Higashi Koikebo, Kokubunji-shi, Tokyo Inside the Central Research Laboratory, Hitachi, Ltd. (56) References JP-A-3-93314 (JP, A) JP-A-3 -163914 (JP, A) JP-A-63-164621 (JP, A) JP-A-64-4118 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB name) H03M 1/00- 1/88

Claims (4)

(57) [Claims] A first power supply terminal to which a first voltage source is supplied; a second power supply terminal to which a second voltage source having a voltage value different from the first voltage source is supplied; A third power supply terminal disposed close to the first power supply terminal and supplied with the second voltage source; and a third power supply terminal disposed close to the second power supply terminal and supplied with the first voltage source. 4, a first resistor string formed by connecting a plurality of resistors in series between the first power terminal and the second power terminal, and the same number of resistors as the first resistor string. A second series of resistors connected in series between the third power supply terminal and the fourth power supply terminal substantially parallel to the first series of resistances; an analog input voltage and a constant reference voltage; Generating means for generating a first input voltage that increases in proportion to the difference between the first input voltage and a second input voltage that decreases in proportion to the difference; One of the voltages divided by the second resistor string is set as one of the voltages divided by the second resistor string.
A plurality of voltages for comparing a difference between the first reference voltage and the second reference voltage with a difference between the first input voltage and the second input voltage, using a second reference voltage as a reference voltage; An analog / digital converter, comprising: a comparator; and means for obtaining a digital value from outputs of the plurality of voltage comparators. 2. A first power supply terminal to which a first voltage source is supplied, and a second voltage source arranged close to the first power supply terminal and having a voltage value different from that of the first voltage source. A second power supply terminal to be supplied; a circuit contact disposed apart from the first power supply terminal and the second power supply terminal; and a plurality of resistors connected to the first power supply terminal and the circuit contact. A first resistor row connected in series between the first resistor row and the same number of resistors between the circuit contact and the second power supply terminal substantially in parallel with the first resistor row. A second series of resistors, a first input voltage that increases in proportion to the difference between the analog input voltage and the fixed reference voltage, and a second input voltage that decreases in proportion to the difference. Generating means for generating one of the voltages divided by the first resistor string as a first reference voltage. Of a voltage divided by the column 1
A plurality of voltages for comparing a difference between the first reference voltage and the second reference voltage with a difference between the first input voltage and the second input voltage, using a second reference voltage as a reference voltage; An analog / digital converter, comprising: a comparator; and means for obtaining a digital value from outputs of the plurality of voltage comparators. 3. The first resistor row and the second resistor row are arranged close to each other on a plane, and one or both sides of the first resistor row and the second resistor row on this plane. A voltage comparator array comprising the plurality of voltage comparators is disposed substantially in parallel with the first resistor array or the second resistor array, and the voltage comparator array of the plurality of voltage comparators is further provided outside the voltage comparator array. 3. An analog / digital converter according to claim 2, wherein said means for obtaining a digital value from an output includes an encoder arranged substantially in parallel with said voltage comparator array. 4. A combination of at least two sets of the resistor row, the voltage comparator row, and the encoder according to claim 3, wherein the resistor rows in each set are substantially parallel on the plane. In addition, one end of each of the resistor rows in the adjacent set is connected by a folded wiring formed in a direction substantially perpendicular to the resistor row, so that a voltage source for all the resistor rows in the set is common. Analog / digital converter.