JP3264758B2 - Analog-to-digital converter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flash type analog / digital converter (hereinafter, referred to as an AD converter) for converting an analog signal such as a video signal into a digital signal.

[0002]

2. Description of the Related Art Generally, an A / D converter called a flash type is used as an A / D converter requiring a fast conversion time for a video signal or the like. An AD converter called a flash type has a number of voltage comparators arranged in parallel and converts them into digital data at a time, so that high conversion speed can be realized.

FIG. 2 shows a conventional n-bit flash type AD.
FIG. 3 is a block diagram illustrating a configuration of a converter. COM1, CO
M2, COM (n-1) are voltage comparators, and COM1, COM2, COM2,
The symbol COM (n-1) is attached.

Each voltage comparator has a reference resistor R1 · R
The voltage of the reference signal divided by 2 · R (n−1) · R (n) is compared with the voltage of the analog input based on the reference signal. The voltage comparator outputs a "low" or "high" digital signal. The output of each voltage comparator is held in a latch circuit LT1, LT2, LT (n-1) corresponding to each voltage comparator, and the output of the latch circuit is digitally coded and output via an encoder ENC1.

To obtain n-bit information from the output of the encoder ENC1 means to decompose the analog quantity into 2 n power states, which requires 2 n -1 voltage comparators. Each voltage comparator has the same circuit, and compares the voltage of each reference signal divided by the reference resistor with the voltage of an analog input to output a digital signal.

FIG. 3 is a circuit diagram showing a configuration of a voltage comparator in a conventional AD converter. Next, a circuit configuration of a voltage comparator such as COM1 shown in FIG. 2 will be described with reference to FIG.

[0007] A first inverter circuit 301 for inverting and outputting the control clock, a second inverter circuit 305 for outputting the result of comparing the voltage of the reference signal with the voltage of the analog input as a digital signal, A first semiconductor switch 302, a second semiconductor switch 303, and a third semiconductor switch 304, which are opened and closed (on-off) by an inverted clock of a control clock inverted and output by the inverter circuit 301 of FIG. D)
It is composed of a C-cut capacitor 306, a parasitic capacitance 307 which is a parasitic capacitance due to a gate capacitance of the second inverter circuit 305 and a junction capacitance between the input side diffusion layer of the third semiconductor switch 304 and the substrate.

The first semiconductor switch 302, the second semiconductor switch 303, and the third semiconductor switch 304 generally have a transmission gate composed of a field-effect P-type transistor and an N-type transistor. .

The circuit operation of the voltage comparator in the conventional AD converter shown in FIG. 3 will be described. Control clock is "
When “high”, the first semiconductor switch 302 and the third semiconductor switch 304 are turned “on”, and the second semiconductor switch 303 is turned “off”. By setting the potential to the voltage of the reference signal and short-circuiting the input and output of the second inverter circuit 305, the DC cut capacitor 3
06 The potential of the other terminal B point is set to Ｖ VDD, and the electric charge is accumulated in the DC cut capacitor 306.

Next, when the control clock goes low,
First semiconductor switch 302, third semiconductor switch 3
04 is turned off, and the second semiconductor switch 303 is turned on. The potential at one terminal A of the DC cut capacitor 306 changes to the analog input voltage, so that the potential at the other terminal B of the DC cut capacitor 306 and the input terminal of the second inverter circuit 305 change. Therefore, when the potential of the input terminal of the second inverter circuit 305 changes, the second inverter circuit 30
5 changes and outputs the comparison result as a digital signal.

FIG. 5 shows a pattern layout diagram of a voltage comparator in a conventional AD converter. The pattern layout shown in FIG. 5 has a complementary metal oxide semiconductor (hereinafter referred to as CMOS) structure using a P-type semiconductor substrate.
Power is supplied to the circuit by the DD wiring 503 and the VSS wiring 504.

First semiconductor switch 302 shown in FIG.
Is a first semiconductor switch 508 shown in FIG. The second semiconductor switch 303 shown in FIG. 3 is the second semiconductor switch 509 shown in FIG. Further, the third semiconductor switch 304 shown in FIG.
Is a third semiconductor switch 502 shown in FIG.

A first semiconductor switch 508 shown in FIG.
Second semiconductor switch 509, third semiconductor switch 5
The P-type transistor 02 is formed on the N-well region 501. The DC cut capacitor 505 is also formed on the N-well region 501.

Here, since the DC cut capacitor 505 and the third semiconductor switch 502 need to separate the N-well region 501, they must be separated by a certain distance in accordance with the design rules.

[0015]

However, the conventional n-bit flash A / D converter shown in FIG. 2 increases the encoder ENC1 by one bit because 2 n-1 voltage comparators are arranged in parallel. And the number of voltage comparators doubles. Therefore, there is a problem that the pattern layout area increases. In particular, the area of the DC cut capacitor 306 shown in FIG. 3 largely depends on the layout area.

Further, in terms of a circuit, an increase in the number of voltage comparators also increases the total DC cut capacitor and the total parasitic capacitance, and lowers the input impedance as viewed from the analog input side. Therefore, the drive capability of an analog output circuit that inputs an analog signal to the AD conversion circuit is required.

However, if the capacity of the DC cut capacitor 306 shown in FIG.
The ratio of the parasitic capacitance 307 to the capacitance of 06 is large, which affects the accuracy of the AD converter.

An object of the present invention is to solve the above-mentioned problems, to improve the accuracy of AD conversion by reducing the parasitic capacitance, and to reduce the DC cut capacitor, increase the input impedance, and increase the area efficiency. It is to provide a conversion circuit.

[0019]

In order to achieve the above-mentioned object, the present invention relates to a flash A / D converter composed of a complementary metal oxide semiconductor, and an auto-balanced A / D converter constituting the A / D converter. In the voltage comparator, a semiconductor switch for connecting the input and output of an inverter circuit for comparing voltages and determining an operating point is constituted by a transistor of a conductivity type opposite to a semiconductor substrate.

[0020]

By configuring the semiconductor switch for determining the operating point of the inverter circuit for comparing voltages with transistors of the opposite conductivity type to the semiconductor substrate, it is possible to further reduce the parasitic capacitance and improve the accuracy of the AD converter. improves. Further, the DC cut capacitor can be made smaller, and the input impedance can be increased to increase the area efficiency.

[0021]

FIG. 1 is a circuit diagram of a voltage comparator in an AD converter according to an embodiment of the present invention. FIG. 1 is a circuit diagram of a voltage comparator having a CMOS structure when a P-type semiconductor substrate is used. Next, the circuit configuration of the voltage comparator will be described with reference to FIG.

A first inverter circuit 101 for inverting and outputting the control clock, a second inverter circuit 105 for outputting the result of comparing the voltage of the reference signal and the voltage of the analog input as a digital signal, a control clock and the first A first semiconductor switch 102, a second semiconductor switch 103, and a third semiconductor switch 104, which are opened and closed (on-off) by an inverted clock of a control clock inverted and output by the inverter circuit 101 of FIG. D)
It comprises a C-cut capacitor 106, a parasitic capacitance 107 which is a parasitic capacitance due to a gate capacitance of the second inverter circuit 105 and a junction capacitance between the input side diffusion layer of the third semiconductor switch 104 and the substrate.

The first semiconductor switch 102 and the second semiconductor switch 103 form a transmission gate with a field-effect P-type transistor and an N-type transistor, and the third semiconductor switch 104 is a second inverter circuit 105. Is short-circuited, and the linearity of the resistance does not matter. Therefore, the transistor is formed of a conductive type transistor which is opposite to the semiconductor substrate, that is, an N-type transistor in FIG.

The connection state of each element will be described below. The control clock is supplied to the input terminal of the first inverter circuit 101, the control terminal of the P-type transistor of the first semiconductor switch 102, and the second semiconductor switch 103
To the control terminal of the N-type transistor.

The output of the first inverter circuit 101 is the control terminal of the N-type transistor of the first semiconductor switch 102, the control terminal of the P-type transistor of the second semiconductor switch 103, and the third semiconductor switch 104. To the control terminal.

The reference signal is connected to one terminal of the first semiconductor switch 102. The analog input is connected to one terminal of the second semiconductor switch 103.

The other terminal of the first semiconductor switch 102 and the other terminal of the second semiconductor switch 103 are each connected to one terminal A of the DC cut capacitor 106.

The other terminal of the DC cut capacitor 106 is connected to the input terminal of the second inverter circuit 105 and the third terminal.
To one terminal of the semiconductor switch 104 and one terminal of the parasitic capacitance 107. The other terminal of the parasitic capacitance 107 is connected to the ground of the AD converter.

The other terminal of the third semiconductor switch 104 is connected to the output terminal of the second inverter circuit 105.

The circuit operation of the voltage comparator in the AD converter of the present invention shown in FIG. 1 will be described. When the control clock is “low”, the first semiconductor switch 102 and the third
Of the second semiconductor switch 103 is turned on, and the second semiconductor switch 103 is turned off. The voltage at one terminal A of the DC cut capacitor 106 is short-circuited to the voltage of the reference signal because the first semiconductor switch 102 is turned on. The voltage at this time is VR1.

At the same time, the third semiconductor switch 104 is also turned on, so that the input and output of the second inverter circuit 105 are short-circuited, and the outputs of the N-type transistor and the P-type field effect transistor of the second inverter circuit 105 are output. Assuming that the impedance is the same, the second inverter circuit 105 includes the DC cut capacitor 106 and the parasitic capacitance 1
07 is charged and the voltage is 1/2 VDD which is half of the power supply voltage.
Is generated in the other terminal of the DC cut capacitor 106 and the parasitic capacitance 107. This is called auto-balancing, and this voltage becomes the threshold voltage of the inverter circuit.

Therefore, a voltage of VR1-1 / 2VDD is applied to both ends of the DC cut capacitor 106, and if the capacitance of the DC cut capacitor 106 is C1, DC
The electric charge q1 stored in the cutting capacitor 106 is C
It becomes 1 × (VR1-1 / 2VDD). Parasitic capacitance 107
Is C2, the electric charge q2 stored in the parasitic capacitance 107 is C2 × １ ／ VDD.

When the control clock is "high", the first semiconductor switch 102 and the third semiconductor switch 104 are "high".
The second semiconductor switch 103 is turned "off" and the second semiconductor switch 103 is turned "on." The input and output of the second inverter circuit 105 are separated because the third semiconductor switch 104 is turned "off."
Since the input impedance of the MOS is very high, there is no path through which the charge / discharge current of the parasitic capacitance 107 flows.

Therefore, the electric charge of the parasitic capacitance 107 moves only to the DC cut capacitor 106. That is, the difference (q1-q2) between the charges of the DC cut capacitor 106 and the parasitic capacitance 107 is preserved.

That is, (q1-q2) = VR1 × C1
−1/2 (C1 + C2) × VDD does not change until the third semiconductor switch 104 is turned on next time. Assuming that the voltage of the analog input is Vin, the voltage of one terminal A of the DC cut capacitor 106 is changed to the first semiconductor switch 102 by the control clock becoming “High”.
Is turned off and the second semiconductor switch 103 is turned on, so that VR1 changes to Vin.

At this time, consider the input voltage of the second inverter circuit 105, that is, the voltage applied to both ends of the parasitic capacitance 107. First, Vin is applied to the DC cut capacitor 106 and the parasitic capacitance 107 in series, so that Vin = q
1 / C1 + q2 / C2 holds.

This equation and the above equation (q1-q2) are expressed by q2
If rearranged as follows, q2 = 1 / 2C2 × VDD + C1C2 /
(C1 + C2) × (Vin−VR1) and the parasitic capacitance 1
Assuming that the voltage at both ends of 07 is V2, V2 = q2 / C2, so V2 = 1 / 2VDD + {C1 / (C1 + C2)}.
(Vin-VR1).

Here, it is clear that the accuracy of the AD converter improves as C1 / (C1 + C2) approaches 1.
That is, it is understood that the capacitance C2 of the parasitic capacitance 107 should be as close as possible to zero.

The parasitic capacitance 107 comprises the gate capacitance of the second inverter circuit 105 and the diffusion capacitance on the input side of the third semiconductor switch 104. In the present invention, the third semiconductor switch 104 is constituted by a single N-type transistor. Therefore, the parasitic capacitance 107 on the input side of the third semiconductor switch 104 shown in FIG. 1 is reduced as compared with the third semiconductor switch 304 shown in FIG. 3 constituted by the conventional N-type transistor and P-type transistor. The accuracy of the analog-to-digital converter is improved.

If the parasitic capacitance 107 is small, DC
The capacity of the cutting capacitor 106 can be reduced, and the pattern layout area can be reduced.

FIG. 4 shows a pattern layout of the voltage comparator according to the present invention. The pattern layout shown in FIG. 4 has a CMOS structure using a P-type semiconductor substrate, and power is supplied to the circuit by a VDD wiring 403 and a VSS wiring 404.

The first semiconductor switch 102 shown in FIG.
Is a first semiconductor switch 408 shown in FIG. The second semiconductor switch 103 shown in FIG. 1 is the second semiconductor switch 409 shown in FIG. Further, the third semiconductor switch 104 shown in FIG.
Is a third semiconductor switch 402 shown in FIG.

The first semiconductor switch 408 shown in FIG.
The P-type transistor of the second semiconductor switch 409 is formed on the N-well region 401, and the DC cut capacitor 405 is also formed on the N-well region 401.

The third semiconductor switch 4 shown in FIG.
02 is composed of only N-type transistors which are opposite to the semiconductor substrate, so that there is no need to form an N-well region which is opposite to the semiconductor substrate. Therefore, compared to the conventional example, DC
It is not necessary to keep the distance between the wells with respect to the cutting capacitor 405, thereby reducing the pattern layout area.

Further, since the number of transistors is one less than that of the conventional example, the pattern layout area is further reduced.

This does not mean that a large layout area is reduced in terms of one voltage comparator. For example, an 8-bit AD converter requires 255 voltage comparators and an 8-bit AD converter. The overall layout area is considerably reduced.

Further, if the parasitic capacitance 107 in FIG. 1 is reduced, the DC cut capacitor 10 can be maintained as long as the charge accumulated in the DC cut capacitor 106 can be maintained during the conversion from analog to digital.
6 can be made as small as possible. By making the parasitic capacitance 107 small, it greatly contributes to the reduction of the whole pattern layout area, and the input impedance of the AD converter can be made high.

In the embodiment of the present invention, a P-type semiconductor substrate is used. However, when an N-type semiconductor substrate is used,
The same effect as that of the embodiment of the present invention can be obtained by using a P-type transistor of the opposite conductivity type to the type semiconductor substrate and inputting a control clock to the control terminal.

Further, although the embodiment of the present invention has a CMOS structure using a P-type semiconductor substrate, it has a P-well region and an N-well region in order to accurately adjust the threshold voltage of the transistor. By producing a CMOS structure, the same effect as that of the embodiment of the present invention can be obtained.

[0050]

As is apparent from the above description, according to the AD converter of the present invention, the semiconductor switch for determining the operating point of the inverter circuit for comparing the voltages is constituted by transistors of the conductivity type opposite to the semiconductor substrate. By doing so, it is possible to further reduce the parasitic capacitance and improve the accuracy of the AD converter. Further, by reducing the parasitic capacitance, the DC cut capacitor can be further reduced, the input impedance can be increased, and the area efficiency can be increased, whereby an efficient AD conversion circuit can be configured.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration of a voltage comparator in an AD converter according to the present invention.

FIG. 2 is a block diagram showing a configuration of a conventional n-bit flash AD converter.

FIG. 3 is a circuit diagram showing a configuration of a voltage comparator in a conventional AD converter.

FIG. 4 is a pattern layout diagram of a voltage comparator in the AD converter according to the present invention.

FIG. 5 is a pattern layout diagram of a voltage comparator in a conventional AD converter.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 101 1st inverter circuit 102 1st semiconductor switch 103 2nd semiconductor switch 104 3rd semiconductor switch 105 2nd inverter circuit 106 DC cut capacitor 107 parasitic capacitance

Claims (1)

(57) [Claims] [Claim 1] inverter circuit for comparing the voltage and the in-
A semiconductor connected between the input and output of the barter circuit to determine the operating point
One terminal is connected to the switch and the input terminal of the inverter.
-Balanced with a DC cut capacitor
Metal oxide film composed of a voltage converter of the type
Flash type analog / digital
In the Tal converter , the DC cut capacitor is a conductor opposite to the semiconductor substrate.
An electric well is used as one terminal, and the well is connected via an oxide film.
Using the conductive member provided on the terminal as the other terminal
And the other terminal is an input terminal of the inverter.
Connected to said semiconductor switch, analog-to-digital converter, characterized by being configured only by one transistor of the opposite conductivity type to the semiconductor substrate.