JPH04181814A - Analog/digital converter - Google Patents

Analog/digital converter

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Publication number
JPH04181814A
JPH04181814A JP30873890A JP30873890A JPH04181814A JP H04181814 A JPH04181814 A JP H04181814A JP 30873890 A JP30873890 A JP 30873890A JP 30873890 A JP30873890 A JP 30873890A JP H04181814 A JPH04181814 A JP H04181814A
Authority
JP
Japan
Prior art keywords
voltage
resistor
input
array
string
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP30873890A
Other languages
Japanese (ja)
Other versions
JP2982909B2 (en
Inventor
Shigeki Imaizumi
栄亀 今泉
Kunihiko Usui
邦彦 臼井
Tatsuji Matsuura
達治 松浦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi ULSI Engineering Corp
Hitachi Ltd
Original Assignee
Hitachi ULSI Engineering Corp
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi ULSI Engineering Corp, Hitachi Ltd filed Critical Hitachi ULSI Engineering Corp
Priority to JP2308738A priority Critical patent/JP2982909B2/en
Publication of JPH04181814A publication Critical patent/JPH04181814A/en
Application granted granted Critical
Publication of JP2982909B2 publication Critical patent/JP2982909B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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  • Analogue/Digital Conversion (AREA)

Abstract

PURPOSE:To simplify the wiring by connecting a 1st resistor array comprising series connection of plural resistors and a 2nd resistor array comprising series connection of same number of resistors between two voltage sources respectively and arranging both the resistor arrays in parallel so that the direction of voltage drop is caused in opposite directions to each other. CONSTITUTION:Each of 1st and 2nd resistor arrays 7 consists of series connection of plural resistors and they are arranged close to each other in parallel on a same plane. Then each of voltage comparators 1 receives four signals being 1st and 2nd input voltages Vsr, Vsv from a differential input voltage generating circuit 3 and 1st and 2nd reference voltages Vxr, Vxv generated as divided voltages of the 1st and 2nd resistor arrays 7. The two resistor arrays generating a reference voltage are arranged in parallel in this way, then the generating positions of the two kinds of the reference voltages used for each voltage comparator are arranged close to each other. Thus, the connection wiring from the resistor arrays to each voltage comparator is considerably simplified.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明はアナログ/ディジタル(以下、A/Dと記す)
変換器に係り、特に、高速で高精度、しかも集積回路化
に際して面積を低減することのできるA/D変換器に関
する。
[Detailed Description of the Invention] [Industrial Application Field] The present invention is an analog/digital (hereinafter referred to as A/D)
The present invention relates to a converter, and particularly to an A/D converter that is high-speed, highly accurate, and can reduce the area when integrated into a circuit.

〔従来の技術〕[Conventional technology]

本発明に関連するA/D変換器については、ジェームズ
ジー・ピーターソン、″モノリシックビデオA/D変換
器″、アイ イーイーイージャーナルオブソリッドステ
ートサーキット、ニスシー14巻、6号、932−93
7頁。
Regarding A/D converters related to the present invention, see James G. Peterson, "Monolithic Video A/D Converter," IEJ Journal of Solid State Circuits, Nisshi Vol. 14, No. 6, 932-93.
7 pages.

1979年12月(James G、 Peterso
n、 ”AMonolithic Video A/ 
D Convertor、” I EEE  J 、 
5olid−5tate C1rcuits、 Vol
December 1979 (James G, Peterso
n, ”AMonolithic Video A/
D Convertor,” I EEE J,
5olid-5tate C1rcuits, Vol.
.

SC−14,No、6.pp、932−937.Dec
SC-14, No, 6. pp, 932-937. Dec
.

1979)において論じられている。1979).

第10図に上記において論じられている並列型A/D変
換器の構成を示す。これは、2つの電圧源VHJI V
)l” (<VHJ)間に接続された基準電圧発生用の
抵抗列7と、その分圧電圧として発生する基準電圧VH
と入力信号V、との大小を比較する複数並列に設けられ
た電圧比較器8と、この比較結果よりディジタル値を8
力するエンコーダ2より構成されている。
FIG. 10 shows the configuration of the parallel A/D converter discussed above. This consists of two voltage sources VHJI V
)l” (<VHJ) and the reference voltage VH generated as its divided voltage.
A plurality of voltage comparators 8 are provided in parallel to compare the magnitudes of the input signal V and the input signal V.
It is composed of an encoder 2 that outputs power.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

従来技術による第10図構成のものは、1つの基準電圧
と1つの入力信号の大小を比較する方式であることから
、各種の雑音が基準電圧あるいは入力信号に混入して比
較誤りとなり易いという問題点があった。
The conventional technology with the configuration shown in FIG. 10 is a method that compares the magnitude of one reference voltage and one input signal, so there is a problem that various noises are likely to mix into the reference voltage or input signal, resulting in a comparison error. There was a point.

これを解決する手段として、第11図に構成例を示すよ
うに、2つの基準電圧Vxr=Vにワの差ΔVX(=V
χ−Vxv)と、入力信号■5に対応する2つの入力信
号vsY、vsvの差ΔV 5 (” V s r−V
sJを完全差動型電圧比較器lで比較することにより、
雑音に強く高精度なA/D変換器が実現されることが知
られている。
As a means to solve this problem, as shown in FIG. 11, a difference ΔVX (=V
χ-Vxv) and the difference between the two input signals vsY and vsv corresponding to the input signal ■5
By comparing sJ with a fully differential voltage comparator l,
It is known that a highly accurate A/D converter that is resistant to noise can be realized.

しかし、この第11図構成を採用する場合、図示のよう
に抵抗列から発生する各基準電圧をそれぞれ2つに分岐
させたうえ個々の電圧比較器に入力する方式であること
から、配線が複雑となり、集積回路化する場合に面積の
増大を招くという問題点がある。
However, when adopting the configuration shown in Figure 11, the wiring is complicated because each reference voltage generated from the resistor string is branched into two and then input to each voltage comparator as shown in the figure. Therefore, there is a problem in that the area increases when integrated into a circuit.

本発明の目的は、従来技術での上記した完全差動型電圧
比較器による場合の問題点を解決し、集積回路化する場
合にも面積の増大を招くことのないA/D変換器を提供
することにある。
An object of the present invention is to solve the problems of the above-mentioned fully differential voltage comparators in the prior art, and to provide an A/D converter that does not increase the area even when integrated into an integrated circuit. It's about doing.

〔課題を解決するための手段〕[Means to solve the problem]

上記目的を達成するために、本発明の請求項1において
は、複数の抵抗体を直列接続してなる第1の抵抗列を電
圧値が異なる2つの電圧源間に接続し、同数の抵抗体を
直列接続してなる第2の抵抗列を別の2つの電圧源間に
接続すると共に電圧降下の方向が第1の抵抗列とは逆と
なるように第1の抵抗列に平行に配置し、アナログ入力
電圧と一定の参照電圧との差の増加に比例して増大する
第1の入力電圧と、比例して減小する第2の入力電圧を
作成する手段と、第1の抵抗列により分圧された電圧の
1つを第1の基準電圧とし第2の抵抗列により分圧され
た電圧の1つを第2の基準電圧として第1の基準電圧と
第2の基準電圧間の差と、上記第1の入力電圧と第2の
入力電圧間の差とを比較する複数の電圧比較器と、該電
圧比較器の出力からディジタル値を得る手段とを備えた
構成とする。
In order to achieve the above object, in claim 1 of the present invention, a first resistor string formed by connecting a plurality of resistors in series is connected between two voltage sources having different voltage values, and the same number of resistors are connected in series. A second resistor string connected in series is connected between two other voltage sources and placed parallel to the first resistor string so that the direction of voltage drop is opposite to that of the first resistor string. , means for creating a first input voltage that increases in proportion to an increase in the difference between the analog input voltage and a constant reference voltage, and a second input voltage that decreases in proportion to an increase in the difference between the analog input voltage and a constant reference voltage; One of the divided voltages is used as a first reference voltage, and one of the voltages divided by the second resistor string is used as a second reference voltage, and the difference between the first reference voltage and the second reference voltage is determined. , a plurality of voltage comparators for comparing the difference between the first input voltage and the second input voltage, and means for obtaining a digital value from the output of the voltage comparators.

請求項2では、上記第1の抵抗列の低圧側端子と第2の
抵抗列の高圧側端子とを電気的に接続して、これらの端
子に接続されていた電圧源は除去し、第1の抵抗列の高
圧側端子を第1の電圧源に、第2の抵抗列の低圧側端子
を上記第1の電圧源より低電圧値の第2の電圧源に接続
した構成とする。
In claim 2, the low voltage side terminal of the first resistance string and the high voltage side terminal of the second resistance string are electrically connected, the voltage source connected to these terminals is removed, and the first The high voltage side terminal of the resistor string is connected to a first voltage source, and the low voltage side terminal of the second resistance string is connected to a second voltage source having a lower voltage value than the first voltage source.

また、請求項3では、第1と第2の抵抗列を平面上に近
接させて配置し、同じ平面上でこの抵抗列の外方の片側
あるいは両側に上記複数の電圧比較器よりなる電圧比較
器列を抵抗列に平行に配置し、この電圧比較器列のさら
に外側に電圧比較器出力からディジタル値を得るエンコ
ーダを電圧比較器列と平行に配置する構成とする。
Further, in claim 3, the first and second resistor arrays are disposed close to each other on a plane, and the voltage comparators are provided on one side or both sides of the resistor array on the same plane. The voltage comparator array is arranged in parallel with the resistor array, and further outside the voltage comparator array, an encoder that obtains a digital value from the voltage comparator output is arranged in parallel with the voltage comparator array.

さらに、請求項4においては、上記の抵抗列、電圧比較
器列、エンコーダの組合せ構成を少なくとも2組以上、
同じ平面上に各組内の抵抗列が平行するように配列し、
かつ、隣接する組内の抵抗列の各一方端を、抵抗列方向
とは直角方向に形成される折り返し用配線により接続し
て、全組内抵抗列に対する電圧源を共通とする構成のA
/D変換器とする。
Furthermore, in claim 4, at least two or more combinations of the above-described resistor array, voltage comparator array, and encoder,
The resistor rows in each set are arranged in parallel on the same plane,
A configuration in which one end of each of the resistor strings in adjacent groups is connected by a folding wiring formed in a direction perpendicular to the direction of the resistance strings, and a common voltage source is used for all the resistance strings in the group.
/D converter.

〔作用〕[Effect]

請求項1の回路構成によれば、個々の電圧比較器に必要
となる第1の基準電圧と第2の基準電圧の発生位置が、
平行に配置された2本の抵抗列において互いに近接する
ようになり、このため、抵抗列から電圧比較器への接続
配線を簡略化することが可能となる。請求項2によれば
、電圧源を2本の抵抗列に対して別個に設ける必要がな
く、全体で1組の電圧源とすることができる。また、請
求項3及び4によれば、集積回路面積の小さい、並列型
A/D変換器の大規模集積回路化が実現可能となる。
According to the circuit configuration of claim 1, the generation positions of the first reference voltage and the second reference voltage required for each voltage comparator are as follows.
The two resistor arrays arranged in parallel are located close to each other, which makes it possible to simplify the connection wiring from the resistor array to the voltage comparator. According to claim 2, there is no need to provide separate voltage sources for the two resistor strings, and the entire set of voltage sources can be used. Further, according to claims 3 and 4, it is possible to realize a large-scale integrated circuit of a parallel type A/D converter with a small integrated circuit area.

〔実施例〕〔Example〕

本発明の一実施例を第1図〜第4図により説明する。第
1図は実施例の構成を示し、個々の完全差動電圧比較器
1に入力される2つの基準電圧Vxyg Vxvを発生
する第1及び第2の抵抗列7と、アナログ入力信号V、
に対して第1の入力電圧vsr及び第2の入力電圧v6
vを作成する差動入力電圧作成回路3と、この第1と第
2の入力電圧の差ΔV S (” V S y  ’/
 sy )と第1と第2の基準電圧の差ΔVX(=VX
、−Vχいとの大小を比較する複数の完全差動電圧比較
器1と、これらの電圧比較器の比較結果に対応するディ
ジタル値を出力するエンコーダ2より構成されている。
An embodiment of the present invention will be described with reference to FIGS. 1 to 4. FIG. 1 shows the configuration of an embodiment, which includes first and second resistor strings 7 that generate two reference voltages Vxyg and Vxv that are input to each fully differential voltage comparator 1, and an analog input signal V,
with respect to the first input voltage vsr and the second input voltage v6
The differential input voltage generation circuit 3 that generates the voltage V and the difference between the first and second input voltages ΔV S ("V S y '/
sy ) and the difference between the first and second reference voltages ΔVX (=VX
, -Vχ, and an encoder 2 that outputs a digital value corresponding to the comparison results of these voltage comparators.

第1及び第2の抵抗列7(図示では左側を第1、右側を
第2とする)は、それぞれ、複数の抵抗体を直列接続し
てなり、同じ平面上に互いに平行するように、近接して
配置される。そして、第1の抵抗列の上部端子は電圧値
VHJの電圧源に、下部端子は電圧値VH”(<VHJ
) (1)電圧源に接続され、また、第2の抵抗列の下
部端子は電圧値VHJの別の電圧源に、上部端子は電圧
値vHwIの別の電圧源に接続される。
The first and second resistor arrays 7 (in the figure, the left side is the first and the right side is the second) are each made up of a plurality of resistors connected in series, and are arranged adjacent to each other so as to be parallel to each other on the same plane. will be placed. The upper terminal of the first resistor string is connected to the voltage source of voltage value VHJ, and the lower terminal is connected to the voltage source of voltage value VH''(<VHJ
) (1) Connected to a voltage source, and the lower terminal of the second resistor string is connected to another voltage source with voltage value VHJ, and the upper terminal is connected to another voltage source with voltage value vHwI.

各電圧比較器1には、差動入力電圧作成回路3からの第
1及び第2の入力電圧V$Y、V5vと、第1及び第2
の抵抗列7の分圧電圧として発生する第1及び第2の基
準電圧Vχ7.vχ、の4信号が入力されるが、この場
合、例えば図示の最上位置の電圧比較器1には、第1の
抵抗列の最上位置の分圧点から発生する第1の基準電圧
と、第2の抵抗列の最上位置の分圧点から発生する第2
の基準電圧が入力される。
Each voltage comparator 1 receives first and second input voltages V$Y, V5v from the differential input voltage generation circuit 3, and first and second input voltages V$Y and V5v from the differential input voltage generation circuit 3.
The first and second reference voltages Vχ7. generated as the divided voltages of the resistor string 7. In this case, for example, the illustrated voltage comparator 1 at the top position receives the first reference voltage generated from the voltage division point at the top position of the first resistor string, and The second voltage generated from the voltage dividing point at the top of the second resistor string
A reference voltage is input.

差動入力電圧作成回路3は、アナログ入力電圧V、と、
一定の参照電圧との差の増加に比例して増大する第1の
入力電圧Vgyと、差の増加に比例して減小する第2の
入力電圧Vgvとを作成する回路であり、その場合の入
力電圧vsと、作成された第1.第2の入力電圧V$r
、vsvとの関係特性を第2図に示す。入力電圧Vsが
基準電圧VH’(<VHJ) ニ等シイ場合には、V 
5 y = V )l ” HVSV:VHJとなり、
またV、:V)IJの場合にはV sr= VHJr 
V sv= VH”となるように、入力電圧V、の増加
に直線的に比例して、vsrは増大し、VSVは減小す
る。したがって、入力電圧V g ”(VHJrVH”
)/2を境として、ΔV 5(= V 5r−Vsv)
はマイナスからプラスに符号が変わることになる。
The differential input voltage generation circuit 3 has an analog input voltage V, and
This is a circuit that creates a first input voltage Vgy that increases in proportion to the increase in the difference from a constant reference voltage, and a second input voltage Vgv that decreases in proportion to the increase in the difference. The input voltage vs and the created first . Second input voltage V$r
, vsv is shown in FIG. When the input voltage Vs is equal to the reference voltage VH'(<VHJ), V
5y=V)l” HVSV:VHJ,
Also, in the case of V, :V)IJ, V sr= VHJr
Vsr increases and VSV decreases in linear proportion to the increase in input voltage V, such that Vsv=VH''. Therefore, input voltage Vg''(VHJrVH''
)/2 as the border, ΔV 5 (= V 5r - Vsv)
will change its sign from negative to positive.

第3図は差動入力電圧作成回路3の一実施例を示す。差
動増幅器6の入出力間にコンデンサC1及びスイッチS
、が並列に接続され、さらにアナログ入力電圧vllを
交流入力するためのコンデンサC2とスイッチS2が差
動増幅器6のそれぞれの入力端に直列接続され、一方の
スイッチS2の一端が入力電圧v8に、他方のスイッチ
S2の一端がアースに接続されている。また、これらの
スイッチS2とコンデンサC2の接続端間に短絡スイッ
チSが接続されている。この差動増幅器6への交流入力
用コンデンサC2に入力電圧V、に応じて蓄えられた電
荷を、差動増幅器6の入出力間に接続されたコンデンサ
C1に互いに符号は異なるが絶対値は等しい電荷が分配
されることにより差動の電圧Vgy、 V5vが発生す
る。
FIG. 3 shows an embodiment of the differential input voltage generating circuit 3. A capacitor C1 and a switch S are connected between the input and output of the differential amplifier 6.
, are connected in parallel, and furthermore, a capacitor C2 and a switch S2 for inputting the analog input voltage vll as AC input are connected in series to each input terminal of the differential amplifier 6, and one end of the switch S2 is connected to the input voltage v8, One end of the other switch S2 is connected to ground. Further, a short circuit switch S is connected between the connection terminals of these switches S2 and the capacitor C2. The charges stored in the AC input capacitor C2 to the differential amplifier 6 according to the input voltage V are transferred to the capacitor C1 connected between the input and output of the differential amplifier 6, with different signs but equal absolute values. Differential voltages Vgy and V5v are generated by distributing the charges.

第4図に本発明のA/D変換器に用いられる完全差動電
圧比較器1の一実施例を示す。(a)図は回路構成図で
あり、差動増幅器6の入出力間に短絡スイッチ5WAZ
が接続され、それぞれの入力端にコンデンサCが直列接
続された増幅器4を多段直列接続し、初段のコンデンサ
Cの他端にはそれぞれ、基準電圧Vxyと入力電圧vs
、を、また基準電圧V31Vと入力電圧’I/4Hyを
交互に切り換え人力するスイッチSWx 、SWs 、
SWx 、SWsが接続されている。また、最終段の増
幅器には、本増幅器の出力から確定した論理値を出力す
るラッチ回路5が接続されている。(b)図に、スイッ
チ開閉の状態図を示す。初めに全ての差動増幅器6の入
出力間のスイッチ5WAZを閉じて各差動増幅器6の入
出力端を自己バイアスする。また同時に初段には基準電
圧Vx−,Vχ9がそれぞれ入力される。次いで差動増
幅器6の入出力間のスイッチ5WAZが開き、初段には
入力電圧v5ア。
FIG. 4 shows an embodiment of the fully differential voltage comparator 1 used in the A/D converter of the present invention. (a) is a circuit configuration diagram, in which a short-circuit switch 5WAZ is installed between the input and output of the differential amplifier 6.
Amplifiers 4 are connected in series in multiple stages, each having a capacitor C connected in series to each input terminal, and a reference voltage Vxy and an input voltage vs to the other terminal of the first stage capacitor C.
, and switches SWx, SWs, which alternately switch between the reference voltage V31V and the input voltage 'I/4Hy.
SWx and SWs are connected. Furthermore, a latch circuit 5 is connected to the final stage amplifier, which outputs a determined logical value from the output of this amplifier. Figure (b) shows a state diagram of switch opening and closing. First, the switches 5WAZ between the input and output of all differential amplifiers 6 are closed to self-bias the input and output terminals of each differential amplifier 6. At the same time, reference voltages Vx- and Vχ9 are respectively input to the first stage. Next, the switch 5WAZ between the input and output of the differential amplifier 6 is opened, and the input voltage v5A is applied to the first stage.

Vsvがそれぞれ印加され、ΔVχ(=Vχ、−VχV
)と八V 5(” V sy  V sV)の差を増幅
出力する。
Vsv is applied, and ΔVχ (=Vχ, −VχV
) and 8V 5 ("V sy V sV) is amplified and output.

第5図に本発明の他の実施例の回路構成図(請求項2、
及び請求項3の抵抗列の両側に電圧比較器列を配置した
場合に対応)を示す。第1図実施例との相違点は、第1
の抵抗列の低圧側端子と第2の抵抗列の高圧側端子とが
電気的に接続され、これらの端子に接続されていた電圧
源が除去されており、この抵抗列の外方の両側に電圧比
較器列1が、さらにこの電圧比較器列1の外側にそれぞ
れエンコーダ2が配置されている点である。このような
回路構成とすることにより、例えば図示の左側の最上位
置の電圧比較器1と右側の最上位置の電圧比較器1とに
用いる第1及び第2の基準電圧Vxr、Vχ9は、それ
ぞれ第1及び第2の抵抗列の最上位置の分圧点から発生
するものを、共通に用いることができる(即ち、Δ■に
=Vにy  Vxvとして、絶対値は同じで符号がプラ
スとマイナスのものを用いることができる)ので、抵抗
列から電圧比較器列への接続配線を大幅に簡略化させる
ことが可能となる。
FIG. 5 is a circuit configuration diagram of another embodiment of the present invention (Claim 2,
and a case where voltage comparator arrays are arranged on both sides of the resistor array according to claim 3). The difference from the embodiment in FIG.
The low voltage side terminal of the second resistor string is electrically connected to the high voltage side terminal of the second resistance string, the voltage source connected to these terminals is removed, and the The voltage comparator array 1 has an encoder 2 arranged outside the voltage comparator array 1. With such a circuit configuration, for example, the first and second reference voltages Vxr and Vχ9 used for the voltage comparator 1 at the top position on the left side and the voltage comparator 1 at the top position on the right side in the diagram are The voltage generated from the voltage dividing point at the top of the first and second resistor strings can be used in common (i.e., Δ■ = V y Vxv, the absolute value is the same and the sign is positive or negative). Therefore, it becomes possible to greatly simplify the connection wiring from the resistor array to the voltage comparator array.

第6図〜第9図は本発明のA/D変換器を集積回路化し
た場合の実施例の配置を示すもので、入力電圧に関係す
る部分を省略し、各電圧比較器を長方形ブロックで示し
たものである。
Figures 6 to 9 show the arrangement of an embodiment in which the A/D converter of the present invention is integrated.The parts related to input voltage are omitted, and each voltage comparator is constructed as a rectangular block. This is what is shown.

第6図は、第5図実施例回路に対応する集積回路化ブロ
ック図で、多数の単位抵抗体を直線上に直列接続してな
る抵抗列の2本を同じ平面上に平行に近接して配置し、
近接する一端を互いに接続し、他端の一端を電圧源VH
Jに、他方を電圧源VH”(<VHJ)に接続し、この
抵抗列の外方の両側にそれぞれ完全差動電圧比較器列を
平行に配置し、さらにその外方に平行に、各電圧比較器
出力よりディジタル値を得るエンコーダ2が配置される
FIG. 6 is an integrated circuit block diagram corresponding to the embodiment circuit shown in FIG. place,
Connect adjacent ends to each other, and connect one end to the voltage source VH.
J and the other to the voltage source VH"(<VHJ), fully differential voltage comparator arrays are placed in parallel on both sides of the outside of this resistor array, and further parallel to the outside of this resistor array, each voltage An encoder 2 is arranged to obtain a digital value from the comparator output.

第7図は、第5図実施例回路における完全差動電圧比較
器列及びエンコーダを、抵抗列の片側にのみ配置した場
合のブロック図である。
FIG. 7 is a block diagram in the case where the fully differential voltage comparator array and encoder in the embodiment circuit of FIG. 5 are arranged only on one side of the resistor array.

第8図、第9図は、抵抗列、電圧比較器列及びエンコー
ダの回路規模がさらに大きくなる場合、抵抗列、電圧比
較器列、エンコーダの組合せを2組以上、同じ平面上に
各組内の抵抗列が平行するように配置し、かつ、隣接す
る組内の抵抗列の各一方端を、抵抗列方向とは直角方向
に形成される折り返し用配線により互いに接続して、電
圧源VHJ+ v、IIを各組の抵抗列に対して共通に
使用する構成としたものである。第8図は、第6図構成
のものを2組、VHJI vH”を共通に使用するよう
に同じ平面上に配置した場合を、第9図は、第7図構成
のものを2組、同じく電圧源は共通に用いて同じ平面上
に配置した場合を示している。
Figures 8 and 9 show that when the circuit scale of the resistor array, voltage comparator array, and encoder becomes larger, two or more combinations of the resistor array, voltage comparator array, and encoder are arranged on the same plane within each set. resistor arrays are arranged in parallel, and one end of each resistor array in an adjacent group is connected to each other by a folding wiring formed in a direction perpendicular to the resistor array direction, and a voltage source VHJ+ v , II are commonly used for each set of resistor strings. Figure 8 shows the case where two sets of the configuration shown in Figure 6 are arranged on the same plane so that VHJI vH'' can be used in common, and Figure 9 shows the case where two sets of the configuration shown in Figure 7 are arranged on the same plane. The case is shown in which the voltage sources are commonly used and arranged on the same plane.

〔発明の効果〕 以上説明したように1本発明の請求項1によれば、電圧
比較器として完全差動型電圧比較器を用い2種の基準電
圧の差ΔVxと、入力信号VSに対応した2種の入力信
号の差Δvsとを比較する方式のA/D変換器において
、基準電圧を発生する抵抗列を2本、平行に配置する構
成としたことにより、各電圧比較器において用いる2種
の基準電圧の発生位置が互いに近接するようになり、こ
れにより、抵抗列から各電圧比較器への接続配線を大幅
に簡略化することが可能となる。
[Effects of the Invention] As explained above, according to claim 1 of the present invention, a fully differential voltage comparator is used as a voltage comparator to compensate for the difference ΔVx between two types of reference voltages and the input signal VS. In an A/D converter that compares the difference Δvs between two types of input signals, by arranging two resistor strings that generate a reference voltage in parallel, the two types of voltage comparators used in each voltage comparator can be The generation positions of the reference voltages are now close to each other, which makes it possible to greatly simplify the connection wiring from the resistor string to each voltage comparator.

請求項2によれば、上記効果に加えて、高圧側電圧源と
低圧側電圧源を、2本の抵抗列に対して共通に用いるこ
とができ、電源構成を簡易化できる利点がある。
According to the second aspect, in addition to the above-mentioned effects, the high-voltage side voltage source and the low-voltage side voltage source can be used in common for the two resistor strings, and there is an advantage that the power supply configuration can be simplified.

請求項3及び請求項4によれば、電源雑音等に強い完全
差動型電圧比較器を用いた並列型A/D変換器を集積回
路化する場合、集積回路の面積を大幅に低減させること
ができる効果がある。
According to claims 3 and 4, when a parallel A/D converter using a fully differential voltage comparator that is resistant to power supply noise etc. is integrated into an integrated circuit, the area of the integrated circuit can be significantly reduced. It has the effect of

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例の構成図、第2図は本発明で
使用される差動入力電圧作成回路の入出力特性を示す図
、第3図は本発明で使用される差動入力電圧作成回路の
一実施例を示す図、第4図は本発明で使用される完全差
動電圧比較器の一列を示す図、第5図は本発明の他の実
施例を示す構成図、第6図、第7図、第8図、第9図は
それぞれ本発明のA/D変換器を集積回路化する場合の
回路配置を示す図、第10図、第11図は本発明に関連
する従来技術の説明図である。 〔符号の説明〕 1・・・完全差動電圧比較器 2・・・エンコーダ 3・・・差動入力電圧作成回路 4・・・増幅器      5・・・ラッチ回路6・・
・差動増幅器    7・・・抵抗列8・・・電圧比較
器 代理人弁理士  中 村 純之助 入力tLv。 第2図 第3図 (a) 第4図 第5図 第6図 第7図 第9図 第10図 第11図
FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a diagram showing the input/output characteristics of a differential input voltage generating circuit used in the present invention, and FIG. 3 is a diagram showing the input/output characteristics of a differential input voltage generating circuit used in the present invention. A diagram showing one embodiment of the input voltage generation circuit, FIG. 4 is a diagram showing a row of fully differential voltage comparators used in the present invention, and FIG. 5 is a block diagram showing another embodiment of the present invention. 6, 7, 8, and 9 are diagrams showing circuit layouts when the A/D converter of the present invention is integrated into an integrated circuit, respectively, and Figures 10 and 11 are related to the present invention. FIG. [Explanation of symbols] 1... Fully differential voltage comparator 2... Encoder 3... Differential input voltage generation circuit 4... Amplifier 5... Latch circuit 6...
・Differential amplifier 7...Resistor string 8...Voltage comparator Junnosuke Nakamura, attorney-in-fact patent attorney Input tLv. Figure 2 Figure 3 (a) Figure 4 Figure 5 Figure 6 Figure 7 Figure 9 Figure 10 Figure 11

Claims (1)

【特許請求の範囲】 1、複数の抵抗体を直列接続してなる第1の抵抗列を電
圧値が異なる2つの電圧源間に接続し、同数の抵抗体を
直列接続してなる第2の抵抗列を別の2つの電圧源間に
接続すると共に電圧降下の方向が第1の抵抗列とは逆と
なるように第1の抵抗列に平行に配置し、アナログ入力
電圧と一定の参照電圧との差の増加に比例して増大する
第1の入力電圧と、比例して減小する第2の入力電圧を
作成する手段と、第1の抵抗列により分圧された電圧の
1つを第1の基準電圧とし第2の抵抗列により分圧され
た電圧の1つを第2の基準電圧として第1の基準電圧と
第2の基準電圧間の差と、上記第1の入力電圧と第2の
入力電圧間の差とを比較する複数の電圧比較器と、該電
圧比較器の出力からディジタル値を得る手段を備えたこ
とを特徴とするアナログ/ディジタル変換器。 2、請求項1記載の第1の抵抗列の低圧側端子と第2の
抵抗列の高圧側端子とを電気的に接続して、これらの端
子に接続されていた電圧源は除去し、第1の抵抗列の高
圧側端子を第1の電圧源に、第2の抵抗列の低圧側端子
を上記第1の電圧源より低電圧値の第2の電圧源に接続
したことを特徴とするアナログ/ディジタル変換器。 3、請求項2記載の第1の抵抗列と第2の抵抗列を平面
上に近接させて配置し、同じ平面上でこの抵抗列の外方
の片側あるいは両側に前記複数の電圧比較器よりなる電
圧比較器列を抵抗列と平行に配置し、この電圧比較器列
のさらに外側に電圧比較器出力からディジタル値を得る
エンコーダを電圧比較器列と平行に配置したことを特徴
とするアナログ/ディジタル変換器。 4、請求項3記載の抵抗列、電圧比較器列、エンコーダ
の組合せ構成を少なくとも2組以上、同じ平面上に各組
内の抵抗列が平行するように配列し、かつ、隣接する組
内の抵抗列の各一方端を、抵抗列方向とは直角方向に形
成される折り返し用配線により接続して、全組内抵抗列
に対する電圧源を共通としたことを特徴とするアナログ
/ディジタル変換器。
[Claims] 1. A first resistor string formed by connecting a plurality of resistors in series is connected between two voltage sources having different voltage values, and a second resistance string is formed by connecting the same number of resistors in series. A resistor string is connected between two other voltage sources and placed parallel to the first resistor string such that the direction of voltage drop is opposite to the first resistor string, and is connected to the analog input voltage and a constant reference voltage. means for creating a first input voltage that increases in proportion to an increase in the difference between the first input voltage and a second input voltage that decreases in proportion to an increase in the difference between the first and second input voltages; The difference between the first reference voltage and the second reference voltage, with one of the voltages divided by the second resistor string as the first reference voltage, and the first input voltage. An analog/digital converter comprising: a plurality of voltage comparators for comparing the difference between second input voltages; and means for obtaining a digital value from the output of the voltage comparators. 2. Electrically connect the low voltage side terminal of the first resistance string and the high voltage side terminal of the second resistance string according to claim 1, remove the voltage source connected to these terminals, and The high voltage side terminal of one resistor string is connected to a first voltage source, and the low voltage side terminal of a second resistance string is connected to a second voltage source having a lower voltage value than the first voltage source. Analog/digital converter. 3. The first resistor array and the second resistor array according to claim 2 are arranged close to each other on a plane, and the plurality of voltage comparators are arranged on one or both sides outside of the resistor array on the same plane. A voltage comparator array is arranged in parallel with a resistor array, and an encoder that obtains a digital value from the voltage comparator output is arranged further outside the voltage comparator array in parallel with the voltage comparator array. Digital converter. 4. At least two or more combinations of the resistor array, voltage comparator array, and encoder according to claim 3 are arranged on the same plane so that the resistor arrays in each set are parallel to each other, and An analog/digital converter characterized in that one end of each resistor string is connected by a folding wiring formed in a direction perpendicular to the direction of the resistor string, so that a common voltage source is used for all the resistance strings in the set.
JP2308738A 1990-11-16 1990-11-16 Analog / digital converter Expired - Fee Related JP2982909B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2308738A JP2982909B2 (en) 1990-11-16 1990-11-16 Analog / digital converter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2308738A JP2982909B2 (en) 1990-11-16 1990-11-16 Analog / digital converter

Publications (2)

Publication Number Publication Date
JPH04181814A true JPH04181814A (en) 1992-06-29
JP2982909B2 JP2982909B2 (en) 1999-11-29

Family

ID=17984693

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2308738A Expired - Fee Related JP2982909B2 (en) 1990-11-16 1990-11-16 Analog / digital converter

Country Status (1)

Country Link
JP (1) JP2982909B2 (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6229472B1 (en) * 1998-07-17 2001-05-08 Nec Corporation A/D converter
KR100490450B1 (en) * 2000-11-01 2005-05-19 인터내셔널 비지네스 머신즈 코포레이션 Analog-to-digital converter having positively biased differential reference inputs
JP2008235998A (en) * 2007-03-16 2008-10-02 Ricoh Co Ltd A/d converter
JP2010258685A (en) * 2009-04-23 2010-11-11 Sony Corp A/d converter

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6229472B1 (en) * 1998-07-17 2001-05-08 Nec Corporation A/D converter
KR100490450B1 (en) * 2000-11-01 2005-05-19 인터내셔널 비지네스 머신즈 코포레이션 Analog-to-digital converter having positively biased differential reference inputs
JP2008235998A (en) * 2007-03-16 2008-10-02 Ricoh Co Ltd A/d converter
JP2010258685A (en) * 2009-04-23 2010-11-11 Sony Corp A/d converter

Also Published As

Publication number Publication date
JP2982909B2 (en) 1999-11-29

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