JP2979702B2 - Method for forming electrode of semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming an electrode of a semiconductor device, and more particularly to a method for forming a back electrode of a power device which has high adhesion to a Si substrate.

[0002]

2. Description of the Related Art Conventionally, there has been known a method of manufacturing a laminated metal electrode in which a titanium film, a nickel film, and a gold film are sequentially formed on a semiconductor wafer by a sputtering method or a vapor deposition method.
There is a problem that a strong film stress is generated in the nickel film to reduce the bonding strength between the laminated metal electrode and the wafer, and that the nickel film is separated particularly at the interface between the titanium and the semiconductor wafer.

For this reason, a method of obtaining an anchor effect by polishing the wafer surface to a specific shape to increase the adhesion, or a method of reducing the nickel film stress as disclosed in Japanese Patent Application Laid-Open No. 2-167890, for example, are known. Are known.

[0004]

However, in the former method, there is a problem that the cost is increased due to an increase in the number of steps and cracking failure is caused by polishing.

In the latter method, the argon gas pressure is set to 12 mTorr or more and the substrate temperature is set to 100 to 250.
℃, nickel film stress is 3 × 10 ⁸ N / m ²
Although the effect can be obtained to some extent, when used industrially continuously in a single-wafer sputtering apparatus or the like, the temperature in the apparatus rises to 250 ° C. or more, and as a result, the nickel film stress increases, and the joining portion also increases. Will occur.

The present invention has been made in view of the above-mentioned problems, and does not increase the number of steps, such as forming irregularities of a specific shape on a Si substrate. It is an object of the present invention to provide a method for forming an electrode of a semiconductor device, which can increase the adhesion between a Si substrate and a metal electrode even if not intended.

[0007]

In order to achieve the above-mentioned object, an electrode forming method according to the present invention comprises a first step in which a native oxide film grown on the surface of a silicon substrate has a thickness of approximately 5 to 15 °. And a second step of forming a contact metal film which easily reacts with oxygen on the surface of the silicon substrate, and a third step of forming a nickel film as a metal for adhesion on the contact metal film.

[0008]

[Operation and Effect] That is, as a result of repeated experiments and considerations by the present inventors, the present invention increases the adhesion by controlling the thickness of the natural oxide film grown on the surface of the Si substrate during electrode formation by sputtering. It is based on the finding that we can do it.

Normally, the native oxide film on the surface of the Si substrate is in a stable SiO ₂ state, but the Si—O bond on the surface of the Si substrate when the thickness is further reduced to 5 to 15 ° is the binding energy of Si atoms. Is not completely chemically shifted by the O atom. Therefore, when a metal for an ohmic contact that easily reacts with oxygen, for example, titanium (Ti) is deposited, a small amount of oxygen present on the surface of the Si substrate acts as an activator in the Ti deposition process. A strong bonding layer such as Si-
An O-Ti amorphous layer is easily formed.

As described above, by controlling the thickness of the natural oxide film grown on the surface of the Si substrate, an excellent effect that the adhesion between the Si substrate and the metal electrode can be increased can be obtained.

[0011]

FIG. 1 is a longitudinal sectional view showing a semiconductor device (DMOS element) to which an embodiment of the present invention is applied. Hereinafter, this embodiment will be described in accordance with the manufacturing process with reference to FIG. 3A to 3F schematically show the laminated metal electrodes manufactured according to the present embodiment in the order of the manufacturing process.

First, referring to FIG.
After forming a gate and a source region of a predetermined power MOS transistor on a silicon (Si) substrate 1 having a thickness of 600 μm and having a thickness of 600 μm (not shown), as shown in FIG. To form a pattern.
Next, as shown in FIG. 3C, for example, silicon nitride (SiN) is used as a passivation film for protecting the aluminum wiring 3.
The layer 5 is formed by a plasma CVD method or the like.

After the element components on the front side of the silicon substrate 1 are formed in this way, the substrate 1 is transported to the sputtering apparatus shown in FIG. Is formed. The sputtering device shown in FIG.
This is a DC parallel plate type magnetron sputtering apparatus manufactured by Arian (XM-8).
The sputtering is performed with the pressure of the argon (Ar) gas 21 supplied into the chamber 23 set to 7.5 mTorr. The Ar gas is supplied into the chamber 23 from the gas inlet 53 via the mass flow meter 51. Also, Ar
The gas pressure is determined by the supply amount of the Ar gas by the mass flow meter 51 and the degree of evacuation by a vacuum pump described later. In FIG. 2, the vacuum pump includes a rotary pump 55, a turbo pump 57, and a cryopump 59.
5, a rough evacuation is performed, a turbo pump 57 performs a middle evacuation and a vacuum evacuation of the lock chamber 61, and a cryopump 59 performs a main evacuation.

In FIG. 2, first, the transport 25
Then, the carry-in lock table 27 receives the wafer, and the carry-in lock table 27 subsequently performs a lowering operation to transfer the wafer to a shuttle (not shown). The shuttle is configured to be movable on the dotted line in FIG. 2, and first moves the received wafer onto the process table 29. In the station 13, the process table 2
A high-frequency power source is connected so that 9 has a low potential and the capture 31 side has a high potential (specifically, a ground potential). In this state, ionization is performed by performing sputtering at 20 W for 30 seconds. The Ar gas collides with the back surface of the silicon substrate 1 to etch the natural oxide film grown on the back surface by 10 °. As a result of this etching, the natural oxide film remains on the Si surface by about 10 ° (not shown). Note that the capture 31 is for collecting contaminants (such as a natural oxide film) on the silicon surface. In FIG. 2, reference numeral 33 denotes a magnet for storing discharge.

Next, the wafer is moved to the station 15 by the shuttle and placed on the process table 35. In this station 15, a DC power supply is connected so that the process table 35 has a high potential (specifically, a ground potential) and the target 37 containing titanium (Ti) has a low potential. 2KW, 7
Ar gas ionized by sputtering under the condition of 5 seconds collides with the target 37, and Ti atoms jumping out of the target 37 are deposited on the silicon substrate 1 via the above-described natural oxide film, and have a thickness of about 2500 °. T
An i film 7 is formed. During this deposition, an interface between the silicon substrate 1 and the Ti film 7 is formed as shown in FIG.
An amorphous layer 8 of i-oxygen (O) -Ti is formed.

Next, the wafer is moved to the station 17 by the shuttle and placed on the process table 39. In this station 17, the station 15
Similarly to the above, a direct current is connected such that the process table 39 has a high potential and the target 41 containing nickel (Ni) has a low potential. In this state, Ar gas ionized by performing sputtering under the conditions of 1 KW and 240 seconds collides with the target 41, and the Ni atoms that have jumped out of the target 41 are converted into the above-mentioned T atoms.
Deposited on the i-film 7 and about 6000 as shown in FIG.
A Ni film 9 having a thickness of Å is formed.

Then, the wafer is moved to the station 19 by the shuttle and placed on the process table 43. Similarly, in the station 19, a DC power supply is connected so that the process table 43 has a high potential and the target 45 containing gold (Au) has a low potential. Then, sputtering is performed in this state at 0.5 KW for 12 seconds, so that A
U atoms are deposited, and an Au film 11 having a thickness of about 500 ° is formed as shown in FIG.

As described above, Ti,
The wafer on which Ni and Au are sequentially formed is transferred to the carry-out lock table 47 by the shuttle, and further, the carry-out lock table performs an ascending operation, thereby causing the transport 49 to move.
And the semiconductor device shown in FIG. 1 is manufactured.

Although the detailed structure of the power MOS transistor has been omitted in the above description, the structure may be a known DMOS structure, or may be a bipolar element, a diode, or the like.

Next, the mechanism of the adhesion between Si and Ti in the structure shown in FIG. 1 manufactured according to the above manufacturing process will be described. FIG. 4 shows the thickness of the native oxide film on the silicon substrate left by Ar etching before depositing the Ti film in the step shown in FIG.
7 shows the relationship with the result of the peel test when the back electrode of u is formed. As is clear from FIG. 4, when the remaining native oxide film is 5 to 15 °, preferably 10 °, the Si—
No peeling between Tis occurred, and adhesion was strong. However, when the natural oxide film is not completely removed or etched (20 °), peeling has occurred.
This is because at this Si / Ti interface, titanium silicide is not formed unless the temperature is 550 ° C. or higher. However, in this embodiment, a very small amount of oxygen having high reactivity with silicon or titanium exists on the silicon surface. Is considered to act as an activator in the Ti deposition process, and to easily form a strong bonding layer and the amorphous layer 8 of Si—O—Ti at the interface even at a low temperature. However, when the natural oxide film thickness is about 20 ° or more, oxygen is strongly bonded to silicon, and it is considered that the reaction with titanium becomes difficult and the adhesion decreases.

This mechanism can be supported by the bonding state of oxygen according to the thickness of the natural oxide film grown on the silicon substrate. In the step shown in FIG. 3D, a natural oxide film is grown on the surface of the silicon substrate 1 by about 20 ° before Ar etching. FIG. 5 shows the result of an Auger analysis of the wafer surface before etching of the native oxide film. FIG. 5A shows the peak intensity profile in the depth direction, and FIG. 5B shows the relationship between the Auger electron kinetic energy and the peak intensity. Show. From FIG. 5, it can be seen that the native oxide film thickness is about 20 °, the Si Auger electrons show different binding energies depending on the bonding with O atoms, and the bonding state of Si—O is strong SiO _2. .

On the other hand, in the step shown in FIG. 3D, a natural oxide film on the surface of the silicon substrate 1 is etched by etching as shown in FIG.
When the angle is about 10 ° as shown in FIG.
As shown in the figure, the Auger electron of the Si atom has one sharp linear spectrum, and is not affected by the chemical bond with the O atom. That is, when the thickness of the natural oxide film is about 10 °, the bonding state of Si—O on the wafer surface is at a level of SiO _X at which silicon (Si) atoms are not chemically shifted by the bonding energy with oxygen (O) atoms. Can be considered.

Therefore, the native oxide film on the silicon
By leaving it at 15 °, preferably 10 °, O atoms on the Si substrate easily react with Si or Ti during the Ti deposition process to form an amorphous layer of Si—O—Ti, This will strengthen the bond.

In the above-described embodiment, an example in which the etching to make the natural oxide film about 10 ° is performed by reverse-sputtering the silicon surface has been described. Alternatively, for example, after wet etching with an HF solution, An oxide film of about 10 ° can be formed even by washing with pure water for 10 minutes and standing in the air for 2 hours, and it has been confirmed that a similar effect can be obtained even with a natural oxide film formed by this method.

In the above embodiment, the Ti layer 7 is formed to form an ohmic contact on the surface of the wafer. , Vanadium (V), zirconium (Zr) or aluminum (Al)
May be formed. The thickness of the Ti layer is 2
The angle is not limited to 500 ° but may be in the range of 1000 to 4000 °. Further, the thickness of the Ni layer is not limited to
It may be in the range of 0-10000 °.

Further, as shown in Japanese Patent Application Laid-Open No. 2-167890, the Ni film stress is 3 × 10 ⁸ N / m ² by precisely controlling the Ar pressure to 12 mTorr or more and the substrate temperature to a range of 100 to 250 ° C. It is considered that the effects of the present invention will be further improved by the following.

[Brief description of the drawings]

FIG. 1 is a longitudinal sectional view showing a semiconductor device (DMOS element) manufactured by applying an embodiment of the present invention.

FIG. 2 is a structural diagram of a sputtering apparatus used in one embodiment of the present invention.

FIGS. 3A to 3F are cross-sectional views schematically showing a laminated metal electrode manufactured according to an embodiment of the present invention in the order of manufacturing steps.

FIG. 4 is a characteristic diagram showing a relationship between a natural oxide film thickness on a wafer surface and a peeling area ratio between Ti and Si.

5A and 5B show the results of Auger analysis of the wafer surface before natural oxide film etching. FIG. 5A shows the peak intensity profile in the depth direction, and FIG. 5B shows the relationship between the Auger electron kinetic energy and the peak intensity. It is a characteristic diagram.

6A and 6B show results of an Auger analysis of a wafer surface when a natural oxide film is reduced to about 10 ° by etching. FIG. 6A shows a peak intensity profile in a depth direction, and FIG.
FIG. 4 is a characteristic diagram showing a relationship between Auger electron kinetic energy and peak intensity.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Silicon substrate 7 Ti film 8 Si-O-Ti amorphous layer 9 Ni film 11 Au film 21 Argon gas

Continuation of the front page (56) References JP-A-4-214467 (JP, A) JP-A-4-58561 (JP, A) JP-A-2-167890 (JP, A) JP-A-58-218116 (JP) JP-A-58-2023 (JP, A) JP-A-56-105631 (JP, A) JP-A-55-138832 (JP, A) JP-A-54-7683 (JP, A) 53-121571 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB name) H01L 21/283 H01L 21/28 301

Claims (3)

(57) [Claims] 1. A first step in which the thickness of a natural oxide film grown on a surface of a silicon substrate is in the range of approximately 5 to 15 °, and a second step of forming a contact metal film which easily reacts with oxygen on the surface of the silicon substrate. And a third step of forming a nickel film as a metal for adhesion on the contact metal film. 2. The method according to claim 1, further comprising a fourth step of forming a final electrode on the nickel film, following the third step. 3. The method according to claim 1, wherein the contact metal film is made of one of titanium, vanadium, chromium, aluminum, and zirconium.