JP2976458B2 - Filter circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention will be described in the following order.

A Field of application in industry B Outline of the invention C Conventional technology D Problems to be solved by the invention E Means to solve the problems (FIGS. 1, 4 and 6) F function (1) (FIGS. 4, 4 and 6) G Example (G1) Overall Configuration of DAT (FIG. 8) (G2) Filter Circuit of First Example (FIGS. 1 to 5) (G3) Second Example Example Filter Circuit (FIGS. 6 and 7) (G4) Other Embodiments H Effect of the Invention A Industrial Field of the Invention The present invention relates to a filter circuit, for example, obtained from a rotating head of a circuit head type digital audio tape recorder. This is suitable for application to a reproduced signal waveform equalization circuit.

B. Summary of the Invention The present invention provides a filter circuit including a plurality of integrators whose time constants change in accordance with the ratio of the supplied first and second currents. The first filter characteristic is obtained by adjusting one of the currents, and the second filter characteristic is obtained by changing one of the input first and second currents at the same ratio. And a second filter characteristic similar to the first filter characteristic on the frequency axis.

C Conventional Technology Conventionally, a rotating head type digital audio tape recorder (hereinafter, referred to as DAT) has been used as a magnetic recording / reproducing apparatus capable of recording audio signals at high density.

In this DAT, input audio data is recorded on a magnetic tape wound around a rotating drum at a predetermined winding angle using a rotating head arranged on a rotating drum, or recorded audio data recorded on a magnetic tape. Is reproduced using a rotating head.

D Problems to be Solved by the Invention By the way, generally, when a magnetic tape on which predetermined audio data is recorded is reproduced using a DAT format, the readout rate of a reproduction signal by a magnetic head can be basically set freely. it can.

Therefore, by switching the number of rotations of the drum while keeping the running speed of the magnetic tape constant, the relative speed of the magnetic tape and the rotating head is changed to the standard speed mode of 3.133 (m / sec) and 1.567 (m). / sec] can be reproduced at two types of read rates, that is, a half speed mode.

However, if it is attempted to equalize the waveforms of the reproduced signals reproduced at two kinds of read rates in order to correct the frequency characteristics, a filter circuit having filter characteristics corresponding to the respective read rates, that is, a waveform equalizer circuit , And the configuration of the reproducing system cannot be prevented from becoming complicated.

The present invention has been made in consideration of the above points, and selectively sets a first filter characteristic and a second filter characteristic similar to the first filter characteristic on the frequency axis with a simple configuration. It is intended to propose a filter circuit that can be used.

Means for Solving E Problem In order to solve such a problem, in the present invention, the ratio of the supplied first and second currents I _1A , I _1B and I _2A , I _2B
A plurality of integrators GA _A and GA _B whose time constants ω ₁ and ω ₂ change according to I _2A / I _1A and I _2B / I _1B are combined to obtain a filter characteristic determined by the time constants ω ₁ and ω ₂ as a whole. In the filter circuit 1 (10) having one of the first and second currents I _1A , I _1B or I _2A , I _2B input to the plurality of integration decisions GA _A and GA _B respectively, the first The filter characteristic T _F1 is obtained, and the first or second current I input to each of the plurality of integration decisions GA _A and GA _B is obtained.
_By changing one of _1A and I _1B or one of I _2A and I _2B at the same ratio, the second filter characteristic _TF2 was obtained.

F action First or second current I _1A , I _1B or
One of I _2A and I _2B is adjusted to obtain the first filter characteristic T _F1, and the input first or second current I _1A or I _1B or one of I _2A or I _2B is the same. By changing the ratio to obtain the second filter characteristic T _F2 ,
It is possible to obtain a second filter characteristic T _F2 to similar on a frequency axis with respect to the first filter characteristic T _F1.

G Example Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

(G1) Overall Configuration FIG. 8 of the DAT 20 shows the overall configuration of a rotary head type digital audio tape recorder (DAT) as a whole, the rotation of the desired audio signal AD _IN, AD _OUT drum 21
A magnetic tape wound around the rotating drum 21 at a predetermined angular interval using the rotating heads 22A and 22B provided above.
22 to be recorded and / or reproduced.

In this DAT 20, first, at the time of recording, an input audio signal AD _IN is input to an audio signal conversion circuit 24.

The audio signal conversion circuit 24 includes a low-pass filter and an analog digital conversion circuit as a recording processing system, converts an input audio signal AD _IN into digital data, and converts the input audio signal AD _IN into a digital signal processing circuit as input digital data DT _IN. Send to 25 recording processing systems.

The recording processing system of the digital signal processing circuit 25 temporarily converts the input digital data DT _IN into the input audio data DT.
The data is written into the memory circuit 26 having a RAM (random access memory) configuration as an _AD .

The recording processing system of the digital signal processing circuit 25 includes an error correction code generation circuit, an interleave processing circuit, an 8-10 modulation circuit, and the like. First, the input audio data DT _AD written in the memory circuit 26 is read. After the error correction code generation circuit reads out and generates the error correction parity, the error correction parity is written into the memory circuit 26.

Writing and reading process for the memory circuit 26 is selected by the address corresponding to the data interleave generated in all the interleave processing circuit, in this way, the input audio data DT _AD that parity for error correction is added 8 -10 Read by the modulation circuit.

8-10 modulation circuit, the input audio data DT _AD consisting of 8-bit data, rotating head 22A, and converts the 10 bit data suitable for magnetic recording by 22B, synchronizing signal,
Address signal, subcode signal, ATF (automatic track
following) Add a signal etc.

The recording processing system of the digital signal processing circuit 25 converts the recording data obtained in this way into a recording signal S _RECO
And sends it to the recording processing system of the recording / reproducing amplifying circuit 27.

The recording processing system of the recording / reproducing amplifying circuit 27 includes a recording signal amplifying circuit and a rotary transformer, amplifies an input recording signal S _RECO, and obtains an amplified recording signal S obtained as a result.
_REC1 is supplied to the rotary heads 22A and 22B on the rotary drum 21 via the rotary transformer, and thus the magnetic tape 23
The input audio signal AD _IN can be recorded in a predetermined recording track.

Here, in this DAT 20, on the basis of the operation data D _OPR input from the input / display circuit 28 to the system control circuit 29 of the microcomputer configuration is adapted to select control the recording operation or reproducing operation.

The input / display circuit 28 includes, for example, a micro computer having a key matrix as operation element input means, and a display panel having a liquid crystal display element as display means, and operates in response to operation of operation elements by a user. It outputs the data D _OPR and performs display on the display panel based on the display data D _DSP input from the system control circuit 29.

The system control circuit 29 also controls the mechanical control data D _MC , the signal processing control data D _CNT and the servo processing control based on the system information preset at the time of recording and the operation data D _OPR input from the input / display circuit 28. The data _DSB is generated and sent to the mechanical control circuit 30, the digital signal processing circuit 25, and the servo processing circuit 31, respectively.

In practice, the recording time of the servo processing circuit 31 based on the servo processing control data D _SB input from the system control circuit 29, the drum motor 32, capstan motor 33, the reel motor 34, respectively drum driving signal C _DR Sends the capstan drive signal C _CP and the reel drive signal C _RM to the rotating drum
21 is rotated at a predetermined number of rotations, and the magnetic tape 23 is rotated.
Is run at a predetermined speed.

At this time, the drum motor 32, the capstan motor
A drum phase signal PG _{DR, a} drum frequency signal FG _DR , a cap frequency signal FG _CP, and a reel frequency signal FG _RM are fed back to the servo processing circuit 31 from the 33 and the reel motor 34, respectively. A servo is formed.

The servo processing circuit 31 is supplied with an internal reference signal D _REF during recording from the digital signal processing circuit 25, and executes speed servo processing and / or phase servo processing based on the internal reference signal D _REF . Rotating head generated based on drum phase signal PG _DR and drum frequency signal FG _DR
22A, 22B switching reference signal SWP to digital signal processing circuit 2
Send 5

Further, the mechanical control circuit 30 based on the control data D _MC inputted from the system control circuit 29, the drive control of the tape Rohde queuing mechanism like a cassette Rohde queuing mechanism and the magnetic tape 23 of the DAT cassette, the mechanical based on the sensor information S _MC input from mechanical parts, generates mechanical information data D _SMC, and sends this to the system control circuit 28.

Here, in this DAT 20, during reproduction, the servo processing circuit 31 first, inside the time of reproduction which is supplied from the rotational speed and the digital signal processing circuit 25 in accordance with the servo processing control data D _SB input from the system control circuit 29 The drum motor 32 is rotationally driven with a phase synchronized with the reference signal D _REF to form a speed servo and a phase servo.

In this state, the reproduction signal _SPBO obtained from the rotary heads 22A and 22B is converted into a recording / reproduction amplification circuit 27 including a rotary transformer, a reproduction signal amplification circuit, a waveform equalization circuit, a binarization circuit, and the like.
Is supplied to the reproduction processing system of the digital signal processing circuit 25 and the tracking control circuit 35 through the reproduction processing system.

In the case of this DAT 20, the tracking control circuit 35
Tracking control according to the TF method is performed.

That is, the tracking control circuit 35 has a waveform equalization circuit for detecting a synchronization signal, and the input reproduction signal S
_The synchronization signal included in _PB1 is detected, and an ATF control signal C _ATF is generated according to the ATF signal obtained based on the timing of the synchronization signal obtained as a result, and is sent to the servo processing circuit 31.

As a result, the servo processing circuit 31 outputs the ATF control signal C _ATF
Accordingly, the ATF servo loop is formed so that the capstan motor 33 is driven and controlled, and thus the rotating heads 22A and 22B can accurately trace on the recording track of the magnetic tape 23.

In this way, when the recorded track on the magnetic tape 23 can be accurately reproduced, the digital signal processing circuit 25
The reproduction processing system starts reproduction processing for the input reproduction signal _SPB1 .

The reproduction processing system of the digital signal processing circuit 25 uses a PLL.
(Phase locked loop) clock recovery circuit, 10-
8 demodulation circuit, an error detecting and correcting circuit, de-interleave processing circuit is configured from the interpolation circuit and the like, first detects the reproduction clock included in the reproduced signal S _PB1 in clock reproduction circuit.

10-8 The demodulation circuit detects a synchronization signal in the reproduced signal S _PB1, based on the reproduction clock detected by the clock reproducing circuit, and 10-8 demodulates the 10 bit content of the reproduced signal S _PB1, the resulting the 8-bit data as reproduced audio data DT _AD to be written sequentially into the memory circuit 26.

In this way, error reproduced audio data DT _AD written into the memory circuit 26 is read out Te cowpea to the error detection and correction circuit, which detects the presence or absence of data error, using the error correction parity for the data error Performs correction processing, and stores the error-corrected data and the correction result in a memory circuit.
Write to 26.

In the writing and reading processing for the memory circuit 26, addresses corresponding to data deinterleaving generated by the deinterleaving processing circuit are all selected, and the interpolation circuit reads the reproduced audio data DT _AD after the error detection and correction processing, For the data for which the error could not be corrected by the interpolation circuit, an interpolation operation was performed by a method such as calculating the average value of the preceding and following data, and this was used as reproduction digital data DT _{OUT to} the reproduction processing system of the audio signal conversion circuit 24. Send out.

The playback processing system of the audio signal conversion processing 24 includes a digital-to-analog conversion circuit and a low-pass filter, converts the playback digital data DT _OUT into an analog signal, and sends out the analog signal as a playback audio signal AD _OUT .

Thus, the recording track of the magnetic tape 23 is read out by the rotating heads 22A and 22B on the rotating drum 21 and the magnetic tape 23
Playback the recorded data recorded on the
AD _OUT is made to get.

(G2) Filter Circuit of First Embodiment In FIG. 1, reference numeral 1 denotes a filter circuit constituting a waveform equalizing circuit included in the recording / reproducing amplifying circuit 27, which _converts a waveform of an inputted amplified / reproduced signal _SPB10 into a predetermined waveform. An equalized reproduction signal _SPB11 is output after filtering based on filter characteristics.

Note that the amplified reproduction signal _SPB10 is _supplied to the rotating _heads 22A and 22A.
The reproduced signal S _PB0 read from the magnetic tape 23 using B
Is input to the reproduction processing system of the recording / reproduction amplification circuit 27, and is amplified through the reproduction signal amplification circuit.

Also, in this filter circuit 1, the amplified reproduction signal
_While the frequency band of the _SPB10 has a reading rate of 9.4 [MHz] in the standard speed mode and a reading rate of 4.7 [MHz] which is 1/2 times as high in the reading rate in the half speed mode, the amplified reproduction signal _{SPB10 has} Utilizing the fact that the frequency characteristic has a similar characteristic of about 1/2 times on the frequency axis, depending on whether the read rate of the input amplified reproduction signal _SPB10 is the standard speed mode or the half speed mode, Switching control of the current generating circuit 2 is performed, whereby the first filter characteristic in the standard speed mode is reduced to about 1/2 on the frequency axis in the half speed mode.
It is designed to obtain a second filter characteristic which is similar to the double filter characteristic.

Here, this filter circuit 1 is disposed on one integrated circuit as a whole, and is called a so-called Gilbert amplifier (US Pat.
3,676,789) using a state variable circuit formed by combining two integrators GA _A and GA _B.

Thereby, each of the integrators GA _A and GA _B
And second currents I _1A and I _2A , I _1B and I _2B
Is controlled separately, the time constant ω of each integrator GA _A and GA _B
1 and ω ₂ can be set arbitrarily, thus obtaining desired filter characteristics as a whole.

The Gilbert amplifiers constituting each of the integrators GA _A and GA _B have a connection configuration as shown in FIG.

That is, in this Gilbert amplifier GA, input voltages v ₊ and the inverting input voltage v _-, respectively current source IS ₁₁ and IS ₁₂ with the emitter constitutes a first differential amplifier circuit is connected via a resistor R Are supplied to the respective bases of the first and second NPN transistors Q1 and Q2 to which the first currents I ₁₁ and I ₁₂ are supplied.

The collectors of the first and second transistors Q1 and Q2 have their bases connected in common, a reference voltage V _REF is applied, and the third and fourth collectors have their collectors connected to a power supply V _CC .
Of the NPN transistors Q3 and Q4.

Thus, the collectors of the first and second transistors Q1 and Q2 are held to a predetermined voltage, the result respectively input voltages v ₊ and the inverting input voltage v _- first and second collector current obtained according to the, A second differential amplifier circuit is connected to a commonly connected emitter through a current source IS ₂ to supply a second current I 2
Fifth and sixth NPN transistors Q5 to which ₂ is supplied and
Supplied to each base in Q6.

The collector of the fifth and sixth transistors Q5 and Q6, each emitter is connected to the power source V _CC, seventh and 8 PNP type transistor Q7 and Q, which are current-mirror-connected
8 and maintained at a constant current, so that the collector current of the sixth transistor Q6 is
It is supplied to the base of N-type transistor Q9.

The base of the ninth NPN transistor Q9, in addition to this, the input voltage v _c is applied through capacitor C, also a collector is connected to a power supply V _CC, a through current source IS ₃ to emitter Three currents I ₃ are supplied,
Accordingly emitter voltage is output as the output voltage v _0.

Thus, in the Gilbert amplifier GA, input voltage v _+, the inverting input voltage v _- the input voltage v _c inputted through and capacitor C, between the output voltage v _0, the following equation using the transfer function s Have represented relationship in, when the ground voltage v _c input via the capacitor C (1) equation, the following equation Thus, as shown in FIG. 3, an integrator can be configured using a Gilbert amplifier GA.

Note that this integrator GA is expressed by the following equation. As represented by the first and second current sources IS ₁ (IS ₁₁ , I
S ₁₂ ) and the ratio of the first and second currents I ₁ (I ₁₁ , I ₁₂ ) and I ₂ respectively supplied to the first and second differential amplifier circuits of the Gilbert amplifier GA through IS _2. It has a proportional time constant ω.

This makes it possible to realize a filter circuit consisting of a state variable circuit that obtains desired filter characteristics by combining a plurality of the integrators GA. Further, by changing the time constant ω of each integrator at the same ratio, similarity can be obtained on the frequency axis. Filter characteristics can be obtained.

In the case of this embodiment, the current generating circuit 2 is connected to the first differential amplifier circuit of each of the first and second integrators GA _A and GA _B by the first.
Constant power supplies 3 and 4 for supplying currents I _1A and I _1B of
And semi-fixed current sources 5 and 6 for supplying second currents I _2A and I _2B to the respective second differential amplifier circuits of the second integrators GA _A and GA _B
Is configured.

Thus, the first and second integrators GA _A and GA _B are respectively And In a constant omega ₁ and omega ₂ when represented, thereby, to control the semi-fixed current sources 5 and 6, respectively, the first current I
With respect to the current value of _1A and I _1B, by setting the current value of the second current I _2A and I _2B, as indicated by the solid line in Figure 4, so as to obtain a first filter characteristic T _F1 as a whole It has been done.

Further, the current generating circuit 2 controls the internal reference power supply 7 of the semi-fixed current sources 5 and 6 based on a control signal CNT input from the outside, so that the second currents I _2A and I _2B
Of the first and second integrators GA _A and G based on the equations (4) and (5).
The time constants ω ₁ and ω ₂ of A _B are each switched by a factor of _two , and thus, as shown by the broken line in FIG. 4, the first filter characteristic T _F1 as a whole is / 2-fold have been made to obtain a second filter characteristic T _F2 to similar with.

Here, in the case of this embodiment, the current generating circuit 2 has an integrated circuit configuration, and is entirely composed of a transistor circuit shown in FIG.

That is, in the current generation circuit 2, the constant current source 3
And 4 comprise a pair of NPN transistors Q10 and Q11 which are current mirror connected and whose emitters are connected to the ground GND.

The collector of the transistor Q10 of the one is connected to a power supply V _CC through a resistor R1, the collector current flowing from the power source V _CC through resistor R1, is folded to the collector of the other transistors Q11, the collector current first current I _1A
And I _1B are sent to the first and second integrators GA _A and GA _B.

The collectors of the semi-fixed current sources 5 and 6 have the power supply V _CC.
Is connected to one end power V _CC connected to a predetermined current I _X voltage through the other end of the resistor R2 flows V _X (= I _X × R
2) is applied to the base, and the emitter is connected to the ground GND through the current source IS.
And two pairs of NPN-type transistors Q15, Q16, Q17 and Q17 each having a current mirror connection and an emitter connected to the ground GND of PNP-type transistors Q13 and Q14 whose respective bases are commonly connected to the emitter of the transistor Q12.
It consists of Q18.

The emitters of the transistors Q13 and Q14 are connected to the power supply V _CC through semi-fixed resistors VR1 and VR2, respectively, so that the collectors of the transistors Q13 and Q14 have the following equation. And the following equation And the collector currents I _CQ13 and I _CQ14 are generated, and this is one of the current mirror connected transistors
Q15 and Q17 are turned back, so that the collector current obtained in the other transistors Q16 and Q18 is equal to the second current.
The signals are sent to the first and second integrators GA _A and GA _B as I _2A and I _2B .

In this current generation circuit 2, the above-described resistor R2
Constitutes a part of the internal reference power supply 7, and is generated by controlling the current _IX flowing through the resistor R2 to 1/2 according to the logic level of the control signal CNT input to the control terminal CA. Voltage V
_{X is} also controlled by 1/2, so that the second currents I _2A and I _2B supplied to the first and second integrators GA _A and GA _B are both reduced by 1 /.
It is made to be able to control twice.

That is, the resistor R2 is connected to the base of the transistor Q12, and is connected to the two current mirror-connected NPs.
It is connected to the collector of one of the transistors Q19 and Q21 of the N-type transistor pair Q19 and Q20, Q21 and Q22.

The collectors of the other transistors Q20 and Q22 are connected to the power supply V _CC through resistors R3 and R4 having the same value, whereby the respective collector currents I _X1 and I _{X2 obtained} are folded back, and the collector currents of the transistors Q19 and Q21 are turned off. the resulting, in accordance connexion resistor R2, current flows I _X made by the following formula _{I X = I X1 + I X2} = 2I X1 ...... (8).

The collector and emitter of the transistor Q22 are:
The collector and the emitter of the switching NPN transistor Q23 to which the control signal CNT is given through the control terminal CA are connected to the base, respectively.

As a result, when the control signal CNT is at the logic “L” level, the transistor Q23 is controlled to the off state, and the resistance R2
The current I _X described above for (8) flows in, when reverse to the control signal CNT is logic "H" level, the transistor Q23 is controlled to the ON state, the current I _X2 generated by resistor R4 transistor Q23 Flow to ground GND through
A current that is 1/2 times the current _IX in equation (8) flows through the resistor R2.

Thus, the control signal CNT input to the control terminal CA
Depending on the logic level of, by controlling the current I _X to 1/2 flowing through the resistor R2, also the voltage V _X generated by the resistor R2 1 /
Can be controlled by a factor of two, so that the first and second integrating GA _A
, And the second currents I _2A and I _2B supplied to GA _B can both be controlled by a factor of two.

Thus, in this filter circuit 1, the control signal
CNT is set to the logic “L” level to set the first filter characteristic T
By selecting the _F1, the amplified reproduction signal S _{PB 10} obtained by reading rate in standard speed mode, it is possible to output an equalized reproduced signal S _PB11 by effectively filtering, also the control signal CNT to the opposite is set to a logic "H" level, by selecting the second filter characteristic T _F2,
Equalizing reproduced by effectively filtering the amplified reproduced signal S _{PB 10} obtained by reading rate by half speed mode signal S _PB11
Can be output.

According to the above configuration, the first and second currents I _1A , I _1B and I _1B input to the two integrators GA _A and GA _B respectively.
With the first currents I _1A and I _1B of I _2B and I _2B fixed,
The second currents I _2A and I _2B are adjusted to obtain a desired first filter characteristic T _F1, and the second currents I _2A and I 2 which are input respectively.
_By changing the _2B by 1/2 at the same ratio to obtain the second filter characteristic T _F2 , it is similar to the first filter characteristic T _F1 by 1/2 on the frequency axis. The second filter characteristic T _F3 can be obtained.

Per nuclear, by selecting the first filter characteristic T _F1 or second filter characteristic T _F2 with a control signal CNT, the read rate is in any case of the standard speed mode or half speed mode, amplified reproduced signal the filter circuit 1 can be realized capable of outputting an equalized reproduced signal S _PB11 by effectively filtering the S _{PB 10.}

(G3) Filter Circuit of Second Embodiment In FIG. 6, in which parts corresponding to those in FIG. 1 are assigned the same reference numerals, reference numeral 10 denotes a filter circuit constituting a waveform equalizing circuit included in the recording / reproducing amplifying circuit 27. A second embodiment will be described.

In the case of this embodiment, the current generating circuit 11
Integrators GA _A and GA first current I _1A and I _1B the constant current source 3 and 4 for supplying to _B, first and second integrators GA _A and GA _B of
And semi-fixed current sources 5 and 6 for supplying the second currents _I2A and _I2B to the first and second current sources.

Accordingly, the first and second integrators GA _A and GA _B provide the time constant ω described above with respect to equations (4) and (5), respectively.
Has a ₁ and omega _2, thereby, the first current I _1A and I _1B
By setting the current values of the second currents I _2A and I _2B respectively, the first filter characteristic T _F1 is obtained as a whole as shown by the solid line in FIG.

The current generating circuit 11 controls the internal current sources 12 of the current sources 3 and 4 that supply the first currents I _1A and I _1B based on a control signal CNT input from the outside,
The current values of the first currents I _1A and I _1B are controlled to be doubled.

As a result, based on the equations (4) and (5), the first
And the time constants ω ₁ and ω ₂ of the second integrators GA _A and GA _B ,
Each can be switched to 1/2, thus, as indicated by a broken line in FIG. 4, first to the first filter characteristic T _F1 as a whole, be similar at approximately 1/2 on the frequency axis 2
The filter characteristic T _F2 is obtained.

Here, in the case of this embodiment, the current generating circuit 11 has an integrated circuit configuration, and is entirely composed of a transistor circuit shown in FIG.

That is, in this current generating circuit 11, the semi-fixed current sources 5 and 6 are two mirror-connected NPN transistor pairs each having an emitter connected to the ground GND.
It consists of Q35 and Q36, Q37 and Q38.

Of these two transistor pairs Q35 and Q36, Q37 and 38, the collectors of one of the transistors Q35 and Q37 are connected to an external power supply V _CC through semi-fixed resistors VR10 and VR11, respectively.
It is connected to the.

This allows the power supply V _CC through the semi-fixed resistors VR10 and VR11.
Collector current flowing from and folded back to the collector of the other transistor Q36 and Q38, as the collector current obtained as a result the second current I _2A and I _2B, respectively, first
And the second integrators GA _A and GA _B.

Further, in the current generating circuit 11, the constant current sources 3 and 4 are two sets of NPN type transistors Q30 and Q3, each of which is connected to a current mirror and whose emitter is connected to the ground GND.
1, Q32 and Q33.

Of the two transistor pairs Q30 and Q31, Q32 and Q33, the collectors of one of the transistors Q30 and Q31 are connected to the power supply V _CC through resistors R10 and R11 having the same resistance.

As a result, the collector currents I _X10 and I _X20 flowing from the power supply V _CC through the resistors R10 and R11 are connected to the other transistor Q31.
And the collector current of Q33, and this collector current is added and sent to the first and second integrators GA _A and GA _B as first currents I _1A and I _1B , respectively.

In addition, the collector and the emitter of the transistor Q32 include:
The collector and the emitter of the switching NPN transistor Q34 to which the control signal CNT is given through the control terminal CA are connected to the base, respectively.

As a result, when the control signal CNT is at the logic "H" level, the transistor Q34 is controlled to the on state, and the current _IX20 generated by the resistor R11 is grounded through the transistor Q34.
By flowing to ND, the collector current _IX10 determined by the resistor R10 is sent out as the first currents _I1A and _I1B .

Conversely, when the control signal CNT is at the logic "L" level, the transistor Q34 is controlled to be in the off state, whereby the sum current of the currents _IX10 and _IX20 generated by the resistors R10 and R11, respectively (that is, (Which is twice the current value) are sent out as the first currents I _1A and I _1B .

Thus, the control signal CNT input to the control terminal CA
The current values of the first currents I _1A and I _1B can be controlled to be doubled in accordance with the logical level of.

Thus, in the filter circuit 10, the control signal
CNT is set to logic “H” level to set the first filter characteristic T
By selecting the _F1, the amplified reproduction signal S _{PB 10} obtained by reading rate in standard speed mode, it is possible to output an equalized reproduced signal S _PB11 by effectively filtering, also the control signal CNT to the opposite is set to a logic "L" level, by selecting the second filter characteristic T _F2,
Equalizing reproduced by effectively filtering the amplified reproduced signal S _{PB 10} obtained by reading rate by half speed mode signal S _PB11
Can be output.

According to the above configuration, the first and second currents I _1A , I _1B and I _2A , I _2A input to the two integrators GA _A , GA _B respectively.
_2B , while the first currents I _1A and I _1B are fixed, the second currents I _2A and I _2B are adjusted to obtain a desired first filter characteristic T _F1.
The resulting, also the first current I _1A to be inputted respectively, by which to obtain a second filter characteristic T _F2 is varied to 2 times in the same ratios I _1B, the first filter characteristic T _F1 On the other hand, the second filter characteristic T, which is similar to 1/2 on the frequency axis
You can get _F2 .

Thus, as in the first embodiment, the control signal CNT is
By selecting the first filter characteristic T _F1 or second filter characteristic T _F2 with the read rate is in any case of the standard speed mode or half speed mode, amplified reproduced signal
The filter circuit capable of outputting an equalized reproduced signal S _PB11 by effectively filtering the S _{PB 10} can be realized.

(G4) Other Embodiments (1) In the above-described embodiment, the case where the filter circuit is applied to a combination of two integrators has been described. However, the number of integrators is not limited to this, and is necessary. Depending on the case, three or more may be combined. In this case,
If the current value of one of the two currents supplied to each integrator is changed at the same ratio for all the integrators, the same effect as in the above-described embodiment can be realized.

(2) In the above embodiment, the first filter circuit
Although the second filter characteristic which is similar to the filter characteristic of 倍 on the frequency axis by 倍 times has been described, the present invention is not limited to this, and the current value to be changed as necessary Arbitrarily, various filter characteristics similar on the frequency axis can be obtained.

(3) In the above-described embodiment, the case where the present invention is applied to a rotary head type digital audio tape recorder has been described. The present invention can be widely applied to an equalizer circuit, and is not limited to a waveform equalizer circuit, but is preferably applied to various filter circuits.

H Effects of the Invention As described above, according to the present invention, one of the input first and second currents is adjusted to obtain the first filter characteristic, and the input first and second currents are adjusted. 2
Is changed at the same ratio to obtain the second filter characteristic, so that the second filter characteristic similar to the first filter characteristic on the frequency axis can be obtained with a simple configuration. A filter circuit can be realized.

In this way, it is possible to realize a filter circuit capable of effectively filtering and transmitting signal components having similar frequency characteristics on the frequency axis with a simple configuration.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of a filter circuit according to the present invention, FIG. 2 is a connection diagram showing a Gilbert amplifier constituting the integrator, and FIG. 3 is a schematic diagram used to explain the integrator. FIG. 4 is a characteristic curve diagram showing filter characteristics, FIG. 5 is a connection diagram showing a current generating circuit of the filter circuit of the first embodiment, FIG. 6 is a block diagram showing a second embodiment of the filter circuit, and FIG. FIG. 7 is a connection diagram showing the current generating circuit, and FIG.
FIG. 1 is a block diagram showing the entire configuration of a rotary head type digital audio tape recorder. 1, 10 ... filter circuit, 3, 4 ... constant current source, 5, 6
...... semi-fixed current source, 7 ...... internal reference power supply, 12 ...... internal reference current source, 20 ...... rotary head type digital audio tape recorder, 27 ...... reproducing amplifier, GA, GA _A, GA _B
... Integrator.

Claims (1)

(57) [Claims] 1. A filter circuit comprising a plurality of integrators whose time constants change in accordance with a ratio of supplied first and second currents, and having a filter characteristic determined by the time constant as a whole. One of the first or second current input to each of the integrators is adjusted to obtain a first filter characteristic, and one of the first or second current input to each of the plurality of integrators is adjusted. A filter circuit characterized in that a second filter characteristic is obtained by changing at the same ratio.