JP2973948B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a photodiode.

[0002]

2. Description of the Related Art FIGS.
This will be described with reference to FIG. 16 to 18 show a photodiode region.

[0003] First, referring to FIG.
^An N-type epitaxial layer 103 is formed on a-type single crystal silicon substrate 101. Next, a P ⁺ type diffusion layer 104 for insulation separation is formed. Next, referring to FIG. 16B, a thick silicon oxide layer 105 is formed in the field region by LOCOS. Next, an N ⁺ -type diffusion layer 106 as a cathode of the photodiode is formed. The N ⁺ type diffusion layer 106 is formed simultaneously with the formation of the collector (not shown) of the NPN transistor. Next, a thin silicon oxide layer 107 is formed by thermal oxidation. Next, using a photoresist pattern (not shown) as a mask, a P ⁺ type diffusion layer 108 as a light receiving portion of the photodiode is formed. Note that this P ⁺ type diffusion layer 108
Is formed simultaneously with the formation of the graft base (not shown) of the NPN transistor. Further, the silicon oxide layer 10
A silicon nitride layer 110 is formed on LP by LPCVD.

Next, referring to FIG. 16C, openings 111 a and 111 b are formed in the silicon nitride layer 110. Next, a photoresist pattern (not shown)
Is used as a mask, the silicon oxide layer 107 only at the opening 111b is removed by etching with hydrofluoric acid. Then, L
A polysilicon layer 112 (not shown) is formed on the entire surface by PCVD. Further, arsenic is ion-implanted into this polysilicon layer and annealed to form an N ⁺ type diffusion layer 11.
3a is formed. Note that this N ⁺ type diffusion layer 113a
It is formed simultaneously with the formation of the emitter (not shown) of the PN transistor. Next, the polysilicon layer 112 is etched by a dry etching method so that the polysilicon layer 112 as a part of the cathode electrode is formed only on the opening 111b.
Leave a.

Next, referring to FIG. 17A, the silicon oxide layer 107 on the opening 111a is removed by etching. Next, an aluminum layer is formed by a sputtering method, and thereafter, the aluminum layers 116a and 116b are selectively left by photolithography and dry etching to form an anode electrode and a cathode electrode of a photodiode.

Next, referring to FIG. 17B, a silicon nitride layer 117 is formed by a plasma CVD method.
Thereafter, a silica layer is applied, and the flat portion is etched back by an anisotropic dry etching method to leave the silica layer 118 only in the concave portion of the silicon nitride layer 117.

Next, referring to FIG. 18A, an aluminum layer is formed by a sputtering method, and is removed from the light receiving portion by a dry etching method to leave the aluminum layer 120.

Finally, referring to FIG. 18B, a silicon nitride layer is formed by a plasma CVD method, and is removed from the light receiving portion by a dry etching method to leave the silicon nitride layer 121 for a cover. Thus, an opening 122 serving as a light receiving unit is formed.

Thus, the silicon oxide layer 107 and the silicon nitride layer 110 remain in the opening 122 as an antireflection layer. That is, by optimizing the thickness of the anti-reflection layer, the light receiving portion (opening 1) of the photodiode can be obtained.
In 22), the reflectance of light from the surface of the silicon substrate is set to zero. Thus, loss due to reflection of light from the silicon substrate can be suppressed.

[0010]

However, in the above-described conventional method for manufacturing a semiconductor device, it is difficult to optimize the thickness of the anti-reflection layer, and as a result, the sensitivity of the photodiode is increased. There was a problem of variation. That is, when the silicon nitride layer 121 is etched, the silicon nitride layer 117 remains as shown in FIG. 19A, or the silicon nitride layer 110 is etched as shown in FIG. This is because that. Note that the silicon nitride layer 110 may be over-etched when the polysilicon layer 112 or the aluminum layer 116 is etched. The issues mentioned above
The present invention provides a semiconductor substrate of a first conductivity type.
A second conductivity type epitaxy opposite to the first conductivity type.
A first oxide layer on the epitaxial layer.
Is formed on the epitaxial layer below the first oxide layer.
Forming an impurity diffusion layer of the first conductivity type, and forming the impurity diffusion layer on the first oxide layer;
Forming a first nitrided layer, and forming a second acid on the first nitrided layer;
Forming a pattern of the oxide layer, and forming a pattern of the second oxide layer.
Forming a second nitride layer on the second pattern;
Selectively remove part of the nitride layer by dry etching
At the same time, the pattern of the second oxide layer partially remains in the thickness direction.
Forming an opening, and opening the second nitride layer as a mask.
The pattern of the remaining second oxide layer at the opening is wet-etched.
Making selective to the first nitrided layer by the ching method
It is .

[0011]

1 to 7 are sectional views showing a first embodiment of a method of manufacturing a semiconductor device according to the present invention. In the drawing, a region PD indicates a photodiode region, a region BIP indicates an NPN transistor region, and a region R indicates a polysilicon resistance region.

First, referring to FIG. 1A, FIG.
5 (A), a P having a specific resistance of about 10 to 50 Ω · cm.
^- the arsenic type single crystal silicon substrate 1 to form the N ⁺ -type buried diffusion layer 2 layer resistance about 20~40Ω / cm ² by ion implantation. Next, a specific resistance of about 1 Ω · cm on the silicon substrate 1,
An N-type epitaxial layer 3 having a thickness of about 2 to 5 μm is formed.
Next, a P ⁺ -type diffusion layer 4 having a layer resistance of about 10 to 50 Ω / cm ² for insulation separation is formed. Next, referring to FIG. 2B, similarly to FIG. 15B, L is added to the field area.
Silicon oxide layer 5 having a thickness of about 1 to 2 μm by the OCOS method
To form Next, the layer resistance of the cathode of the photodiode and the collector of the NPN transistor is about 10 to 10.
N ⁺ type diffusion layers 6a and 6b of 40Ω / cm ² are formed. Next, a silicon oxide layer 7 having a thickness of about 400 to 500 ° is formed by thermal oxidation. Then, acceleration energy about 20 ~
50 keV, dose amount about 1 × 10 ¹⁵ to 2 × 10 ¹⁵ / cm
^{In step 2} , boron is ion-implanted using a photoresist pattern (not shown) as a mask. Thereby, the P ⁺ -type diffusion layer 8a having a depth of about 0.4 to 0.8 μm as a light receiving portion of the photodiode and an NPN transistor graft base,
8b is formed. Furthermore, LPC is formed on the silicon oxide layer 7.
Approximately 700-800７００ silicon nitride layer 1 by VD method
0 is formed. Furthermore, acceleration energy about 20-50k
Boron is ion-implanted at eV and a dose of 5 × 10 ¹³ to 10 × 10 ¹³ / cm ² using a photoresist pattern (not shown) as a mask. Thus, a P-type diffusion layer 9 having a depth of about 0.3 to 0.5 μm as a base of the NPN transistor is formed.

Next, referring to FIG. 2A, FIG.
(C), an opening 11 is formed in the silicon nitride layer 10.
a, 11b, 11c, 11d, and 11e are formed. The openings 11a and 11b correspond to the anode and cathode of the photodiode, and the openings 11c, 11d and 11e.
Corresponds to the base, emitter and collector of the NPN transistor. Next, using the photoresist pattern (not shown) as a mask, the silicon oxide layer 7 only at the openings 11b, 11d, and 11e is removed by etching with hydrofluoric acid. Next, a thickness of about 100
A polysilicon layer 12 (not shown) of 0 to 2000 ° is formed. Further, an acceleration energy of about 60 to 80 keV and a dose of about 5 × 10 ¹⁵ to 2 × 10 ^{16 are} applied to the polysilicon layer.
Is ion-implanted and annealed at about 900 ° C. for about 30 to 60 minutes to form N ⁺ -type diffusion layers 13a, 13b and 13c having a depth of about 0.1 to 0.2 μm. Next, the polysilicon layer 12 is etched by a dry etching method to leave the polysilicon layers 12a, 12b, and 12c as the cathode electrode, the emitter electrode, and the collector electrode on the openings 11b, 11d, and 11e. Also, a polysilicon layer 12d as a polysilicon resistor is left.

Next, referring to FIG. 2B, the normal pressure C
A silicon oxide layer having a thickness of about 5000 .ANG. Is formed by the VD method, and is etched with hydrofluoric acid using a photoresist pattern (not shown) as a mask.
a and 14b are left. In this case, openings 15a and 15b for electrodes are formed in the silicon oxide layer 14b. At this time, the silicon oxide layer 7 on the openings 11a and 11c is also removed by etching at the same time.

Next, referring to FIG. 3A, an aluminum layer is formed by a sputtering method, and then selectively formed by an aluminum layer 16a, 16b, 16c, 16d, 16e, by photolithography and dry etching.
16f, 16g, leaving an anode electrode and a cathode electrode of a photodiode, a base electrode of an NPN transistor,
These are the emitter electrode, collector electrode, and polysilicon resistor electrode.

Next, referring to FIG. 3B, a silicon nitride layer 17 having a thickness of about 1 μm is formed by a plasma CVD method. Thereafter, a silica layer is applied, and the flat portion thereof is etched back by an anisotropic dry etching method so that the silica layer 18 remains only in the concave portion of the silicon nitride layer 17. Next, the silicon nitride layer 17 on the light receiving portion of the photodiode region SD is isotropically dry-etched by about 0.5 μm, and the rest is anisotropically dry-etched, thereby forming an opening 19a. At the same time, an opening (through hole) 19b is formed on the electrode 16g in the polysilicon resistance region R.

Next, referring to FIG. 4, an aluminum layer is formed by a sputtering method, and is removed from the light receiving portion by a dry etching method to leave the aluminum layer 20. At the same time, the aluminum layer 20 is also left in the polysilicon resistance region R.

Next, referring to FIG. 5, the thickness is about 0.5 μm.
An m silicon nitride layer 21 is formed by a plasma CVD method.

Next, referring to FIG. 6, the silicon nitride layer 21 in the photodiode region PD is selectively dry-etched to form an opening 22 serving as a light receiving portion. Finally, referring to FIG. 7, the remaining silicon oxide layer 14a
Is completely removed by etching with hydrofluoric acid.

As described above, only the silicon oxide layer 7 and the silicon nitride layer 10 completely remain in the opening 22 as an antireflection layer. That is, the silicon oxide layer 14a is provided as a buffer layer for over-etching when the aluminum layer 16, the silicon nitride layer 7, and the cover silicon nitride layer 21 are dry-etched. Finally, as shown in FIGS. The buffer layer is removed by wet etching. Therefore, the thickness of the silicon nitride layer 10 at the time of film formation can be finally left. That is, in other words, by optimizing the thicknesses of the silicon oxide layer 7 and the silicon nitride layer 10, the reflectance of light from the silicon substrate surface at the light receiving portion (opening 22) of the photodiode is made zero. Accordingly, loss due to reflection of light from the silicon substrate can be suppressed, and variation in sensitivity of the photodiode can be eliminated and high sensitivity can be maintained.

The sensitivity S of the photodiode means that light having a predetermined wavelength and a predetermined intensity is vertically incident on a light receiving portion of the photodiode under the condition that a predetermined reverse bias voltage is applied between the anode and the cathode of the photodiode. The photocurrent at the time of light incidence is defined as I, and the dark current at the time when no light is incident is I _0.
Then, it can be expressed by S = I / I ₀ . This sensitivity S is determined by the bulk and film structure of the light receiving part of the photodiode. Of these, the bulk of the light receiving section is determined by the concentration and depth of the other element such as the impurity diffusion layer of the bulk of the bipolar transistor. On the other hand, the film structure also depends on the other elements.
FIGS In the first embodiment shown in 7, the thickness d ₂ of the thick d ₁ and the silicon oxide layer 7 of silicon nitride layer 10
Is determined under the following conditions so that the reflectance becomes zero. ^{_{tan -1 (2πn 1 d 1 /}} λ) = n 1 2 (n S -n 0) (n 2 2 -n 0 n S) / (n 1 2 n S -n 2 2 n 0) (n 0 n ^{_{S -n 1 2) tan -1 (}} 2πn 2 d 2 / λ) = n 2 2 (n S -n 0) (n 1 2 -n 0 n S) / (n 1 2 n S -n 2 2 n ₀ ) (n ₀ n _S −n ₂ ² ) where n ₀ is the refractive index of an incident medium such as air, n _S is the refractive index of the semiconductor substrate 1 (N-type epitaxial layer 3), and n ₁ is the refractive index of the silicon nitride layer 10. , N ₂ is the refractive index of the silicon darkening layer 7 and λ is the wavelength of the vertically incident light. For example, n ₀ = 1,
If n _S = 3.44, n ₁ = 2.0, and n ₂ = 1.45, d ₁ = 722 d ₂ = 423Å.

Incidentally, in the first embodiment shown in FIGS. 1 to 7, when the polysilicon layer 12 is dry-etched, the silicon nitride layer 10 may be over-etched. Further, since the silicon oxide layer 14b remains in the polysilicon resistance region R, it cannot be made too thick due to its flatness. As a result, the thickness of the silicon oxide layer 14a cannot be increased, which may be insufficient as a buffer film.

8 to 15 are sectional views showing a second embodiment of the method for manufacturing a semiconductor device according to the present invention.

First, referring to FIG. 8A, FIG.
As in (A), arsenic is ion-implanted into the P ⁻ -type single-crystal silicon substrate 1 to form an N ⁺ -type buried diffusion layer 2. Next, an N-type epitaxial layer 3 is formed on the silicon substrate 1. Next, a P ⁺ type diffusion layer 4 for insulation separation is formed.

Next, referring to FIG. 8B, similarly to FIG. 2B, an oxide layer 5 is formed in the field region. Next, N ⁺ -type diffusion layers 6a and 6b as a cathode of the photodiode and a collector of the NPN transistor
To form Next, a silicon oxide layer 7 is formed. Next, P ⁺ -type diffusion layers 8a and 8b are formed as a light receiving portion of the photodiode and a graft base of the NPN transistor. Further, a silicon nitride layer 10 is formed on the silicon oxide layer 7. Further, a P-type diffusion layer 9 as a base of the NPN transistor is formed.

Next, referring to FIG. 9A, the normal pressure C
A silicon oxide layer 31 having a thickness of about 5000 ° is formed by the VD method, and portions other than the light receiving portion in the photodiode region PD are removed by etching with hydrofluoric acid using a photoresist pattern (not shown) as a mask.

Next, referring to FIG. 9B, similarly to FIG. 2A, an opening 11 is formed in the silicon nitride layer 10.
a, 11b, 11c, 11d, and 11e are formed. Next, the silicon oxide layer 7 only in the openings 11b, 11d and 11e is removed by etching with hydrofluoric acid. Then
A polysilicon layer is formed on the entire surface by the LPCVD method.
Further, arsenic is ion-implanted into the polysilicon layer and annealed to form N ⁺ -type diffusion layers 13a, 13b, 13b.
Form c. Next, the polysilicon layer 12 is etched by a dry etching method to open the openings 11b and 11b.
d, 11e, polysilicon layers 12a, 12b, 1 as part of a cathode electrode, an emitter electrode, and a collector electrode.
Leave 2c. Also, a polysilicon layer 12d as a polysilicon resistor is left.

Next, referring to FIG. 10A, FIG.
Similarly to (B), the thickness is about 5,000 by the atmospheric pressure CVD method.
Forming a silicon oxide layer of Å, etching with a photoresist pattern (not shown) as a mask with hydrofluoric acid,
Light receiving portion of photodiode and polysilicon resistor 12d
The silicon oxide layers 14a and 14b are left thereon. In this case, the electrode opening 15 is formed in the silicon oxide layer 14b.
a and 15b are formed. At this time, the opening 11
The silicon oxide layer 7 on a and 11c is also removed by etching at the same time.

Next, referring to FIG. 10B, FIG.
(A), an aluminum layer is formed, and then
Optionally, aluminum layers 16a, 16b, 16c, 16
Except for d, 16e, 16f, and 16g, the anode electrode and the cathode electrode of the photodiode, the base electrode, the emitter electrode, the collector electrode of the NPN transistor, and the electrode of the polysilicon resistor are used.

Next, referring to FIG. 11, FIG.
Is formed in the same manner as above. Thereafter, a silica layer is applied, and the flat portion thereof is etched back by an anisotropic dry etching method so that the silica layer 18 remains only in the concave portion of the silicon nitride layer 17. Next, the silicon nitride layer 17 on the light receiving portion in the photodiode region SD is isotropically dry-etched, and the rest is anisotropically dry-etched, thereby forming the opening 19a. At the same time, an opening (through hole) 19b is formed on the electrode 16g in the polysilicon resistance region R.

Next, referring to FIG. 12, similarly to FIG. 4, an aluminum layer is formed and removed from the light receiving portion by a dry etching method to leave the aluminum layer 20. At the same time, the aluminum layer 20 is also left in the polysilicon resistance region R.

Next, referring to FIG. 13, similarly to FIG. 5, a silicon nitride layer 21 is formed by a plasma CVD method.

Next, referring to FIG. 14, similarly to FIG. 6, the silicon nitride layer 21 in the photodiode region PD is selectively dry etched to form an opening 22 serving as a light receiving portion.
To form

Finally, referring to FIG. 15, similarly to FIG. 7, the remaining silicon oxide layer 31 and silicon oxide layer 1
4a is completely removed by etching with hydrofluoric acid.

As described above, in the second embodiment shown in FIGS. 8 to 15, the silicon oxide layer 31 is formed before the polysilicon layer 12 is dry-etched. It is possible to prevent the silicon nitride layer 10 from being thinned due to over-etching . Further, by stacking the silicon oxide layer 31 of the same thickness on the silicon oxide layer 14, the thickness becomes sufficient as a buffer film at the time of dry etching, and the thickness of the silicon nitride layer 10 is completely reduced. Can be prevented.

[0036]

As described above, according to the present invention, the variation in the sensitivity of the photodiode can be suppressed.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a first embodiment of a method for manufacturing a semiconductor device according to the present invention.

FIG. 2 is a sectional view showing a first embodiment of a method for manufacturing a semiconductor device according to the present invention.

FIG. 3 is a sectional view illustrating a first embodiment of a method for manufacturing a semiconductor device according to the present invention.

FIG. 4 is a sectional view showing a first embodiment of a method for manufacturing a semiconductor device according to the present invention.

FIG. 5 is a sectional view showing a first embodiment of a method for manufacturing a semiconductor device according to the present invention.

FIG. 6 is a sectional view showing a first embodiment of a method for manufacturing a semiconductor device according to the present invention.

FIG. 7 is a sectional view illustrating a first embodiment of a method for manufacturing a semiconductor device according to the present invention.

FIG. 8 is a sectional view showing a second embodiment of a method for manufacturing a semiconductor device according to the present invention.

FIG. 9 is a sectional view showing a second embodiment of a method for manufacturing a semiconductor device according to the present invention.

FIG. 10 is a sectional view showing a second embodiment of a method for manufacturing a semiconductor device according to the present invention.

FIG. 11 is a sectional view showing a second embodiment of a method for manufacturing a semiconductor device according to the present invention.

FIG. 12 is a sectional view showing a second embodiment of a method for manufacturing a semiconductor device according to the present invention.

FIG. 13 is a sectional view showing a second embodiment of the method for manufacturing a semiconductor device according to the present invention.

FIG. 14 is a sectional view showing a second embodiment of a method for manufacturing a semiconductor device according to the present invention.

FIG. 15 is a sectional view showing a second embodiment of a method for manufacturing a semiconductor device according to the present invention.

FIG. 16 is a cross-sectional view showing a conventional method for manufacturing a semiconductor device.

FIG. 17 is a cross-sectional view illustrating a method for manufacturing a conventional semiconductor device.

FIG. 18 is a cross-sectional view illustrating a conventional method for manufacturing a semiconductor device.

FIG. 19 is a cross-sectional view illustrating a problem.

[Explanation of symbols]

1─P ⁻ -type single crystal silicon substrate 2─N ⁺ -type buried diffusion layer 3─N-type epitaxial layer 4─P ⁺ -type diffusion layer 5─Silicon oxide layer 6a, 6b─N ⁺ -type diffusion layer 7─Silicon oxide layer 8a, 8b {P ⁺ type diffusion layer 9} P type diffusion layer 10 {silicon nitride layer 11a-11e} opening 12a, 12b, 12c {polysilicon layer 13a, 13b, 13c} N ⁺ type diffusion layer 14a, 14b Silicon oxide layer 15a, 15b {opening 16a-16g} aluminum layer 17 {silicon nitride layer 18} silica layer 19a, 19b {opening 20} aluminum layer 21 {silicon nitride layer 22} opening 31 {silicon oxide layer 101} P ⁻ type single crystal silicon substrate 103 ─N type epitaxial layer 104 ─P ⁺ type diffusion layer 105 ─silicon oxide layer 106 ─N ⁺ type diffusion layer 107 ─silicon oxide Layer 108 {P ⁺ type diffusion layer 110} Silicon nitride layer 111a, 111b {Opening 112a} Polysilicon layer 113a {N ⁺ type diffusion layer 116a, 116b} Aluminum layer 117 {Silicon nitride layer 118} Silica layer 120} Aluminum layer 121─ silicon nitride layer 122 opening

Claims (4)

(57) [Claims] Forming an epitaxial layer of a second conductivity type opposite to the first conductivity type on a semiconductor substrate of a first conductivity type; Forming a first oxide layer (7), forming the first conductivity type impurity diffusion layer (8a) in the epitaxial layer below the first oxide layer, and forming the first oxide layer. Forming a first nitride layer on the first nitride layer; and patterning a second oxide layer on the first nitride layer.
Forming at least a second nitride layer (17) on the pattern of the second oxide layer, and selecting a part of the second nitride layer on the pattern of the second oxide layer Removal by dry etching method
And the pattern of the second oxide layer is aligned in the thickness direction.
Forming an opening (19a) by leaving a portion of the second nitride layer as a mask;
The oxide layer pattern of the above by wet etching method
Selectively removing the first nitride layer . 2. forming a second conductive type epitaxial layer (3) opposite to the first conductive type on a first conductive type semiconductor substrate (1); Forming a first oxide layer (7), forming the first conductivity type impurity diffusion layer (8a) in the epitaxial layer below the first oxide layer, and forming the first oxide layer. Forming a first nitride layer on the first nitride layer; and patterning a second oxide layer on the first nitride layer.
Forming a first conductive layer pattern (16) outside the second oxide layer pattern; and forming a pattern on the first conductive layer pattern and the second oxide layer pattern. A second nitride layer (17) is formed, and a portion of the second nitride layer on the pattern of the second oxide layer is selectively removed by a dry etching method to form a first opening (19a). Forming a pattern of the second conductive layer outside the pattern of the second oxide layer; and forming a pattern of the second conductive layer and the second oxide layer. A third nitride layer (21) is formed on the pattern, and a part of the third nitride layer on the pattern of the second oxide layer is selectively removed by dry etching to form a second opening. Forming (22); and forming the first and second layers using the second and third nitride layers as masks.
Removing the pattern of the second oxide layer in the opening by a wet etching method. Forming a pattern of a third oxide layer after forming the first nitride layer; and forming a polysilicon layer on the pattern of the third oxide layer.
And selectively removing a portion of the polysilicon layer on the pattern of the third oxide layer by dry etching. The pattern of the second oxide layer is formed of the third oxide layer. 3. The method according to claim 1, wherein the semiconductor device is formed on a pattern of an oxide layer. 4. The thickness d ₁ of the first nitride layer and the thickness d ₂ of the first oxide layer are expressed by the following conditional expression: tan ⁻¹ (2πn ₁ d ₁ / λ) = n ₁ ² _{n S -n 0) (n 2} 2 -n
_{0 n S) / (n 1} 2 n S -n 2 2 n 0) (n 0 n S -n 1 2) tan -1 (2πn 2 d 2 / λ) = n 2 2 (n S -n 0) (n ₁ ² -n ₀ n
^{_{S) / (n 1 2 n}} S -n 2 2 n 0) (n 0 n S -n 2 2) However, n ₀ is the refractive index n _S of incident medium refraction of the semiconductor substrate and the N-type epitaxial layer 3. The method according to claim ₁ , wherein a refractive index n 1 satisfies a refractive index of the nitride layer, n ₂ satisfies a refractive index of the medium layer, and λ satisfies the wavelength of vertically incident light.