JP3506314B2 - Manufacturing method of integrated light receiving element - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing an integrated light receiving element in which a light receiving element section and a drive circuit section used in an optical disk device such as a compact disk are integrated in one chip.

[0002]

2. Description of the Related Art An integrated light receiving element in which a light receiving element section and a drive circuit section for driving the light receiving element section are integrated enables high-speed operation and improves the S / N (information signal / noise signal) ratio. It is being developed because it has the advantage of.

A conventional integrated light receiving element will be described below with reference to the drawings. FIG. 5 is a sectional view showing a conventional integrated light receiving element 16. First, the configuration of the conventional integrated light receiving element 16 will be described. Integrated light receiving element 1
Reference numeral 6 generally includes a light receiving element portion 3 formed on an n-type semiconductor substrate 2 made of Si, and a MOS transistor 4 connected to the light receiving element portion 3 to drive the light receiving element portion 3. The light-receiving element portion 3 has a light-receiving portion 3c, and a first light-receiving element 3a formed by forming a pn junction from the p-type first diffusion layer 5a in the n-type semiconductor substrate 2 and the n-type semiconductor substrate 2; The second light receiving element 3b is formed by forming a pn junction from the second type diffusion layer 5b and the n-type semiconductor substrate 2. Generally, a plurality of light-receiving elements are formed in the light-receiving element section 3, because when used in combination with a semiconductor laser element, control is performed so that the light output of the semiconductor laser element is always constant. Is. The MOS transistor 4 includes a p-type third diffusion layer 6 formed in the n-type semiconductor substrate 2, a p-type fourth diffusion layer 7, and between the p-type third diffusion layer 6 and the p-type fourth diffusion layer 7. And a gate 8 formed on the.

A thermal oxide film 9 is formed on the M0S transistor 4, the light receiving element section 3 and the n-type semiconductor substrate 2, and the light receiving element section 3 for separating the installation position of the M0S transistor 4 from the light receiving element section 3 is formed. An isolation oxide film 9a is formed between it and the MOS transistor 4. A gate polycrystalline silicon 10 used as a gate electrode is formed on the gate 8 via a thermal oxide film 9. Silicon nitride 12 is formed on the thermal oxide film 9 and the gate polycrystalline silicon 10. Furthermore, silicon nitride 12
Forms an antireflection film 13 together with the thermal oxide film 9 on the light receiving portion 3c. An antireflection film 1 is formed on the silicon nitride 12.
An interlayer insulating layer 11 having an opening is formed on the surface 3.

Next, the operation of the conventional integrated light receiving element 16 will be described. When light enters the light receiving element section 3 through the light receiving section 3c of the integrated light receiving element 16, the light receiving element section 3
The current generated by the photoelectric conversion in (1) is amplified by the MOS transistor 4 and output to an external circuit to operate. On this occasion,
The antireflection film 13 is formed to have an optimum thickness in order to improve photoelectric conversion efficiency of light incident on the light receiving element section 3.

Next, a method of manufacturing the integrated light receiving element 16 will be described. A thermal oxide film 9 is formed on the n-type semiconductor substrate 2 by the thermal oxidation method, and an isolation oxide film 9a for isolating each element such as a MOS transistor and a light receiving element in the depth direction.
To form. Then, the n-type semiconductor substrate 2 is formed by the diffusion method.
P-type diffusion is performed on the p-type first diffusion layer 5a and the p-type second diffusion layer 5b on one side separated by the isolation oxide film 9a.
Then, the p-type third diffusion layer 6 and the p-type fourth diffusion layer 7 are formed on the other side. A gate 8 is provided between the p-type third diffusion layer 6 and the p-type fourth diffusion layer 7. The light receiving element 3a is
It is composed of the p-type first diffusion layer 5a and the n-type semiconductor substrate 2, and p
The light-receiving element 3b has an n-junction, is composed of the p-type second diffusion layer 5b and the n-type semiconductor substrate 2, and is formed to have a pn-junction. Thus, the light receiving element portion 3 including the light receiving element portions 3a and 3b and having the light receiving portion 3c is formed on one side of the isolation oxide film 9a, and the p-type third diffusion layer 6 is formed on the other side. ,
The MOS transistor 4 including the p-type fourth diffusion layer 7 and the gate 8 is formed.

Next, after forming polycrystalline silicon on the thermal oxide film 9, the gate polycrystalline silicon 10 is formed on the thermal oxide film 9 corresponding to the gate 8 by using the photolithography method and the dry etching method. . After that, the silicon nitride 12 is formed on the thermal oxide film 9 and the gate polycrystalline silicon 10 by the CVD method. In the CVD method, generally, the film is formed by heating at a temperature of 200 ° C to 400 ° C. At this time, the thermal oxide film 9 and the silicon nitride 12 on the light receiving portion 3c form an antireflection film 13. Further, the interlayer insulating layer 11 is formed on the silicon nitride 12, and the interlayer insulating layer 11 corresponding to the light receiving section 3c is removed by using the photolithography method and the etching method to remove the integrated light receiving element 1 shown in FIG.
6 is obtained. The interlayer insulating layer 11 is a multilayer film including an oxide film (hereinafter, referred to as a CVD oxide film) manufactured by a CVD method and spin-on glass (Spin On Glass, hereinafter abbreviated as SOG).

[0008]

However, when the interlayer insulating layer 11 on the light receiving portion 3c is removed by etching,
When a wet etching method using hydrofluoric acid or the like is used, hydrofluoric acid permeates the SOG forming the interlayer insulating layer 11 to cause film peeling. Further, when the dry etching method is used, the selectivity between the CVD oxide film in the interlayer insulating layer 11 and the silicon nitride 12 is poor and the silicon nitride 12 is etched, so that the entire film of the antireflection film 13 is etched. The thickness could not be controlled. For this reason, the reflectance of the light incident on the light receiving portion 3c of the light receiving element portion 3 changes, causing a problem that the photoelectric conversion efficiency varies.

If the thermal oxide film 9 and the silicon nitride 12 on the light receiving portion 3c are formed thick so that the thickness of the antireflection film 13 does not become too thin, the heat applied when forming these layers. As a result, the gate polycrystalline silicon 10 was oxidized and the effective gate length was shortened. Further, since the silicon nitride 12 is formed on the gate polycrystalline silicon 10, the plasma is used for etching in the dry etching method, so that the heat of the lower portion of the gate polycrystalline silicon 10 damaged by the plasma is heated. It was not possible to carry out hydrogen treatment to reduce traps and interface states in the oxide film. The present invention has been made in order to solve such a problem, and an object of the present invention is to provide a method for manufacturing an integrated light receiving element which does not deteriorate the characteristics of a MOS transistor and has good photoelectric conversion efficiency.

[0010]

In a method of manufacturing an integrated light receiving element according to the present invention, the first invention is that a light receiving element portion having a light receiving portion and a circuit driving portion having a gate are integrated on a semiconductor substrate. In the method of manufacturing the integrated light receiving element,
Forming a thermal oxide film on the light receiving portion and the circuit driving portion; forming polycrystalline silicon on the thermal oxide film; and etching the polycrystalline silicon other than the light receiving portion and the gate portion. A step of forming an interlayer insulating film on the polycrystalline silicon and the thermal oxide film, and etching the interlayer insulating layer on the light receiving portion down to the polycrystalline silicon, and removing the polycrystalline silicon from the thermal oxide film. Etching step, performing hydrogen treatment on the interlayer insulating layer and the thermal oxide film to recover damage caused by the etching, and forming an insulating layer on the interlayer insulating layer and the thermal oxide film, And a step of forming an antireflection film including the thermal oxide film and the insulating layer on the light receiving portion.

According to a second aspect of the present invention, in the method of manufacturing an integrated light receiving element according to the first aspect, the etching is dry etching.

[0012]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below.
This will be described with reference to FIGS. 1 to 4. The same components as those of the conventional example are designated by the same reference numerals and the description thereof will be omitted. FIG. 1 is a sectional view showing an integrated light receiving element of the present invention. 2 to 4 are cross-sectional views showing the steps of the method for manufacturing the integrated light receiving element of the present invention. The structure of the integrated light receiving element 1 of the present invention is the same as the conventional integrated light receiving element 16 except that the silicon nitride 12 is the thermal oxide film 9 and the interlayer insulating layer 11 on the light receiving portion 3c.
It is formed above.

First, the structure of the integrated light receiving element 1 of the present invention will be described. The integrated light-receiving element 1 generally includes an n-type semiconductor substrate 2 made of Si, a light-receiving element portion 3 formed on the n-type semiconductor substrate 2, and an MO for driving the light-receiving element portion 3.
It is composed of an S-transistor 4. Light receiving element section 3
Includes a light receiving portion 3c, a first light receiving element portion 3a having a p-type first diffusion layer 5a on the n-type semiconductor substrate 2 and a pn junction formed by the n-type semiconductor substrate 2, and a p-type second diffusion layer 5b and n. The second semiconductor light receiving element portion 3b having a pn junction is formed by the type semiconductor substrate 2. In general, a plurality of light receiving element portions are formed in the light receiving element portion 3. When the light receiving element portion 3 is used in combination with the semiconductor laser element, it controls so that the light output of the semiconductor laser element is always constant. This is because. The MOS transistor 4 includes a p-type third diffusion layer 6 formed on the n-type semiconductor substrate 2, a p-type fourth diffusion layer 7, and a space between the p-type third diffusion layer 6 and the p-type fourth diffusion layer 7. And the gate 8 formed.

The thermal oxide film 9 is formed on the M0S transistor 4, the light receiving portion 3c and the n-type semiconductor substrate 2, and the isolation oxide film 9a is provided between the light receiving element portion 3 and the MOS transistor 4.
Is formed. A gate polycrystalline silicon 10 is formed on the gate 8 as a gate electrode via a thermal oxide film 9. Further, the thermal oxide film 9 and the gate polycrystalline silicon 1
0, the interlayer insulating layer 1 having an opening on the light receiving portion 3c.
1 is formed, and silicon nitride 12 is formed on the interlayer insulating layer 11 and the thermal oxide film 9 on the light receiving portion 3c. This silicon nitride 12 is formed at 200 ° C. to 400 ° C. by the CVD method.
CVD oxide film produced by heating to a temperature of ℃ or this C
It may be a multi-layer film of VD oxide film and silicon nitride. In this way, the silicon nitride 12 forms the antireflection film 13 together with the thermal oxide film 9 on the light receiving portion 3c. here,
The wiring of the light receiving element portion 3 and the MOS transistor 4 and the surface protective film formed on the interlayer insulating layer 11 are omitted.

Next, the operation of the integrated light receiving element 1 of the present invention will be described. When light is incident on the light receiving portion 3c of the light receiving element portion 3, the voltage generated by photoelectric conversion in the light receiving element portion 3 is M
It is amplified by the OS transistor 4 and output to an external circuit for operation. At this time, the antireflection film 13 is formed to have an optimum thickness in order to improve the photoelectric conversion efficiency of the light incident on the light receiving section 3c of the light receiving element section 3.

Next, a method of manufacturing the integrated light receiving element of the present invention will be described with reference to FIGS. (First step) As shown in FIG. 2, in order to form a thermal oxide film 9 on the n-type semiconductor substrate 2 by a thermal oxidation method and isolate each element such as a MOS transistor and a light receiving element in the depth direction. Forming an isolation oxide film 9a. Then, p-type diffusion is performed on the n-type semiconductor substrate 2 by a diffusion method, and the p-type first diffusion layer 5a is formed on one side separated by the isolation oxide film 9a.
After the p-type second diffusion layer 5b is formed, the p-type third diffusion layer 6 and the p-type fourth diffusion layer 7 are formed on the other side. p-type 3rd
A gate 8 is provided between the diffusion layer 6 and the p-type fourth diffusion layer 7. In the embodiment of the present invention, the p-type first diffusion layer 5a and the p-type second diffusion layer 5b are formed, and then the p-type third diffusion layer 6 and the p-type fourth diffusion layer 7 are formed. The reverse procedure is also acceptable. Further, the p-type first diffusion layer 5a, the p-type second diffusion layer 5b, the p-type third diffusion layer 6 and the p-type second diffusion layer 7 may be simultaneously formed. Thus, the light receiving element portion 3 including the light receiving element portions 3a and 3b and having the light receiving portion 3c is formed on one side of the isolation oxide film 9a, and the p-type third diffusion layer 6 is formed on the other side. ,
The MOS transistor 4 including the p-type fourth diffusion layer 7 and the gate 8 is formed. Since the thermal oxidation method can control the film thickness on the order of submicron, the thickness of the thermal oxide film 9 can be accurately manufactured.

Further, polycrystalline silicon 14 is formed on the thermal oxide film 9 by the CVD method. After that, the portions other than the portions corresponding to the light receiving element portion 3 and the gate 8 are removed by etching using the photolithography method and the dry etching method, and the polycrystalline silicon 1 is formed in the portion corresponding to the light receiving portion 3c.
Gate polycrystalline silicon 1 in the portion corresponding to 4 and gate 8
Try to leave 0. Further, an interlayer insulating film 11 made of SiO ₂ or silicon nitride is formed on the thermal oxide film 9, the polycrystalline silicon 14 and the gate polycrystalline silicon 10. Thereafter, a photoresist pattern 15 having an opening 15a is formed on the interlayer insulating film 10 corresponding to the polycrystalline silicon 13 on the light receiving element 3 by using the photolithography method.

(Second Step) Next, as shown in FIG. 3, a photoresist pattern 1 is formed by using a dry etching method.
The interlayer insulating layer 11 exposed from the opening 15a of No. 5 is plasma-etched up to the polycrystalline silicon 14. In this dry etching, the n-type semiconductor substrate 2 having the interlayer insulating layer 11 formed therein is introduced into a chamber of a dry etching apparatus (not shown), and a vacuum of 10 ^{−6 to} 10 ⁻⁷ Torr is applied. A mixed gas of ₄ or CHF ₃ is introduced, a vacuum of 0.2 Torr is applied, a high frequency voltage of 500 W is applied, and plasma of CF ₄ or CHF ₃ gas is used. Here, Ar gas is introduced to keep the gas pressure in the chamber constant. When the interlayer insulating layer 11 is etched, since the etching rate of the polycrystalline silicon 14 is significantly slower than that of the interlayer insulating layer 11,
The etching stops at the polycrystalline silicon 14. Therefore, the polycrystalline silicon 14 is not etched, but only the interlayer insulating layer 11 is etched.

(Third step) Subsequently, as shown in FIG.
First, using a dry etching method, polycrystalline silicon 14
Plasma etching to the thermal oxide film 9
The con 14 is removed. The dry etching at this time is
Not shown is the polycrystalline etching chamber in the dry etching chamber.
1 is introduced by introducing the n-type semiconductor substrate 2 on which the recon 14 is formed.
0^-6Through 10 ^-7After applying a high vacuum of Torr, N₂With
BCl₃Or Cl₂0.1T after introducing the mixed gas of
Make a vacuum of orr and apply high frequency voltage of 300W,
BCl ₃Or Cl₂It is performed by using gas plasma. This
When using a dry etching method such as
The etching rate of the oxide film 9 is different from that of the polycrystalline silicon 14.
The etching is stopped by the thermal oxide film 9 because it is much slower.
It Therefore, the thermal oxide film 9 is not etched and is often
Only the crystalline silicon 14 is etched.

(Fourth Step) Next, after removing the photoresist pattern 15 by ashing, hydrogen treatment is performed.
Here, the reason for performing the hydrogen treatment will be described. Since hydrogen molecules are so small that they do not pass through the polycrystalline silicon 14 and the gate polycrystalline silicon 10, but pass through the interlayer insulating layer 11, the thermal oxide film 9 is exposed to hydrogen. Further, in reality, since the length of the gate polycrystalline silicon 10 portion is on the order of submicron, hydrogen instantaneously penetrates between the polycrystalline silicon 14 and the gate polycrystalline 10 and the thermal oxide film 9. Therefore, the thermal oxide film 9 is entirely exposed to hydrogen. Since hydrogen has a function of reducing and recovering a portion damaged by oxidation, if hydrogen treatment is performed on the portion of the thermal oxide film 9 damaged by oxidation, traps formed in the thermal oxide film 9 and The interface state can be eliminated.

Next, a silicon nitride 12 is formed on the thermal oxide layer 9 and the interlayer insulating layer 11 by the CVD method. Thus, the antireflection film 13 is formed from the thermal oxide layer 9 and the silicon nitride 12 on the light receiving portion 3c of the light receiving element portion 3. As a result, an integrated light receiving element 1 similar to that shown in FIG. 1 is obtained.

As described above, the etching rate of the interlayer insulating layer 11 is high, and the etching is stopped at the polycrystalline silicon 14 which is much slower than the etching rate of the interlayer insulating layer 11. The etching rate of the polycrystalline silicon 14 is
Since it is fast and much slower than the thermal oxide layer 9, the etching stops at the thermal oxide film 9. Therefore, CVD
Since the silicon nitride 12 is formed on the thermal oxide film 9 whose thickness is controlled by the method, the thickness of the antireflection film 13 becomes accurate. As a result, it is possible to obtain good light reception with stable reflectance and no variation in photoelectric conversion efficiency.

Further, since it is not necessary to form the thermal oxide film 9 on the light receiving element portion 3 thickly, the influence of the thermal oxidation applied when forming the thermal oxide film 9 is eliminated, so that the polycrystalline silicon 14 is formed. Can be prevented. Since hydrogen treatment is performed before forming the silicon nitride 12, traps and interfaces formed in the thermal oxide film 9 below the gate polycrystalline silicon 10 when plasma etching the polycrystalline silicon 14 using the dry etching method are performed. The level can be eliminated. Therefore, it is possible to obtain the MOS transistor 4 capable of performing stable operation.

In the embodiment of the present invention, the polycrystalline silicon 14 was formed on the thermal oxide film 9 in the (first step).
A CVD insulating film formed by the CVD method may be provided between the thermal oxide film 9 and the polycrystalline silicon 14. In this case, the antireflection film 13 may be composed of the CVD insulating film and the thermal oxide film 9 after etching the polycrystalline silicon 14 corresponding to the light receiving element section 3. Also in this case, the same effect as the effect of the present invention can be obtained.

[0025]

According to the method of manufacturing an integrated light receiving element according to the present invention, when the interlayer insulating layer is etched, the etching rate of the interlayer insulating layer is fast and the etching rate of the interlayer insulating layer is significantly slow. Etching stops at the gate polysilicon. Further, since the etching rate of the gate polycrystalline silicon is high and the etching rate of the gate polycrystalline silicon is much slower than that of the thermal oxide layer, the etching stops at the thermal oxide film. Therefore, since silicon nitride is formed on the thermal oxide film of which thickness is controlled, the thickness of the antireflection film including the thermal oxide film and the insulating layer is accurate. Therefore, it is possible to obtain an integrated light receiving element having a good photoelectric conversion efficiency of the light receiving element section.
Further, after removing the polycrystalline silicon, hydrogen treatment is performed on the interlayer insulating layer and the thermal oxide film, so that traps and interface states formed in the thermal oxide film under the gate polycrystalline silicon can be eliminated, and the driving circuit The part can be driven stably.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing an integrated light receiving element manufactured by an integrated light receiving element manufacturing method of the present invention.

FIG. 2 is a cross-sectional view showing (first step) of the method for manufacturing an integrated light-receiving element of the present invention.

FIG. 3 is a cross-sectional view showing (second step) of the method for manufacturing an integrated light-receiving element of the present invention.

FIG. 4 is a cross-sectional view showing (third step) of the method for manufacturing an integrated light receiving element of the present invention.

FIG. 5 is a sectional view showing a conventional integrated light receiving element.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Integrated light receiving element, 2 ... N-type semiconductor substrate, 3 ... Light receiving element part, 4 ... MOS transistor (driving circuit part), 8 ... Gate, 9 ... Thermal oxide film, 10 ... Gate polycrystalline silicon, 1
1 ... Interlayer insulating layer, 12 ... Silicon nitride (insulating layer), 13
... Antireflection film, 14 ... Polycrystalline silicon

Front page continued (58) Fields surveyed (Int.Cl. ⁷ , DB name) H01L 27/14 H01L 31/02 H01L 31/10

Claims (2)

(57) [Claims] 1. A method of manufacturing an integrated light-receiving element, comprising a semiconductor substrate and a light-receiving element section having a light-receiving section and a circuit driving section having a gate integrated with each other, wherein a thermal oxide film is formed on the light-receiving section and the circuit driving section. A step of forming, a step of forming polycrystalline silicon on the thermal oxide film, a step of etching the polycrystalline silicon except for the light receiving portion and the gate portion, and on the polycrystalline silicon and the thermal oxide film Forming an interlayer insulating layer and etching the interlayer insulating layer on the light receiving portion to the polycrystalline silicon; etching the polycrystalline silicon to the thermal oxide film; the interlayer insulating layer and the thermal oxidation; Performing a hydrogen treatment on the film to recover the damage caused by the etching; and forming an insulating layer on the interlayer insulating layer and the thermal oxide film,
A method of manufacturing an integrated light receiving element, comprising the step of forming an antireflection film including the thermal oxide film and the insulating layer on the light receiving portion. 2. The method of manufacturing an integrated light receiving element according to claim 1, wherein the etching is dry etching.