JP2971157B2 - Packet switching method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a packet switch, which divides a packet into a plurality of fixed lengths,
The present invention relates to a packet switching system for transmitting a packet with a header including a sequence number and the like.

[0002]

2. Description of the Related Art Conventionally, as a technique in this field, for example, a technique described in Japanese Patent Application Laid-Open No. 2-181555 is known. FIG. 4 is a block diagram showing the conventional packet switching system. In the conventional packet switching system shown in the figure, in order to divide a packet into a plurality of fixed lengths and transmit them to the line, the control processor sets transmission data on the input buffer circuit 34 for each packet, and sets the information length. A data length and a destination are set in the receiving circuit 31 and the destination receiving circuit 32, respectively, and thereafter, packets are divided into fixed lengths by a hardware control and transmitted over the line.

[0003]

However, in the packet switching system having the above configuration, every time one packet is transmitted, the control processor sends out data to the input buffer circuit 34, and the information length receiving circuit 31 outputs the data length.
Each destination must be set in the destination receiving circuit 32. Therefore, when there are a large number of packets to be transmitted, there is a problem in that the overhead of the program becomes large and high-speed packet transfer cannot be performed.

After a packet is transmitted, an input buffer circuit 3 is used until it can be confirmed whether or not the packet has reached the destination.
The area of that packet in 4 cannot be vacated. And since the transmission confirmation does not always return from the partner side in the order of transmission, the input buffer does not become empty as a continuous area, that is, it becomes empty as a continuous area. There is a problem that the empty area cannot be used effectively.

The present invention solves the above-mentioned conventional problems,
An object of the present invention is to provide a packet switching system capable of transferring a large amount of packets at high speed by minimizing the intervention of a control processor and effectively utilizing a data area of a buffer memory.

[0006]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the present invention provides a packet switching system which divides packet data into fixed lengths, adds header information and the like, and sends the fixed length packets. In the system, first storage means (transmission buffer memory 1) for storing packet data to be transmitted, header information (a ₀ , b _0, etc.) of the transmission data and the route of the transmission data in the first storage means are separately provided. Second storage means (route-specific command table memory 4) for storing information (p _{0 and the} like) indicating a storage address for each header information
And third storage means (route-specific command table address memory 7) for storing information (e.g., _x0 ) indicating a storage address for each route of the header information in the second storage means. The information (a ₀ , b ₀ , p _0, etc.) stored for each header information is read out by designating the read address of the second storage means by the information (x _0, etc.) stored in the storage means, the reading the transmission data specified by the read address of the first storage means by the information (p _0, etc.) indicating the storage address of the transmission data read out from the second storage means in which the features.

[0007]

According to the present invention, since the packet switching system is configured as described above, the control processor firstly sets the header information (a ₀ , header information) of the packet data stored in the first storage means (transmission buffer memory 1). It reads b _0, etc.) denote the storage address information (p _0, etc.), stores each header information of the transmission data to the second storage means (route-specific command table memory 4), leaving the third storage means ( storing information indicating the storage address of the header information in the second storage means to route specific command table address memory 7) (x _0, etc.). Then, the information (x
₀ ), the read address of the second storage means is designated, and each piece of information (a ₀ , b ₀ ,
It reads p _0, etc.), reads the transmission data specified by the read address of the second information indicating the storage address of the transmission data read out from the storage means (p _0, etc.) by the first storage means.

[0008]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a block diagram showing a packet switching system according to an embodiment of the present invention. FIG. 2 is a data configuration diagram in a transmission buffer memory, a command table memory for each route, and a command table address memory for each route in the embodiment of the present invention. FIG. 3 is a configuration diagram of a fixed length packet in the embodiment of the present invention.

Next, the operation of the packet switching system according to the embodiment of the present invention will be described with reference to FIGS. Assuming that a plurality of packets to be transmitted are stored in the transmission buffer memory 1 on the line 2 as shown in FIG. 2A, first, the control processor 3 reads the contents of the transmission buffer memory 1, Know the outgoing route number, partner terminal number, and data length for each packet. Then, a transmission command table for each packet is created for each route in the route-specific command table memory 4 in the format shown in FIG. 2B. further,
FIG. 2 (c) shows the command table address memory 7 for each route.
A command address table is created for each route in the format shown in (1).

First, the counter 6 is initialized by the control circuit 5, and the head address of the path-specific command table address memory 7 is set. At this time, the selector 8 is directed to the A side by the control circuit 5. Then, the control circuit 5 reads the contents of the head address of the path-specific command table address memory 7 and sets the contents of the counter 10 through the selector 9. That is, the content x of the head address y ₀ of the route-specific command table address memory in FIG.
₀ is read out and set in the counter 10. Next, the control circuit 5 reads out the contents of the path-specific command table memory 4 by designating a read address based on the output value of the counter 10, and transfers it to the transmission circuit 11. Next, the control circuit 5 counts up the counter 10 by one, reads out the contents of the command table memory 4 for each route, and transfers it to the sending circuit 11 in the same manner as described above. To explain this in FIG. 3, first output path number a ₀ is read from the head address x ₀ of route-specific command table memory in FIG. 2 (b), are transferred to the transmitting circuit 11, then the remote terminal number b ₀ is read and transferred to the sending circuit 11 again.

Next, the counter 10 is counted up by one, and the transmission buffer address, that is, p ₀ in FIG. 2B is read out and set in the counter 12. Next, the counter 10 is incremented by one, and the command address, that is, x ₃ as shown in FIG. 2B is read out and held in the flip-flop 13. Next, the counter 10 is incremented by one, and the number of transmission frames, that is, k ₀ in FIG.
Set to 4. Next, the counter 10 counts up by one, reads out a plurality of packet information (in this case, information indicating “there is a plurality of packets” shown in FIG. 2B), and holds it in the control circuit 5. Next, the counter 10 is incremented by one, and the command table end instruction information (in this case, FIG.
(Information "command table not completed" shown in (b))
Is read and stored in the control circuit 5.

Now that all the information necessary to transmit one packet has been prepared, the transmission procedure will be described next. First, the header information a ₀ , b transferred from the route-specific command table memory 4 by the control circuit 5 earlier
Sends ₀ . Next, the selector 15 is turned to the B side.
_The transmission data is sequentially read from the address p _{0 of the} transmission buffer memory 1 by using the output of the counter 12 in which the value of ₀ is set, and the count is counted a fixed number of times, that is, the fixed length while transferring to the transmission circuit 11, and the counting is stopped. At the same time, the count end signal 21 is turned on to notify the sending circuit 11.

When the transmission circuit 11 receives the count end signal 21, it knows the end of the transmission of the fixed-length data, adds the FCS, and ends the transmission of one fixed-length packet. At this time, the counter 14 holds the number (k ₀ ) of fixed-length data to be transmitted, and is counted down by −1 according to the count end signal 21. At this time, since the count enable signal 22 output from the counter 14 remains on, the counter 12 turns off the count end signal 21 and continues counting for a fixed length, and transfers the transmission data from the transmission buffer memory 1 to the transmission circuit 11. The sending circuit 11 sends out the header information a ₀ and b ₀ to the line, sends out the data thereafter, adds the FCS by the count end signal 21, and ends the sending operation. Hereinafter, the above operation is continued until the output of the counter 14, that is, the count enable signal 22 is turned off.

As described above, one packet is transmitted at high speed and continuously by hardware control without intervention of the control processor. Next, the control circuit 5 recognizes that there is still a packet to be sent to the same destination based on the information “there is a plurality of packets” held in the above and the value held in the flip-flop 13, and Similarly, the selector 9 is turned to the B side, and the value x ₃ held in the flip-flop 13 is set in the counter 10. And
Using the above x ₃ , x of the command table memory 4 for each route
Counting and reading are performed from address _{3 in the same} manner as described above, and preparation for packet transmission is performed again.

Next, the transmission data is read out from the transmission buffer memory 1 in the same manner as described above, transferred to the transmission circuit 11, and headers a ₀ and b ₀ are added.
To perform a sending operation. The above operation is performed by the counter 14
Until the count enable signal 22 is turned off. After the transmission of one packet is completed, the control circuit 5
Since the command table end instruction information indicates the end, it recognizes the end of transmitting a plurality of packets to one destination.

Next, the control circuit 5 counts up the counter 6 by one so as to indicate the next address of the command table address memory 7 for each route. Then, the control circuit 5 controls the command table address memory 7 for each output route.
Is read out and set in the counter 10 through the selector 9. Referring to FIG. 2, the content x ₁ of the address y _{1 of the} command table address memory for each departure path shown in FIG. 2C is read and set in the counter 10.

Hereinafter, the operation described above is repeated. In this way, when the counter 6 finishes counting, the count end signal 23 is turned on, and the control circuit 5 is notified. The control circuit 5 notifies the control processor 3 by turning on the transmission completion signal 24 when all the packets currently being transmitted have been transmitted.

In the above embodiment, the packet transferred from the control processor is stored in the buffer memory. However, the packet may be stored in the buffer memory by DMA transfer. Further, the present invention is not limited to the above-described embodiment, and various modifications are possible based on the gist of the present invention, and they are not excluded from the scope of the present invention.

[0019]

As described above in detail, according to the present invention, the control processor first reads the header information and the data length of a large amount of packets stored in the first storage means (transmission buffer memory), After setting the second storage means (route-specific command table memory) and the third storage means (route-specific command table address memory), the transmission operation of all packets is continuously performed only by read control. Thus, the intervention of the control processor can be reduced and a large amount of packets can be transferred at high speed.

The address of the first storage means (transmission buffer memory) and the address of the second storage means (command memory for each path) are used as data for the second storage means (command table memory for each path). Since the data is stored, the transmission data at an arbitrary position in the transmission buffer memory can be transmitted, and the command table for each route can be placed at an arbitrary position in the memory, so that the memory can be effectively used.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a packet switching system according to an embodiment of the present invention.

FIG. 2 is a data configuration diagram of a memory according to an embodiment of the present invention.

FIG. 3 is a configuration diagram of a fixed-length packet according to the embodiment of the present invention.

FIG. 4 is a block diagram showing a conventional packet switching system.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 transmission buffer memory 2 line 3 control processor 4 route-specific command table memory 5 control circuit 6, 10, 12, 14 counter 7 route-specific command table address memory 8, 9, 15 selector 11 sending circuit 13 flip-flop

Claims (2)

(57) [Claims] 1. Dividing packet data into fixed lengths,
In a packet switching system in which header information and the like are added and fixed length packets are transmitted, (a) first storage means for storing packet data to be transmitted, (b) header information of the transmission data and the first A second storage unit for storing, for each header information, information indicating a storage address for each route of the transmission data in the storage unit; and (c) a route of the header information in the second storage unit.
A third storage unit for storing information indicating another storage address, wherein a read address of the second storage unit is designated based on the information stored in the third storage unit, and stored for each of the header information. Characterized in that the read out data is read out by reading out the read information and designating the read out address of the first storage means by the information indicating the storage address of the transmission data read out from the second storage means. Exchange method. To wherein (a) a second storage means, information indicating the storage address of the header information and <br/> control data, and information indicating the number of divisions into <br/> fixed length data of the transmission data Information indicating that there are a plurality of packets to be sent to the same destination stored in the first storage means, and whether the control data exists;
Or a command table indicating if it no longer exists
And (b) storing the second instruction information based on the information read from the third storage means.
And means for reading stored said control data to each header information storage means, and means for reading the transmission data according to the information indicating the (c) storing the address of the transmission data read from the second storage means, ( notifying means for controlling the means to issue said read per d) a plurality of fixed length, that it has completed sending the (e) said to read the storage address of the control data for every header information, and all packets 2. A packet switching system according to claim 1, further comprising: ( f ) a control circuit for controlling the operation timing of each of said means.