JP2970512B2 - Vector processor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001] 1. Field of the Invention [0002] The present invention relates to a vector processor, and more particularly to a vector processor that realizes coordinate conversion processing used in computer graphics and the like.

[0001]

2. Description of the Related Art Conventionally, in this type of technology, coordinate conversion processing for projecting and projecting three-dimensional coordinates as shown in the following equation is realized by connecting one or more microprocessors and controlling the software on the processor. I was

[0002]

Further, a general-purpose DSP or the like is connected to a microprocessor to realize a coordinate conversion process for projecting and projecting three-dimensional coordinates as shown in the above equation. Further, for example, as disclosed in Japanese Patent Application Laid-Open No. 1-270174, a dedicated A
It is considered that the SIC is provided with a pipeline configuration arithmetic unit. In this Japanese Unexamined Patent Publication No. 1-270174, the coordinate transformation process is divided into four stages, each stage has registers on the input side and the output side except for the final stage, and the operation of each stage is performed when the input side registers are empty. A technique to be executed in the case is described.

[0004]

In the above-mentioned prior art,
Since a general-purpose processor or the like is used and the coordinate conversion processing is realized by a software program, there is a problem that the coordinate conversion processing cannot be performed at high speed.

In the prior art, the coordinate transformation process is divided into four stages. Each stage has a register on the input side and the output side except for the final stage, and the operation of each stage is performed when the register on the input side is empty. To run
There was a problem that the coordinate conversion process could not be performed at high speed.

An object of the present invention is to provide a vector processor capable of performing image generation processing at high speed.

[0007]

In order to solve the above-mentioned problems, a vector processor according to the present invention is a vector processor including a plurality of pipeline operation mechanisms and performing vector processing by a multi-parallel pipeline. mechanism seen <br/> including control means for controlling switching of a mode for executing the mode coordinate conversion processing executes a normal operation process for performing vector processing by multiple parallel pipelines, it executes the normal processing mode Before if
The same vector for each of the multiple pipeline operations
A mode for sorting and sending data and executing coordinate conversion processing
In the case of a plurality of pipeline operation mechanisms,
Rhodes sending multiple different vector data to each
A pipeline operation mechanism, further comprising a tor unit;
Has a plurality of first input vector registers and the first input
Select the data to be stored in the force vector register.
Selection means, wherein the control means includes
Multiple pipelines in the execution mode
The first input vector register at the same position in each of the arithmetic mechanisms;
So that the registers store different vector data
If the mode is to execute the target conversion process,
A first input vector at each of the same positions of the ply operation mechanism
The same vector data in the register
Instruct the selection means.

In another vector processor according to the present invention, the pipeline operation mechanism includes a plurality of second input vectors.
A torque register, a plurality of scalar registers, and the second
From the output from the vector register and from the scalar register
Second selection means for selecting and outputting the output of the
Output from the vector register and the output from the selection means.
And a plurality of multipliers for multiplying
And an output vector for storing the output of the adder.
And a control register, wherein the control means includes
If the mode is to execute arithmetic processing, the second vector
Output from the motor register to the
If it is a mode, select the output from the scalar register.
The second selection means is instructed to make a selection.

Another vector processor according to the present invention performs vector processing by a multi-parallel pipeline.
A vector processor, k pipeline arithmetic units
Wherein the pipeline operation mechanism comprises a plurality of first
An input vector register and the first input vector register
First selecting means for selecting an input to the
An input vector register, multiple scalar registers,
The output from the second vector register and the scalar
Second selection means for selectively outputting the output from the register,
The output from the input vector register and the selection means
A plurality of multipliers for multiplying the output of
Adder that adds the output of the adder, and stores the output of the adder.
Output vector register and the result of decoding the instruction
When indicating a coordinate transformation, the first input vector register
Data in the scalar register
The selection means so as to selectively output the output from the
And the first vector register when indicating normal operation
To store (k-1) discrete vector elements,
Select output from second vector register
Control means for instructing the selection means

[0010]

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, an embodiment of the vector processor according to the present invention will be described in detail with reference to the drawings.

A vector processor according to one embodiment of the present invention implements the following three-dimensional matrix operation. In the following equation, X, Y, Z, x, y, and z are vectors X [k], Y [k], Z [k], x each including m elements.
[K], y [k] and z [k] (0 ≦ k ≦ m).

[0013]

Referring to FIG. 2 , a vector processor according to an embodiment of the present invention includes pipeline operation units 1 and 2.
And 3 are connected to the load / store unit 4 via buses 6, 7, 8, 9, 10, and 11, respectively. The load store unit 4 is connected to the main storage device 5.

The pipeline operation mechanisms 1, 2, and 3
It performs vector pipeline operation, and all of these internal configurations are the same.

The buses 6, 7, and 8 are connected to all inputs of the pipeline arithmetic units 1, 2, and 3, and supply input data to each pipeline arithmetic unit.
Input data is stored in the main memory 5, pies via bus 6, 7 and 8 by load store unit 4
It is supplied to the pipeline operation mechanisms 1, 2, and 3. Bus 9, 10 and 11 are respectively connected to the output side of the pipeline operation mechanism 1, 2 and 3, each pipeline
The output of the in- operation mechanism is sent out. The output data is stored in the main storage device 5 via the load store unit 4.

Referring to FIG. 3 , a vector operation mechanism 1 according to one embodiment of the present invention includes input vector registers 1-1, 1 and 2.
-2 and 1-3 and multipliers 1-5, 1-6 and 1-7
, A multi-input adder 1-8, and an output vector register 1-4. Each of buses 6, 7 and 8 is connected to selectors 1-12, 1-13 and 1-14. The selector 1-12 is connected to the input vector register 1-1, the selector 1-13 is connected to the input vector register 1-2, and the selector 1-14 is connected to the input vector register 1-3.
Select the inputs to these registers.

The scalar register 1-9 has a selector 1-15.
It is connected to the. The selector 1-15 selects the contents of the scalar register 1-9 and the contents of a vector register (not shown). The multiplier 1-5 includes the selector 1
The output from -15 and the output from vector register 1-1 are input and multiplied. The scalar register 1-10 is connected to the selector 1-16.
The selector 1-16 selects the contents of the scalar register 1-10 and the contents of a vector register (not shown). The multiplier 1-6 is connected so that the output from the selector 1-16 and the output from the vector register 1-2 are input and multiplied. The scalar register 1-11 is connected to the selector 1-17. This selector 1-
Reference numeral 17 selects the contents of the scalar register 1-11 and the contents of a vector register (not shown). Multiplier 1-7
Are connected so that the output from the selector 1-17 and the output from the vector register 1-2 are input and multiplied. The outputs of the multipliers 1-5, 1-6 and 1-7 are connected to a multi-input arithmetic unit 1-8 and added. The output of the multi-input adder 1-8 is connected so as to be stored in the output vector register 1-4.

The pipeline operation mechanism 1 includes a control circuit 1-
The control circuit 21 controls switching between a normal operation mode for executing vector processing by a conventional multiple parallel pipeline and a coordinate conversion mode for executing coordinate conversion processing. The mode switching instruction signal from the control circuit 1-21 is supplied to the selectors 1-12, 1-13, and 1-1.
4, 1-15, 1-16, 1-17, 1-18, 1-1
9 and 1-20, and these selectors are switched according to the respective modes.

Next, the operation of the vector processor according to one embodiment of the present invention will be described in detail with reference to the drawings.

An instruction control circuit (not shown) decodes the instruction, and determines whether the operation mode is the normal operation mode or the coordinate conversion mode by the control circuits 1-21, 2-21 and 2-21 of the pipeline operation mechanisms 1, 2 and 3. Notify 3-21. Each of the control circuits 1-21, 2-21, and 3-21 receives this notification and controls switching between the normal operation mode and the coordinate conversion mode. In the normal operation mode, the pipeline operation mechanism 1, 2 and 3 a single vector data V [k] (0
≦ k ≦ 3m) is sent by distributed, each pipeline
The input vector register of down operation mechanism, different vector elements are stored. In coordinate transformation mode, the pipeline
The same vector data x
Each of [k], y [k] and z [k] (0 ≦ k ≦ m) is sent out and stored in each of the input vector registers of each pipeline operation unit. In the normal operation mode, three vector operations are executed simultaneously, and in the coordinate conversion mode, one coordinate conversion is executed simultaneously. The notification of whether the mode is the normal operation mode or the coordinate conversion mode is also sent to the load store unit 4. When the load store unit 4 is in the normal operation mode, the buses 6, 7, and 8
, And a bus 7 has vector elements V [1], V [4],..., And a bus 7 has vector elements V [2], V [5],. , And are distributed to the bus 8 as vector elements V [3], V [6],... When in the coordinate transformation mode,
Vector x [k] on bus 6 and vector y on bus 7
[K] causes the bus 8 to transmit the vector z [k].

Referring to FIG. 3 , in the normal operation mode, control circuit 1-2 in pipeline operation mechanism 1 is provided.
1 instructs the selector 1-12 to select the bus 6 so that the data of the bus 6 is input to the pipeline operation mechanism 1. Elements V [1], V [4],... Are stored in the input vector register 1-1.

The control circuit 1-21 instructs the selector 1-15 to select scalar data or the contents of another vector register (not shown). The scalar data selected by the selector 1-15 or the contents of another vector register (not shown) is sent out as one input of the multiplier 1-5.

The multiplier 1-5 has an input vector register 1
-1 is multiplied by the scalar data selected by the selector 1-15 or the contents of another vector register (not shown). This multiplication result is stored in another vector register (not shown). Also,
Selector 1-19 receiving instruction from control circuit 1-21
Can be used as one input of the multi-input adder 1-8.

In the pipeline operation mechanism 2, the vector elements V [2], V [5],... Are stored in the input vector register 2-1 from the bus 7, and
In the operation unit 3, the vector element V
[3], V [6],...
1 and the vector operation is performed similarly.

In the coordinate conversion mode, in the pipeline operation mechanism 1, X [k] = a [1,1] * x [k] + a [2,1] * y [k]
+ A [3,1] * z [k] In the pipeline operation mechanism 2, Y [k] = a [1,2] * x [k] + a [2,2] * y [k]
+ A [3,2] * z [k] In the pipeline operation mechanism 3, Z [k] = a [1,3] * x [k] + a [2,3] * y [k]
The operation of + a [3,3] * z [k] is realized respectively.

The vector x [k] (0 ≦ k) via the bus 6
≦ m) is converted into a vector y [k] (0 ≦ k ≦
m) is converted into a vector z [k] (0 ≦ k ≦
m) are sent to the pipeline operation mechanisms 1, 2 and 3, respectively.

In the pipeline operation mechanism 1, the control circuit 1-21 selects the bus 6 for the selector 1-12 and stores the vector element x in the input vector register 1-1.
[K] (0 ≦ k ≦ m) is instructed to be stored. The control circuit 1-21 selects the bus 7 for the selector 1-13, and stores the vector element y in the input vector register 1-2.
[K] (0 ≦ k ≦ m) is instructed to be stored. The control circuit 1-21 selects the bus 8 for the selector 1-14 and stores the vector element z in the input vector register 1-3.
[K] (0 ≦ k ≦ m) is instructed to be stored. Register 1-9 stores the value of matrix element a [1,1]. The scalar register 1-10 has a matrix element a [2,1]
Is stored. The value of the matrix element a [3, 1] is stored in the scalar register 1-11. In the multiplier 1-5,
The content output from the input vector register 1-1 is multiplied by the content from the scalar register 1-9 selected by the selector 1-15 according to an instruction from the control circuit 1-21. In the multiplier 1-6, the content output from the input vector register 1-2 is multiplied by the content from the scalar register 1-10 selected by the selector 1-16 according to the instruction of the control circuit 1-21. The multiplier 1-7 multiplies the content output from the input vector register 1-3 by the content from the scalar register 1-11 selected by the selector 1-17 according to an instruction from the control circuit 1-21. Multipliers 1-5, 1
The operation results of -6 and 1-7 are input to the multi-input adder 1-8 and added. This result is output vector register 1
-4. The contents of the output vector registers 1-4 are stored in the load store unit 4 via the bus 9.

The processing in the coordinate conversion mode in the pipeline operation mechanism 1 is performed by the pipeline operation mechanisms 2 and 3
Is performed similarly.

Referring to FIG. 4 , the horizontal axis of the timing chart represents time. The lengths of the upper and lower sides of the diamond represent the time required to process all elements of the vector register.

In the load processing, a vector x [k] (0 ≦ k ≦ m) is transferred from the main memory to the input registers 1-1, 2-1 and 3-1 by the load store unit, and a vector y [k] is input.
(0 ≦ k ≦ m) to input registers 1-2, 2-2, 3-2
And the vector z [k] (0 ≦ k ≦ m) in the input register 1
-3, 2-3, and 3-3 respectively. This loading process includes a turnaround time T
It takes only L. The loaded vector elements are multipliers 1-5, 1-6, 1-7, 2-5, 2-6, 2-7, 3
At -5, 3-6 and 3-7, each element of the preset coordinate transformation matrix is multiplied simultaneously by all multipliers. This multiplication process takes only the turnaround time TM. The multiplication results output from the respective multipliers are sent to multi-input adders 1-8, 2-8 and 3-8, and the multi-input adders simultaneously perform addition processing. This addition process requires only the turnaround time TA.

From the above, the turnaround time for all processes is (TL + TM + TA). As the throughput, one coordinate conversion can be performed per clock cycle.

Thus, in the first embodiment of the present invention,
Input vector registers 1-1 and 1- for the order of coordinate transformation
2,1-3,2-1,2-2,2-3,3-1,3-
2, 3-3 were provided. Continuous vector elements were stored in this input vector register. Since the arithmetic processing of these and the coordinate conversion matrix is performed in parallel, one coordinate conversion can be realized per clock cycle.

[0034]

[0035]

[0036]

[0037]

[0038]

[0039]

[0040]

[0041]

[0042]

[0043]

[0044]

[0045]

[0046]

[0047]

[0048]

As is apparent from the above description, according to the present invention, a vector processor for performing vector processing by a multiplex parallel pipeline including a plurality of pipeline arithmetic mechanisms is provided with a coordinate conversion mode and a normal arithmetic mode.
These are switched. In normal operation mode,
To store different data in the input vector register in the same position of each of the plurality of pipeline operation mechanism, in the coordinate conversion mode, to store the same data in the input vector register in the same position of each of the plurality of pipeline operation mechanism I made it. For this reason, a plurality of vector calculations can be performed simultaneously during the normal calculation, and one coordinate conversion can be performed simultaneously during the coordinate conversion.

According to the present invention, at the time of coordinate conversion,
A continuous vector is stored in a plurality of input vector registers, the value of the input vector register is multiplied by the values of a plurality of scalar registers storing each element of a coordinate transformation matrix, and the result is added by a multi-input adder. I did it. Therefore, the coordinate conversion processing can be executed at high speed.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of a vector processor according to the present invention.

FIG. 2 is a block diagram showing an internal configuration of a pipeline operation mechanism according to one embodiment of the present invention.

FIG. 3 is a timing chart showing the operation timing of the vector processor according to one embodiment of the present invention.

FIG. 4 is a block diagram illustrating a configuration of a vector processor according to a second embodiment of the present invention.

[Explanation of symbols]

 1, 2, 3 Pipeline operation mechanism 4 Load store unit 5 Main storage device 6, 7, 8, 9, 10, 11 Bus 1-1, 1-2, 1-3 Input vector register 1-4 Output vector register 1 -5, 1-6, 1-7 Multiplier 1-8 Multi-input adder 1-9, 1-10, 1-11 Scalar register 1-12, 1-13, 1-14 Selector 1-15, 1- 16, 1-17 Selector 1-18, 1-19, 1-20 Selector 1-21 Control circuit

Claims (3)

(57) [Claims] 1. A vector processor for performing vector processing by multiple parallel pipelines including a plurality of pipeline operation mechanism, each of the plurality of pipeline operation mechanism, normal calculation for performing vector processing by multiple parallel pipelines selecting a control means for controlling switching of a mode for executing the mode coordinate conversion processing to execute processing, the next fraction first input vector register of the coordinate transformation, the data to be stored into the first input vector register With multiple selection means
Only including, the control unit, when a mode for executing the normal operations process is different among the plurality of pipeline operation mechanism
So as to store the first input vector <br/> Ru vector elements different for the registers in things, when a mode for executing a coordinate transformation process is first definitive to be different among the plurality of pipeline operation mechanism features and be behenate-vector processor that instructs the selecting means so as to store the same vector elements for one of the input vector register. 2. The pipeline operation mechanism includes a plurality of second input vector registers, a plurality of scalar registers, and a second output for selectively outputting an output from the second vector register and an output from the scalar register. A plurality of multipliers for multiplying an output from the first input vector register by an output from the selection unit; an adder for adding an output from the multiplier; and an output of the adder. Further comprising an output vector register for storing the output from the second vector register when the mode is a mode for executing a normal operation process, and a mode for executing a coordinate conversion process when the mode is a mode for executing a coordinate conversion process. 2. The vector processor according to claim 1, wherein said instruction instructs said second selecting means to select an output from said scalar register. 3. A vector processor for performing vector processing by multiple parallel pipelines includes k number of pipeline operation mechanism, each of the pipeline operation mechanism includes a plurality of first input vector register, this First selecting means for selecting an input to the first input vector register; a plurality of second input vector registers; a plurality of scalar registers; an output from the second vector register and a signal from the scalar register. Second selection means for selecting and outputting an output; a plurality of multipliers for multiplying the output from the first input vector register by the output from the selection means; and an addition for adding the outputs from the multipliers An output vector register for storing the output of the adder; and the first input buffer if the result of decoding the instruction indicates a coordinate transformation. Consecutive vector elements Torr register is sequentially stored, the instructing said selection means so as to select and output the output from the scalar register and to indicate normal operation for the first vector register (k-1) pieces 2. The vector processor according to claim 1, further comprising control means for instructing the selection means to store vector elements at intervals and to selectively output the output from the second vector register.