JP2580371B2 - Vector data processing device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a vector data processing apparatus, and more particularly, to an operation unit configuration method of a vector operation unit including a plurality of operation units and an operation execution method. .

[Prior Art] A vector data processing apparatus temporally overlaps a plurality of arithmetic units by a so-called chaining function in which a register for storing an operation result of a preceding operation instruction is designated as an operand register of a subsequent operation instruction. It can be used and has high data processing capability. When performing large-scale scientific and technical calculations with a vector data processing device,
As a program coding style, coding utilizing a parallel computing unit is generally used. That is, a technique for increasing the number of operation terms on the right side of an assignment statement is effective for improving performance. Also, in complex arithmetic and vector functions, the appearance ratio of vector operation instructions is higher than other vector instructions,
High-speed processing of operation instructions greatly contributes to overall performance improvement.

Hereinafter, a configuration of a conventional vector data processing device which improves performance in response to this kind of tendency will be described.

FIG. 6 shows a schematic configuration of an example of a vector data processing device having a plurality of arithmetic units. In the figure, a vector data processing device is composed of a high-speed random access memory (hereinafter, referred to as a RAM), can read and write independently, and can hold 32 vector data of 32 elements each of VR0 to VR31. Vector register 111
a to 111h, scalar data buffers 112a and 112b for storing scalar data corresponding to two operand data,
Vector registers 111a to 111h and scalar data buffer 11
A selector (hereinafter, referred to as SEL) 114 of switch matrix logic for selectively outputting the output data of 2a and 112b to each resource by an instruction, a No. 0 arithmetic unit 102 including a pipeline adder 101, and a pipeline multiplier The first operation unit 104 composed of the first operation unit 103, the operand paths 105 and 106 for inputting the operand data supplied through the SEL 114 to the zero operation unit 102, the operand paths 108 and 109 for inputting the first operation unit 103 similarly, A result path 107 for outputting the operation result of the operation unit 102, a result path 110 for outputting the operation result of the first operation unit 104, and a result path 1 according to an instruction.
The calculation result from 07, 110 is stored in the vector register 1 of VR0 to VR31.
Selector (hereinafter, referred to as DIST) 113 composed of switch matrix logic selected to write to 11a to 111h
It consists of.

It is assumed that a load pipeline for supplying operand data from the main memory to the vector register and a store pipeline for storing data from the vector register to the main memory are provided although not shown. Further, the resources referred to here refer to the 0th operation unit 102, the 1st operation unit 104, the load pipeline and the store pipeline, and each resource can perform a parallel operation and a chaining operation by an instruction.

In the vector data processing device shown in FIG.
No. operation unit 102, which is one operation resource, and No. 1 operation unit 1
04 can be operated in parallel. Therefore, an addition instruction and a multiplication instruction, or a multiplication instruction and an addition instruction can be processed in parallel, and high processing performance has been achieved by using a chaining operation together.

However, in the case where a polynomial operation in large-scale scientific and technical calculation is expanded into an instruction sequence of a vector data processing device, a case in which successive addition instructions that can be theoretically simultaneously processed in parallel and a case in which multiplication instructions are continuous appear. There are many cases. FIGS. 4 (c) and 4 (e) show a processing sequence in such a case in the vector data processing apparatus shown in FIG. In FIG. 4 (c), the instruction
Vadd VR0 VR1 VR2 represents an instruction to read the contents of the vector registers VR1 and VR2, add the vector data by the pipeline adder, and write the result to the vector register VR0. Hereinafter, this relationship is described as follows.

Vadd VR0 VR1 VR2 ⇒ VR1 + VR2 = VR0 The next instruction is Vadd VR3 VR4 VR5 ⇒ VR4 + VR5 = VR3. Similarly, the contents of the vector registers VR4 and VR5 are read, the vector data is added, and the result is written to the vector register VR3. Indicates an instruction. by the way,
These two instruction sequences can theoretically be operated simultaneously in parallel.
However, in the arithmetic unit configuration of the vector data processing device shown in FIG. 6, as shown in FIG. 4 (c), the first stage of the vector adder composed of a plurality of pipelines is VR1 + V
Not after the operand data for R2 has passed, VR
4 + Operand data for VR5 cannot be supplied to the first stage of the pipeline. The same applies to the case of the multiplication instruction shown in FIG. In the case shown in FIG. 4C, the chaining operation with the instruction preceding the Vadd instruction, for example, the instruction to load the vector register VR4 is interrupted. Such a state is called an operation resource bottleneck, and causes a reduction in performance. Further, in both cases of FIGS. 4 (c) and 4 (e), even though one of the operation resources is busy, the other operation resource is idle and the efficiency is low.

FIG. 7 shows a schematic configuration of a vector data processing device in which the configuration of a plurality of arithmetic units is further improved. In the figure, vector registers 215a to 215h, scalar data buffers 216a and 216b, SEL 218, operand paths 209, 210, and 2
The configuration of 12,213, result paths 211, 214, DIST 217, and the load / store pipeline is the same as in FIG. The first arithmetic unit 205 includes a pipeline adder 204. However, the 0-th arithmetic unit 203 has a composite configuration of the pipeline multiplier 202 and the pipeline adder 201, and outputs the arithmetic result of the pipeline multiplier 202 to the output path 206.
Through which data can be supplied as one operand of the pipeline adder 201. Further, the operand path 209 is configured to supply data to both the pipeline multiplier 202 and the pipeline adder 201. Operation result output path 206 of pipeline multiplier 202 and operation result output path 20 of pipeline adder 201
7 is such that the output path 206 is selected by the selector 208 when the multiplication instruction is executed, and the output pulse 207 is selected by the selector 208 when the addition instruction using the multiplication result as one operand data is output to the result path 211. It is configured. Further, the 0-th arithmetic unit 203 can execute a simple addition instruction using the pipeline adder 201 by allowing the data from the operand path 210 to pass through the pipeline multiplier 202 as it is. .

In the vector data processing device shown in FIG. 7, a complex operation (inner product, sum, etc.) is processed as a macro instruction as an automatic vectorizing function utilizing the complex arithmetic unit configuration.
For example, Hitachi's HITAC S-810 and its successor HITAC S-810
In the TAC S-820 vector data processing device, the inner product operation (S = S + A (I) * B (I)) that is effective in solving simultaneous linear equations by using the result of the vector multiplier as operand data of the vector adder ), Product-sum operation of three terms (A
(I) + C * B (I)) and the like, and a vector processing method for executing a composite operation as a macro instruction with one instruction is applied to achieve high speed. Since the vector data processing device shown in FIG. 7 has two adders, FIG.
It is possible to perform simultaneous parallel processing in the case indicated by. The case is shown in FIG. 4 (d). That is, since there is no contention for the addition operation resources, simultaneous parallel processing is possible. In addition, the fifth
A composite operation instruction (macro instruction) shown in FIG. In FIG. 5 (i), Vmltadd VR0 VR1 VR2 SR → (VR2 × SR) + VR1 = VR0. In the processing of the instruction, the preceding multiplication is a product of the vector data VR2 and the scalar data SR, and the subsequent addition is a product of the vector data (VR2 × SR) of the result of the preceding multiplication and the vector data VR1. However, in the vector data processing apparatus shown in FIG. 7, it is impossible to perform all-vector operand processing in which all operands such as, for example, Vmltadd VR0 R1 VR2 VR3⇒ (VR2 × VR3) + VR1 = VR0 are vector data. This is a constraint that both the reading of the vector data VR2 and the reading of the vector data VR1 use the operand path 209. Although it is conceivable to use the operand path 209 in a time-division manner, the control for this is complicated and the processing performance is reduced.

Furthermore, in order to perform chaining of instruction sequences and realize high-speed vector data processing in the vector data processing device having such an arithmetic unit configuration, scheduling control for effectively assigning arithmetic instructions to each arithmetic unit is necessary. It is. For example, if the first addition instruction is assigned to the 0th operation unit 203 in a continuous case of an addition instruction and a multiplication instruction, an operation resource conflict occurs at the next activation of the multiplication instruction. As a result, the multiplication process is awaited, and a chain break occurs. Such a non-uniform operation unit configuration requires complicated operation instruction scheduling especially in polynomial operation, and it is difficult to efficiently allocate the operation units.

The vector data processing device shown in FIG. 8 is another example in which polynomial operation processing is performed at high speed with a configuration of a plurality of operation units. 6, the vector registers 321a to 321h, the scalar data buffers 322a and 322b, and the load / store pipeline have the same configuration as in FIG. SEL32
4, operand path 309,310,312,313,315,316,318,319,
As for the result paths 311, 314, 317, 320, and DIST 323, the data paths for the arithmetic units increased compared to FIG. 6 and the selector logic is changed. Also, a No. 0 arithmetic unit 302 including a pipeline adder 301, a No. 1 arithmetic unit 304 including a pipeline multiplier 303, a No. 2 arithmetic unit 306 including a pipeline adder 305, The third arithmetic unit 308 including the pipeline multiplier 307 is an arithmetic resource and can execute arithmetic instructions independently and in parallel.

When the successive case of the addition instruction and the successive case of the multiplication instruction shown in FIG. 4 are executed for the vector data processing device shown in FIG. 8, as shown in FIGS. 4 (d) and 4 (f). Since the same type of operation resources do not conflict, the processing time of the instruction sequence can be reduced. However, in the case of such an arithmetic unit configuration, since a plurality of arithmetic units are all operation resources capable of executing one operation instruction, from the instruction control side, a scheduling process of allocating an operation instruction sequence to each operation resource is performed. It gets complicated. In addition, the amount of hardware such as a data path and control logic including the SEL 324 also increases. Further, the vector data processing device is capable of not only the polynomial operation case, but also load /
There are many instruction sequences in which store-related instructions and arithmetic-related instructions are mixed in a one-to-one ratio. In such a case, there occurs a computing unit in which the computing resources of the device are not used. That is,
It can be said that it is excessive design (over design).

By the way, as examples of the typical vector data processing device of the conventional example shown in FIG.
Hitachi, introduced on April 11, 1983, (No. 314), pp. 159 to 184, and 1987, December 28, 1987, (No. 437), pp. 111 to 125. HITAC S-810 and S-820 manufactured by HITAC. Japanese Patent Application Laid-Open No. 64-67678 discloses a similar vector data processing device. Further, an apparatus corresponding to the conventional example shown in FIG. 8 is a Hitachi HITAC S-8.
There are ten.

[Problems to be Solved by the Invention] According to the above-described conventional technology, the vector data processing apparatus may be used in a case where the same type of operation instruction is consecutive depending on the configuration of a plurality of operation units shown in FIG. An operation resource bottleneck occurs. In addition, there is a case where the efficiency of the operation is reduced due to a case where one operation resource is busy and the other operation resource plays. In addition, in order to support a complex operation instruction as shown in FIG. 7, in an arithmetic unit configuration in which a multiplier and an adder are connected in series,
All vector operand processing was not possible. Further, the method of increasing the operation resources shown in FIG. 8 not only requires twice as many data paths as the conventional one but also requires complicated operation instruction scheduling, which makes it difficult to efficiently allocate the operation units. . In addition, there is a problem that the amount of hardware increases to realize such complicated control.

Accordingly, an object of the present invention is to provide a vector data processing device including a plurality of arithmetic units, which overcomes the above-described problems and provides efficient vector data processing while minimizing an increase in the amount of hardware. And

Means for Solving the Problems In order to achieve the above object, a vector data processing device according to the present invention has a vector data buffer for holding a plurality of sets of vector data composed of a plurality of vector elements. A vector data processing apparatus for performing a vector operation on the vector data held in the first compound arithmetic unit including an adder and a multiplier, and having a path for feeding back at least one output of both arithmetic units to the other input; A second composite arithmetic unit having the same configuration as that of the first composite arithmetic unit, and three of the four inputs of the adder and the multiplier being externally provided from the first composite arithmetic unit. The first, second, and third operand paths that can be provided, and at the same time, three inputs out of all four inputs of the adder and the multiplier from the outside of the second complex operator are given at a time. Fourth capable, fifth, those provided with the sixth operand path.

Preferably, each of the first and second composite arithmetic units selectively returns the output of the adder to one of the four inputs, and outputs the output of the multiplier to the four inputs. Means for selectively feeding back to one of the inputs.

Also, preferably, for two consecutive same type of operation instructions, regardless of the type of the operation instruction, the preceding operation instruction is allocated to the less busy complex operation unit,
Operation instruction scheduling means for allocating a subsequent operation instruction to the other composite operation unit is further provided.

The operation instruction scheduling means, when a subsequent multiplication (or addition) instruction designates a register for storing the result of a preceding addition (or multiplication) instruction as the operand register, stores both instructions in the same complex operation unit. Can be assigned.

Preferably, each of the compound arithmetic units is configured such that, when a subsequent multiplication (or addition) instruction designates a register for storing a result of a preceding addition (or multiplication) instruction as the operand register, the preceding first operation An instruction is processed by an adder (or multiplier) using two of the three operand paths, and a subsequent operation instruction is processed by a multiplier (or adder) as a feedback path of the operation result and the remaining operand paths. Calculation processing is performed using

In each of the complex operation units, when the operation instruction is a macro operation instruction that uses a result of a preceding addition (or multiplication) as operand data of a subsequent multiplication (or addition), preferably, the preceding operation is performed by an adder (or a multiplier) ), The operation is performed using two of the three operand paths, and the subsequent operation is performed by a multiplier (or adder) using the feedback path of the operation processing result and the remaining operand paths.

At the timing when the result of the preceding operation is input to the operation unit of the subsequent operation via the feedback path, the operand itself or an instruction for reading the operand so that the operand from the remaining operand path reaches the operation unit. May be provided.

According to another aspect, a vector data processing device according to the present invention includes a vector data buffer that holds a plurality of sets of vector data including a plurality of vector elements, and performs a vector operation on the vector data held in the vector data buffer. In a vector data processing apparatus for performing a complex operation, a complex operation unit including an adder and a multiplier, and having a path for returning at least one output of both operation units to the other input, and the adder and the multiplication unit from outside the complex operation unit And a first, second, and third operand paths that can provide three inputs at a time out of all four inputs of the adder, wherein the complex arithmetic unit outputs the output of the adder to the output of the four inputs. Means for selectively feeding back to one input;
Means for selectively feeding back one of the inputs.

[Operation] In the vector data processing apparatus according to the present invention, in the case where the vector addition instruction is continuous, the first addition instruction is subjected to the arithmetic processing on the non-busy composite operation unit of the first and second composite operation units. Assignment, assigning the succeeding addition instruction to the opposite complex operator to which the leading addition instruction is assigned. Further, in the case where the vector multiplication instructions are consecutive, the first multiplication instruction is assigned an operation processing to the non-busy composite operation unit of the first and second composite operation units, and the subsequent multiplication instruction is assigned to the preceding multiplication instruction. Allocate to the opposite complex operator. Further, when the vector addition instruction and the vector multiplication instruction are continuous and both vector operation instructions are in a chaining relationship, the first addition operation instruction and the second operation unit which are not busy with respect to the first addition operation instruction are compared with each other. And the subsequent multiplication instruction is also assigned to the complex arithmetic unit.

The operand of the preceding addition instruction is read from the vector register or the scalar data buffer indicated by the instruction, and if the composite operation unit to which the addition instruction is assigned is the first composite operation unit, the first operand path and the second operand path are
In the case of the second compound operation unit, the signal is supplied to the pipeline adder through the fourth operand path and the fifth operand path. The supply operand outputs the addition result to the result path after the lapse of the operation stage of the pipeline adder, and writes the result to the vector register indicated by the addition instruction. Further, the result of the addition is input as a multiplicand data of the subsequent multiplication instruction to a pipeline multiplier of the complex arithmetic unit via a feedback path. The multiplication instruction is controlled so that the multiplier data is read from the vector register or the scalar data buffer indicated by the multiplication instruction so that the head element of the feedback result arrives at the head stage of the pipeline multiplier at the same time. When the unit is the first compound operation unit, the third operand path is input to the pipeline multiplier through the sixth operand path when the unit is the second compound operation unit. The supply operand outputs the multiplication result to the result path after the lapse of the operation stage of the pipeline multiplier, and writes the result to the vector register indicated by the multiplication instruction. Also, when a vector multiplication instruction and a vector addition instruction are continuous and both vector operation instructions have a chaining relationship, they are similarly assigned to the same complex arithmetic unit.

That is, in the processing device, when an operation instruction using a pipeline adder and an operation instruction using a pipeline multiplier are in a chaining relationship, these instruction strings are assigned to a control process assigned to the same complex arithmetic unit. I do.

Further, in the case of a macro instruction in which vector addition and vector multiplication are combined, the arithmetic processing is assigned to the non-busy one of the first and second compound operators. In the macro operation processing, the operand of the operation processing is read from a vector register or a scalar data buffer indicated by the instruction, and if the composite operation unit to which the macro instruction is assigned is the first composite operation unit, the first operand path, the second operand path, The operand path and the third operand path are supplied through the second compound operation unit, and the fourth operand path, the fifth operand path, and the sixth operand path are supplied through the second compound operation unit. In the supply operand, the first and fourth operands are operation data, and the second and fifth operands are operation target data. After the operation data and the data to be operated have elapsed by the operation stage of the preceding pipeline operation unit of the addition or multiplication indicated by the content of the macro instruction, the operation result is passed through a feedback path to the macro instruction of the composite operation unit. The data is input to the subsequent pipeline arithmetic unit of the addition or multiplication indicated by the contents as the operation target data of the subsequent operation. The operation data of the subsequent operation includes a third operand path when the composite operation unit is the first composite operation unit, so that a first element of the feedback result arrives at the first stage of the pipeline operation unit at the same time. In the case of a two-composite arithmetic unit, the sixth operand path is delay-controlled and input to the pipeline arithmetic unit. After a lapse of the operation stage of the pipeline operation unit, the supply operand outputs the operation result to a result path and writes the result to a vector register indicated by the macro instruction.

In the case where the macro instructions are consecutive, the first macro instruction is assigned to the arithmetic operation unit which is not busy with the first and second composite operation units, and the subsequent macro instruction is assigned to the preceding macro instruction. Assigned to the opposite complex operator.

[Examples] Hereinafter, examples of the present invention will be described in detail.

First, an embodiment of the first vector data processing device according to the present invention will be described. FIG. 1 shows a configuration excluding a control unit of the vector data processing device according to the present embodiment.

In the figure, the vector data processing device has 32 vector registers 3 of VR0 to VR31, each of which can read and write independently, and can hold vector data of 128 elements each.
3a to 33h, scalar data buffers 34a to 34c for storing scalar data corresponding to three operand data, vector registers 33a to 33h, and scalar data buffers 34a to 34a.
A switch matrix logic SEL 36 for selecting the output data of 4c to each resource by an instruction, and a switch for selecting and sending the write data sent from each resource to the vector registers 33a to 33h to the vector registers 33a to 33h indicated by the instruction. It is composed of a matrix logic DIST 35, a No. 0 complex operator 3 which is an operation resource, and a No. 1 complex operator 6. Although not shown, a load pipeline for supplying operands from the main memory to the vector register and a store pipeline for storing data from the vector register to the main memory are provided, and each is controlled as a resource from the control system. .

No. 0 complex operator 3 (hereinafter, PDI (Parallel Dual Instr.)
Auction 0) is a first operand path 15, a second operand path 16, a third operand path 17 for reading vector data and scalar data from vector registers 33a to 33h and scalar buffers 34a to 34c, and a pipeline. The operation result of the adder 1, the pipeline multiplier 2, and the pipeline adder 1 is fed back, and the path 11 is used as an operand of the pipeline adder 1 and the pipeline multiplier 2, and the operation of the pipeline multiplier 2 A path 12 that feeds back the result to be an operand of the pipeline adder 1 and the pipeline multiplier 2, and a first operand path
A selector 7 which selects input data from the feedback path 11, the feedback path 11 and the feedback path 12 by an instruction and uses them as addend data of the pipeline adder 1, a second operand path 16, a third operand path 17, and a feedback path 11
, A selector 8 which selects input data from the feedback path 12 by an instruction and uses it as addend data of the pipeline adder 1, a first operand path 15 and a feedback path.
A selector 9 that selects input data from the feedback path 11 and the feedback path 12 by an instruction and sets the data as multiplicand data of the pipeline multiplier 2, a second operand path 16, a third operand path 17, a feedback path 11 and a feedback path 12
10, a selector 10 which selects input data from the CPU 2 as an instruction to select multiplier data of the pipeline multiplier 2, an output circuit 13 of the pipeline adder 1, an output circuit 14 of the pipeline multiplier 2, and a pipeline adder. The result path 18 writes the operation result of 1 to the vector register, and the result path 19 writes the operation result of the pipeline multiplier 2 to the vector register.

The first composite computing unit 6 (hereinafter referred to as PDI computing unit 1)
Vector registers and scalar data are stored in vector registers
33a-33h and fourth operand path 28, fifth operand path 29, sixth operand path 30, read from scalar buffers 34a-34c, pipeline adder 4, pipeline multiplier 5, and pipeline adder 4. A path 24 which feeds back the operation result and is used as an operand of the pipeline adder 4 and the pipeline multiplier 5;
Is fed back to the pipeline adder 4
And a path 25 as an operand of the pipeline multiplier 5
And a selector 20 which selects input data from the fourth operand path 28, the feedback path 24, and the feedback path 25 by an instruction and uses the data as addend data of the pipeline adder 4, a fifth operand path 29, and a sixth operand Pass 30
And the input data from the feedback path 24 and the feedback path 25 are selected by the instruction and the pipeline adder 4
Selector 21 as the addend data of the fourth operand path
A selector 22, which selects input data from the feedback path 24, the feedback path 24, and the feedback path 25 by an instruction and sets the data as multiplicand data of the pipeline multiplier 5, a fifth operand path 29, a sixth operand path 30, and a feedback path 24.
And a selector 23 that selects input data from the feedback path 25 by an instruction and sets the data as multiplier data of the pipeline multiplier 5, an output circuit 26 of the pipeline adder 4, an output circuit 27 of the pipeline multiplier 5, It comprises a result path 31 for writing the operation result of the pipeline adder 4 to the vector register, and a result path 32 for writing the operation result of the pipeline multiplier 5 to the vector register.

FIG. 2 shows a configuration of the vector data processing device and the instruction control unit according to the present embodiment.

In the figure, the vector data processing device instruction control unit 37
Is the instruction buffer 38 and the execution instruction queue 4 for the PDI operator 1
0 (hereinafter, referred to as PDI1Xi), the next execution instruction queue 39 (hereinafter, referred to as PDI1Ni), and the execution instruction queue 4 for the PDI operation unit 0
2 (hereinafter, referred to as PDI0Xi), a next execution instruction queue 41 (hereinafter, referred to as PDI0Ni), and an instruction queue from the instruction buffer 38.
An instruction transfer path 45 to 39 to 42, a control path 44 for issuing a control instruction to the DIST 35, the vector register 33, the SEL 36, and the PDI arithmetic unit 0 according to the contents of the PDI0Xi and PDI0Ni, and a DIST 35, the vector register 33, the SEL 36, PDI1Xi, PDI for PDI calculator 1
The control path 43 issues a control instruction based on the contents of 1Ni. Also, instruction queues on two sides of Xi and Ni are provided for each resource, and each has a busy flag (busy flag).
falg) enables the management of the busy state of the instruction queue and resources. Although not shown, a resource instruction queue for the load / store pipeline is provided similarly to the instruction queue for the PDI0,1 arithmetic unit.

FIG. 3 is a diagram for explaining an example of an operation instruction sequence that is most effective in the first vector data processing device according to the present invention.

In the figure, the operation instruction sequence is Vadd VR0 R1 VR2⇒VR1 + VR2 = VR0 Vmlt VR3 VR4 VR0⇒VR4 × VR0 = VR3 Vmlt VR5 VR6 VR7⇒VR6 × VR7 = VR5 Vadd VR8 VR9 VR5⇒VR9 + VR5 = VR8, and instruction control It is assumed that instructions are sequentially stored in the instruction buffer 38 in the unit 37 with the instructions at the head. Further, the addition result VR0 of the instruction and the operand VR0 of the instruction, the multiplication result VR5 of the instruction, and the operand VR5 of the instruction have a chaining relationship.

The operation when the instruction sequence is processed by the first vector data processing device shown in FIG. 1 is based on the assumption that the resources of the PDI operation units 0 and 1 are not used in the preceding instruction.
The addition instruction is assigned to PDI0Xi, and the subsequent multiplication instruction is assigned to the same PDI0Ni because of the chaining relationship with the addition instruction. Further, the following multiplication instruction is executed by the PDI operator 0
Is busy, assign to PDI1Xi, and since the subsequent addition instruction is chained with the multiplication instruction, PDI1Xi
Assign to Ni. As described above, when the continuous operation instruction sequences are in a chaining relationship with each other, these two operation instruction sequences are assigned to the instruction queue of the same resource. The instruction sequence read from the instruction buffer is accumulated in the instruction queue provided for the resource.However, if there is no chaining relationship between the preceding and succeeding instructions, for example, the preceding The instruction will be placed in the opposite computational resource instruction queue to which it was assigned.

Upon activation of the addition instruction stored in PDI0Xi42, the vector control unit 37 gives an instruction to simultaneously read VR1 and VR2 to the vector register 33 and an instruction to select data of VR1 and VR2 to the first operand path and the second operand path. SEL36, and an instruction to add data from the first operand path and the second operand path to the PDI operator 0. Further, an instruction to select the pipeline adder result path 18 of the PDI operation unit 0 to VR0 is given to the DIST 35, and an instruction to write to VR0 is given to the vector register 33.

The multiplication instruction stored in PDI0Ni41 is generated after the sum of the operation stage time of the pipeline adder 1 and the travel time of the feedback path 11 since the start of the addition instruction.
Is activated. In the activation control, a counter operation is performed using a counting circuit that increments by one every operation cycle at the same time as the instruction activation, and the release count value (operation stage time + feedback path travel time) and the count value registered in advance are counted. Perform when they match. Upon activation of the multiplication instruction, the vector control unit 37
An instruction to read VR4 is given to the vector register 33, and an instruction to select data from VR4 to the third operand path 17 is given by SE.
L36, and instructs the PDI calculator 0 to multiply the data from the third operand path 17 and the feedback path 11. Further, an instruction to select the pipeline multiplier result path 19 of the PDI operator 0 to VR3 is given to the DIST 35, and the VR3
Is given to the vector register 33. As a result, the addition instruction and the multiplication instruction are overlapped and processed by the PDI calculator 0.

On the other hand, activation of the multiplication instruction stored in PDI1Xi40
If the arithmetic unit 1 is not in the busy state, the processing is performed simultaneously with the storage. That is, the operation is performed in the next operation cycle after the instruction is stored in PDI0Ni. By the activation, the vector control unit 37
Sets the vector register to read VR6 and VR7 simultaneously.
33, and an instruction to select the data of VR6 and VR7 to the fourth operand path and the fifth operand path is given to SEL36.
The PDI operation unit 1 is instructed to multiply and execute data from the fourth and fifth operand paths. Furthermore, P
VR5 of pipeline multiplier result path 32 of DI operation unit 1
Is given to the DIST 35, and an instruction to write to VR5 is given to the vector register 33.

The addition instruction stored in PDI1Ni39 is activated after a total time of the operation stage time of the pipeline multiplier 5 and the travel time of the feedback path 25 has elapsed since the activation of the multiplication instruction. Upon activation of the addition instruction, the vector control unit 37 gives a read instruction of VR9 to the vector register 33, gives an instruction to select the data of VR9 to the sixth operand path 30 to the SEL, and outputs the instruction from the sixth operand path 3 and the feedback path 25. Is given to the PDI calculator 1. Further, an instruction to select the pipeline adder result path 31 of the PDI operation unit 1 to VR8 is issued by DIST35.
And the instruction to write the multiplication result in VR8 is given to the vector register 33. As a result, the multiplication instruction and the addition instruction are overlapped and processed by the PDI calculator 1.

In this way, in the case where the preceding operation instruction and the following operation instruction are in a chaining relationship, the PDI operation unit forms a pair via the feedback path while writing the pipeline operation result of the preceding operation instruction to the vector register. Operands can be supplied to the other pipeline arithmetic unit. In other words, one PDI operation unit can simultaneously execute up to two operation instructions having a chaining relationship in parallel. This process is called a macro chaining mode. In the macro chaining mode, the result of the preceding operation is written to the vector register, so that the result of the operation can be chained with another resource that can operate in parallel. For example, in the operation instruction sequence case shown in FIG. 5, Vadd VR0 VR1 VR2⇒VR1 + VR2 = VR0 Vmlt VR3 VR4 VR0⇒VR4 × VR0 = VR3 Vmlt VR5 VR6 VR0⇒VR6 × VR7 = VR5, which is shown in FIG. 8 of the conventional example. In the vector data processing device, as shown in FIG. 5 (g), the instruction sequence is subjected to chaining processing via separate vector processing resources via the vector register, so that the operation instruction becomes resource busy and the processing is delayed. However, in the first vector data processing device according to the present invention, as shown in FIG. 5 (h), while performing macro-chaining mode processing using one PDI operator between the instruction sequence and the other PDI processing unit, The processing time can be shortened because the overlap with the instruction sequence can be performed using the arithmetic unit. When the instruction is changed to the VR0 store instruction, a chaining process for storing the result of the preceding operation in the main memory is also possible, and the same effect can be obtained. In addition, the above-mentioned operation instruction sequence
FIG. 3 (b) shows a series of processing relationships. As a comparison, FIG. 3 (a) shows the processing relationship when executing the same instruction sequence in the conventional vector data processing apparatus shown in FIG.
Shown in In the first vector data processing device according to the present invention, as shown in FIG. 3 (b), the calculation processing time can be reduced.

Next, an embodiment of the second vector data processing device according to the present invention will be described.

FIG. 9 shows a configuration excluding the control unit of the vector data processing device according to the present embodiment. In the second vector data processing device, a macro instruction in which addition and multiplication are arbitrarily combined can be processed in parallel by each of the complex arithmetic units. Although the macro operation instruction has not been described in the first vector data processing device, the macro operation instruction can be similarly executed in the first vector data processing device.

This embodiment is different from the first embodiment in that a means for selecting one of the outputs of the adder and the multiplier in the complex arithmetic unit is provided. This makes it possible to halve the number of result paths for returning operation results to the vector register and to simplify the configuration of the DIST as compared with the first embodiment. And the operation will be described.

The vector data processing device of FIG. 9 is similar to the vector data processing device of FIG.
, Scalar data buffers 430a to 430c, SEL432, DI
ST431, No. 0 compound arithmetic unit 403 as an arithmetic resource, and 1
It is composed of a number composite arithmetic unit 406. Although not shown, a load pipeline for supplying operands from the main memory to the vector register and a store pipeline for storing data from the vector register to the main memory are provided, and each is controlled as a resource from the control system. .

The No. 0 complex arithmetic unit 403 (hereinafter referred to as PDI arithmetic unit 0)
Vector registers and scalar data are stored in vector registers
492a to 429h and first operand path 414, second operand path 415, third operand path 416 read from scalar buffers 430a to 430c, pipeline adder 401, pipeline multiplier 402, and pipeline adder 401. A path 411 that feeds back the operation result and is used as an operand of the pipeline adder 401 and the pipeline multiplier 402, and a feedback path that feeds back the operation result of the pipeline multiplier 402 and the operand of the pipeline adder 401 and the pipeline multiplier 402. Path 412, a first operand path 414, a feedback path 411, and a selector 407 that selects input data from the feedback path 412 by an instruction and uses the data as augend data of the pipeline adder 401, and a second operand path 4
A selector 408 that selects input data from the fifteenth, third operand path 416, feedback path 411, and feedback path 412 by an instruction and uses it as addend data of the pipeline adder 401; a first operand path 414 and a feedback path 411; A selector 409 that selects input data from the feedback path 412 by an instruction and uses the data as multiplicand data of the pipeline multiplier 402, a second operand path 415, and a third
A selector 410 that selects input data from the operand path 416, the feedback path 411, and the feedback path 412 by an instruction and uses the data as multiplication data of the pipeline multiplier 402.
And a selector 413 for selecting the operation result feedback path 411 of the pipeline adder 401 and the operation result feedback path 412 of the pipeline multiplier 402, and a result path 417 for writing the operation result of the PDI operation unit 0 to the vector register. Is done.

The first composite computing unit 406 (hereinafter referred to as PDI computing unit 1)
Vector registers and scalar data are stored in vector registers
429a to 429h and fourth operand path 425, fifth operand path 426, sixth operand path 427, read from scalar buffers 430a to 430c, pipeline adder 404, pipeline multiplier 405, and pipeline adder 404. A path 422 that feeds back the operation result and is used as an operand of the pipeline adder 404 and the pipeline multiplier 405, and an operand of the pipeline adder 404 and the pipeline multiplier 405 that feeds back the operation result of the pipeline multiplier 405. 422, a selector 418 that selects input data from the fourth operand path 425, the feedback path 422, and the feedback path 423 by an instruction and uses it as addend data of the pipeline adder 404, and a fifth operand path 4
A selector 419 that selects input data from the 26, sixth operand path 427, feedback path 422, and feedback path 423 by an instruction and uses it as addend data of the pipeline adder 404; a fourth operand path 425 and a feedback path 422; A selector 420 which selects input data from the feedback path 423 by an instruction and sets the data as multiplicand data of the pipeline multiplier 405, a fifth operand path 426 and a sixth
A selector 421 that selects input data from the operand path 427, the feedback path 422, and the feedback path 423 by an instruction and uses the data as multiplier data of the pipeline multiplier 405.
And a selector 424 for selecting an operation result feedback path 422 of the pipeline adder 404 and an operation result feedback path 423 of the pipeline multiplier 405, and a result path 428 for writing the operation result of the PDI operation unit 1 to a vector register. Is done.

The configuration of the instruction control unit of the vector data processing device according to the present embodiment is the same as that of the first vector data
As shown in the figure, the description is omitted.

FIG. 11 is a diagram for explaining an example of an operation instruction executed by one instruction in the second vector data processing device according to the present invention, using the operation instruction sequence shown in FIG. 3 as a macro instruction.

In the figure, the operation instructions are as follows: Vaddmlt VR3 VR4 VR1 VR2 ⇒ (VR1 + VR2) × VR4 = VR3. Although not shown, the operation instruction sequence shown in FIG. 3 is also Vmltadd VR8 VR9 VR6 VR7 ⇒ (VR6 × VR7｝). + VR9 = VR8 and can be replaced by a macro instruction.
It is assumed that both macro instructions are sequentially stored in the instruction buffer 38 in the instruction control unit 37 shown in FIG. The operation when the instruction sequence is processed by the second vector data processing device shown in FIG.
Assuming that the resources of the PDI computing units 0 and 1 are not used, a macro instruction is assigned to PDI0Xi, and the subsequent macro instruction is assigned to PDI1Xi because the PDI computing unit 0 is in the busy state. In this way, the operation instruction sequence is assigned to the instruction queue so as to perform operation scheduling using the operation resources alternately.

Upon activation of the macro instruction stored in PDI0Xi42, the vector control unit 37 gives an instruction to simultaneously read VR1, VR2, and VR4 to the vector registers 429a to 429h, and outputs VR1, VR2, and VR4.
SE to select the first data into the first operand path, the second operand path, and the third operand path, respectively.
L432, the data from the first operand path and the data from the second operand path are added and executed, and the data obtained from the feedback path 411 and the third operand path 416 are added.
Is given to the PDI calculator 0.
At this time, as shown in FIG.
A delay circuit 501 is provided for an operand input to the PDI calculator 0, and a delay control instruction is issued to delay the preceding operation, in this case, the operation stage time of the addition processing. Thus, the operation of the head vector data of the addition result and the head element of the vector data input from the third operand path can be started simultaneously. Although not shown, the delay circuit 501
A configuration similar to that described above is also provided in the sixth operand path 427. Incidentally, this delay processing can be performed by a method of delaying the vector register read instruction to the third operand path and the sixth operand path using a release count circuit as in the first vector data processing device. Further, the control unit 37 gives to the selector 413 an instruction to select the output result of the pipeline multiplier 402 of the PDI arithmetic unit 0 and send it to the result path 417, and gives an instruction to select the result path 417 of the PDI arithmetic unit 0 to VR3 to the DIST 431. And an instruction to write the macro operation result to VR3 is given to the vector registers 429a to 429h. As a result, the macro instruction is processed by the PDI calculator 0.

On the other hand, the activation of the macro instruction stored in PDI1Xi40
If the I operation unit 1 is not in the busy state, the operation is performed simultaneously with the storage. That is, it is performed in the next operation cycle after the storage of the macro instruction in the PDI0Xi. With this activation, the vector control unit 37 gives an instruction to simultaneously read VR6, VR7, and VR9 to the vector registers 429a to 429h, and stores the data of VR1, VR2, and VR4 in the fourth operand path, the fifth operand path, and the sixth operand, respectively. An instruction to select the path is given to the SEL 432, the data from the fourth and fifth operand paths are multiplied and executed, and the data from the feedback path 23, which is the result of the multiplication, and the delayed sixth operand path 42
The instruction to add the data from 7 is given to the PDI calculator 1.
Further, the control unit 37 controls the pipeline adder 4 of the PDI operation unit 1.
04 The instruction to select the output result and send it to the result path 428 is given to the select 424, and the result path 428 of the PDI operator 1 is set to V
The instruction to select is given to R8 to DIST 431, and the instruction to write the macro operation result to VR8 is given to vector registers 429a to 429h. As a result, the macro instruction is processed by the PDI calculator 1.

As described above, in the second vector data processing apparatus according to the present invention, up to two macro operation instructions in which addition and multiplication are arbitrarily combined can be executed simultaneously in parallel, and the operation processing time can be reduced.

By the way, the first and second vector data processing devices
Since one scalar data buffer can be connected to an arbitrary operand path, flexible arithmetic processing for assigning scalar data and vector data to an arbitrary operand is possible. Further, a feedback path of the PDI operation unit is provided for each of the addition and multiplication pipeline operation units, and the feedback path can be selected as both operands of each of the pipeline operation units. , C, the following arithmetic processing can be executed by one macro operation instruction.

(1) A ± B (2) A × B (3) (A ± B) × C (4) (A × B) ± C (5) (A ± B) Further, when the first and second vector data processing devices according to the present invention are configured by combining an element parallel method of processing a plurality of vector elements in parallel in one operation cycle, for example, in the case of four-element parallel processing, A set of a plurality of vector registers and two PDI operators for processing the 4i (i = 0, 1, 2...) Element, a set for processing the 4i + 1 element, a set for processing the 4i + 2 element, and a 4i + 3 element It is composed of independent sets for processing, and each set can process one element in one operation cycle.
Since the operation parallel processing of four elements is possible, higher processing performance can be obtained.

Further, the first and second vector data processing systems according to the present invention, particularly the macro chaining mode system, use a microprocessor in which registers such as a vector register and a scalar register and a plurality of pipeline arithmetic units are integrated on one chip. For example, the travel time can be reduced, which is useful.

[Effects of the Invention] As described above, according to the present invention, a vector data processing device can be provided with the following effects.

(1) In the case where the same type of operation instruction continues, the operation resource bottleneck can be reduced.

(2) Similarly, since there are two sets of composite arithmetic units having the same configuration including an adder and a multiplier, scheduling control of arithmetic instructions becomes easy.

(3) Since three operand paths are provided in each compound operation unit, compound operation using all vector operands can be performed.

(4) In addition to (3), a feedback path is provided to feed back the outputs of the adders and multipliers of each complex arithmetic unit to the inputs of the adders and multipliers. It is possible to perform a composite operation by arbitrarily combining and addition.

(5) As described above, it is possible to minimize an increase in the amount of hardware of the data path and the control logic, and to shorten the processing time.

[Brief description of the drawings]

FIG. 1 is a schematic block diagram of a data system of a first vector data processing device according to an embodiment of the present invention, FIG. 2 is a schematic block diagram of an instruction control unit of the vector data processing device according to the present invention, and FIG. FIG. 3A is a timing chart showing a processing concept of a conventional vector data processing apparatus, FIG. 3B is a timing chart showing a processing concept of a first vector data processing apparatus according to the present invention, and FIG. , (E) are timing diagrams showing the processing concept of the conventional vector data processing device, and FIGS. 4 (d), (f) are the first and second vector data processing devices according to the present invention and the operation of the prior art. Diagram showing the processing concept of the device parallel system vector data processing device,
FIG. 5 (g) is a timing chart showing the processing concept of the conventional vector data processing apparatus, and FIG. 5 (h) is a timing chart showing the macro chaining mode processing concept of the first vector data processing apparatus according to the present invention. FIG. 5 (i) is a timing chart showing the processing concept of a conventional vector data processing apparatus which cannot execute the macro instruction processing of all vector operands, and FIG. 6 is a conventional vector data processing apparatus which tends to become an operation resource bottleneck. FIG. 7 is a block diagram showing a conventional vector data processing device which cannot perform macro instruction processing of all vector operands, FIG. 8 is a block diagram showing a conventional arithmetic unit parallel system vector data processing device, FIG. 9 is a block diagram of a second embodiment of the vector data processing apparatus of the present invention, and FIG.
FIG. 11 is a block diagram showing an operand delay circuit of the vector data processing device shown in FIG. 11, and FIG. 11 is a timing chart showing an example of the processing concept of the second vector data processing device according to the present invention. 1,4... Pipeline adder, 2,5... Pipeline multiplier, 3... 0 complex computing unit (PDI computing unit 0), 6.
No. compound arithmetic unit (PDI arithmetic unit 1), 7 to 10 ... selector, 1
1,12 ... feedback path, 13,14 ... output circuit, 15
... First operand path, 16... Second operand path,
17… 3rd operand pass, 18,19 …… Result pass, 2
0 to 23: Selector, 24, 25 ... Feedback path, 2
6,27 …… Output circuit, 28 …… Fourth operand path, 29 ……
5th operand path, 30 ... 6th operand path, 31,3
2 ... Result path, 33a-33h, 33 ... Vector register, 34a-34c ... Scalar data buffer, 35 ... DIST,
36 ... SEL, 37 ... Instruction control unit, 38 ... Instruction buffer, 3
9 to 42: instruction queue, 43, 44: control path, 501: delay circuit.

 ────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-64-67678 (JP, A) JP-A-61-62174 (JP, A) JP-A-56-88561 (JP, A) FUJITSU Vol. 41 No. 1P. 3-11 IEEE Int Conf Acoustic Speech Signal Process Vol. 1983 No. 1P. 447−450

Claims (11)

(57) [Claims] A vector data processing apparatus having a vector data buffer for holding a plurality of sets of vector data composed of a plurality of vector elements and performing a vector operation on the vector data held in the approximate vector data buffer. And a total of six operand paths, each of which is provided with three for each of the two composite arithmetic units and provides one input of the corresponding composite arithmetic unit, An adder, a multiplier, a first feedback path for providing the output of the adder as one input of the complex arithmetic unit, and a second feedback path for providing the output of the multiplier as one input of the complex arithmetic unit. A feedback path, i is provided for each of the inputs of the adder and the inputs of the multiplier of the complex arithmetic unit, i is provided for the complex arithmetic unit. A first selection in which two inputs given by two of the three operand paths are two inputs of an adder; and ii, three inputs of the three operand paths provided for the complex operation unit. A second selection of two inputs given by the two operand paths as two inputs of the multiplier; ii.
i, three inputs given by three operand paths provided for the complex arithmetic unit are taken as two inputs of the adder and one input of the multiplier, and one input given by the first feedback path is taken as the multiplier Iv, the three inputs given by the three operand paths provided for the complex arithmetic unit are taken as two inputs of the multiplier and one input of the adder, and And a fourth selection unit that makes one input given by the feedback path as the remaining one input of the adder; and a selection unit that performs at least four selections. 2. A method according to claim 1, further comprising: allocating a preceding operation instruction to a non-busy complex operation unit and allocating a subsequent operation instruction to the other composite operation unit irrespective of the type of the operation instruction. 2. The vector data processing device according to claim 1, further comprising an operation instruction scheduling means for allocating to the operation unit. 3. The arithmetic instruction scheduling means according to claim 1, wherein a register for storing a result of a preceding addition (or multiplication) instruction is designated by a subsequent multiplication (or addition) instruction as the operand register. 3. The vector data processing device according to claim 2, wherein the vector data is assigned to the composite arithmetic unit. 4. The selecting means of each of the compound arithmetic units is configured to execute the above-mentioned operation when a register for storing a result of a preceding addition (or multiplication) instruction is designated by a subsequent multiplication (or addition) instruction as the operand register. The third (or fourth) selection is performed, the operation of the preceding first operation instruction is processed by the adder (or multiplier), and the operation of the subsequent operation instruction is performed by the multiplier (or adder) 2. The vector processing apparatus according to claim 1, wherein the processing is performed. 5. The multi-function device according to claim 3, wherein the operation instruction is a macro operation instruction using a result of preceding addition (or multiplication) as operand data of a subsequent multiplication (or addition). 2. The vector processing device according to claim 1, wherein the selection is performed, the preceding operation is processed by an adder, and the subsequent operation is processed by a multiplier. 6. The method according to claim 1, wherein at a timing when a result of the preceding operation processing is input to the operation unit for performing the subsequent operation processing via the first (or second) feedback path, the operand from the operand path is used for the subsequent operation. 5. The system according to claim 4, further comprising means for delaying the operand itself or an instruction to read the operand so that the operand arrives at a processing unit for processing.
Or the vector data processing device according to 5. 7. The vector data according to claim 1, wherein each of the composite arithmetic units has an operation result path for separately outputting each operation result to the outside of each of the adder and the multiplier. Processing equipment. 8. The vector according to claim 1, wherein each of the composite arithmetic units has an operation result path for selectively outputting one of both operation results to the outside for each of the adder and the multiplier. Data processing device. 9. An element-parallel vector data processing apparatus for processing a plurality of vector elements in parallel in one operation cycle, wherein the apparatus according to claim 1 is employed for at least one element parallel. Processing equipment. 10. The vector data processing apparatus according to claim 1, wherein at least said vector data buffer and said second composite arithmetic unit are constructed in a one-chip microprocessor. 11. A composite operation comprising: a vector data buffer for holding a plurality of sets of vector data composed of a plurality of vector elements; a scalar data buffer for holding a plurality of scalar data; and an adder and a multiplier. And a total of six operand paths for providing vector data or scalar data operands to the corresponding composite arithmetic units, three each for each of the two composite arithmetic units, and the vector data buffer Means for connecting individual read paths of the scalar data buffer to each operand path in response to a program instruction; and, in response to the program instruction, each output of each adder and each multiplier of each of the complex arithmetic units, Means for independently connecting to and writing to a vector data buffer or a scalar data buffer. A first feedback path for providing the output of the adder of the complex arithmetic unit as one operand of the complex arithmetic unit, and the complex feedback of the output of the multiplier of the complex arithmetic unit. A second feedback path provided as one operand of the arithmetic unit, i as the selection of each operand of the adder and each operand of the multiplier of the complex arithmetic unit, i, three operand paths provided for the complex arithmetic unit, Selection, in which the two operands given by the two operand paths are two operands of the adder, and ii, two operand paths of the three operand paths provided for the complex arithmetic unit A second selection in which the two operands given by the above are used as two operands of the multiplier, and iii, A third selection in which the three operands given by the perland path are taken as two operands of the adder and one operand of the multiplier, and one operand given by the first feedback path is taken as the remaining one operand of the multiplier; The three operands provided by the three operand paths provided for the complex arithmetic unit are defined as two operands of the multiplier and one operand of the adder, and one operand provided by the second feedback path is defined as one remaining operand of the adder. A selecting means for performing at least four selections of a fourth selection as an operand in response to a program instruction.