JP2967353B2 - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device

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Publication number
JP2967353B2
JP2967353B2 JP10273156A JP27315698A JP2967353B2 JP 2967353 B2 JP2967353 B2 JP 2967353B2 JP 10273156 A JP10273156 A JP 10273156A JP 27315698 A JP27315698 A JP 27315698A JP 2967353 B2 JP2967353 B2 JP 2967353B2
Authority
JP
Japan
Prior art keywords
well
type well
photoresist
forming
type
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP10273156A
Other languages
Japanese (ja)
Other versions
JPH11163164A (en
Inventor
ゼ・キョン・アン
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
ERU JII SEMIKON CO Ltd
Original Assignee
ERU JII SEMIKON CO Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by ERU JII SEMIKON CO Ltd filed Critical ERU JII SEMIKON CO Ltd
Publication of JPH11163164A publication Critical patent/JPH11163164A/en
Application granted granted Critical
Publication of JP2967353B2 publication Critical patent/JP2967353B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本発明は半導体デバイスの製
造方法に係り、特にＣＭＯＳにおいて互いに異なるタイ
プのウェル形成時のラッチアップ特性を改善することが
できる半導体デバイスの製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a semiconductor device capable of improving latch-up characteristics when different types of wells are formed in CMOS.

【０００２】[0002]

【従来の技術】一般に、ＣＭＯＳとはｐチャネルＭＯＳ
ＦＥＴとｎチャネルＭＯＳＦＥＴを一つのチップに構成
して相補的に動作させるようにしたものである。ＣＭＯ
Ｓはイオン注入技術の実用化によって可能になり、消費
電力が低く、バイポーラデバイスに近い高速動作が可能
でメガビット級が主流となっている。2. Description of the Related Art Generally, CMOS is a p-channel MOS.
The FET and the n-channel MOSFET are configured on a single chip to operate complementarily. CMO
S is made possible by the practical use of ion implantation technology, has low power consumption, can operate at a high speed close to that of a bipolar device, and is of the megabit class.

【０００３】以下、図１を参照して従来の半導体デバイ
スの製造方法について説明する。図１ａに示すように、
半導体基板１の全面に第１フォトレジストを堆積して、
露光及び現像工程によって選択的に第１フォトレジスト
を除去して、半導体基板１の表面が露出されるように第
１フォトレジストパターン２を形成する。その第１フォ
トレジストパターン２をマスクとして不純物イオン注入
でｎ型ウェル３を形成する。この時、それぞれの目的に
よってエネルギーと不純物量を調節して複数のｎ型ウェ
ル３を形成する。不純物としては燐Ｐを利用する。複数
のｎ型ウェル３は水平配置である。Hereinafter, a conventional method for manufacturing a semiconductor device will be described with reference to FIG. As shown in FIG. 1a,
Depositing a first photoresist on the entire surface of the semiconductor substrate 1;
The first photoresist is selectively removed by an exposure and development process to form a first photoresist pattern 2 such that the surface of the semiconductor substrate 1 is exposed. Using the first photoresist pattern 2 as a mask, an n-type well 3 is formed by impurity ion implantation. At this time, a plurality of n-type wells 3 are formed by adjusting the energy and the amount of impurities according to each purpose. Phosphorus P is used as an impurity. The plurality of n-type wells 3 are arranged horizontally.

【０００４】続いて、図１ｂに示すように、第１フォト
レジストパターン２を除去した後、全面に第２フォトレ
ジストを堆積してから、露光及び現像工程によって選択
的に第２フォトレジストをｎ型ウェル３領域上側にだけ
残るように除去して第２フォトレジストパターン４を形
成する。その第２フォトレジストパターン４をマスクと
して不純物イオンを注入してｐ型ウェル５を形成する。
この時、それぞれの目的によってエネルギーと不純物量
を調節して複数のｐ型ウェル５層を形成する。不純物は
ホウ素Ｂを用いる。ｐ型ウェル５は水平に複数形成され
る。Then, as shown in FIG. 1B, after the first photoresist pattern 2 is removed, a second photoresist is deposited on the entire surface, and then the second photoresist is selectively removed by an exposure and development process. The second photoresist pattern 4 is formed by being removed so as to remain only above the mold well 3 region. Using the second photoresist pattern 4 as a mask, impurity ions are implanted to form a p-type well 5.
At this time, a plurality of five p-type well layers are formed by adjusting the energy and the impurity amount according to each purpose. Boron B is used as an impurity. A plurality of p-type wells 5 are formed horizontally.

【０００５】続いて、図１ｃに示すように、第２フォト
レジストパターン４を除去した後、ｎ型ウェル３とｐ型
ウェル５を熱処理する。この時、ｎ型ウェル３の不純物
とｐ型ウェル５の不純物が互いに相殺されて、ウェルジ
ャンクション６は垂直方向に形成されず、深さによって
ｎ型ウェル３やｐ型ウェル５の方向に移動して図示のよ
うに不均一に形成される。Subsequently, as shown in FIG. 1C, after removing the second photoresist pattern 4, the n-type well 3 and the p-type well 5 are heat-treated. At this time, the impurities in the n-type well 3 and the impurities in the p-type well 5 cancel each other, and the well junction 6 is not formed in the vertical direction, but moves in the direction of the n-type well 3 or the p-type well 5 depending on the depth. And is formed non-uniformly as shown.

【０００６】[0006]

【発明が解決しようとする課題】しかし、上記のような
従来の半導体デバイスの製造方法においては次のような
問題点があった。ｎ型ウェルとｐ型ウェルはそれぞれの
目的によってエネルギーと不純物量が異なるので、ウェ
ルジャンクションは垂直方向に直線状にならず、深さに
よってｎ型ウェルやｐ型ウェルの方向に移動して不均一
に形成される。従って、正確に垂直なウェルジャンクシ
ョンが定められない。ラッチ−アップ特性を保持させる
ためウェルジャンクション付近のウェルドーピング濃度
を高くすべきであるが、従来技術のドーピング濃度は、
ｎ型不純物とｐ型不純物が横方向に拡散し、互いに相殺
されるので濃度が低下する。その結果ウェル抵抗が増加
し、ラッチアップ特性が低下する。本発明はかかる従来
の問題点を解決するためのもので、その目的は、ラッチ
−アップ特性と、ウェルとウェルの隔離特性とを改善す
ることができるＣＭＯＳ半導体デバイスの製造方法を提
供することである。However, the conventional method for manufacturing a semiconductor device as described above has the following problems. Since the n-type well and the p-type well have different energies and impurity amounts according to their respective purposes, the well junction does not become linear in the vertical direction, but moves in the direction of the n-type well or the p-type well depending on the depth and becomes uneven. Formed. Therefore, an exact vertical well junction cannot be defined. The well doping concentration near the well junction should be high in order to maintain the latch-up characteristic, but the doping concentration in the prior art is
The n-type impurity and the p-type impurity diffuse in the horizontal direction and cancel each other out, so that the concentration decreases. As a result, the well resistance increases and the latch-up characteristics deteriorate. SUMMARY OF THE INVENTION The present invention has been made to solve the conventional problems, and has as its object to provide a method of manufacturing a CMOS semiconductor device capable of improving latch-up characteristics and well-to-well isolation characteristics. is there.

【０００７】[0007]

【課題を解決するための手段】本発明は、二つのウェル
が接合する位置であるウェルジャンクション位置を定
め、そのウェルジャンクションの両側のウェルとウェル
との間に未注入領域を形成することを特徴とするもので
ある。より具体的には、本発明方法は、二つのウェルが
接合するウェルジャンクション位置を定めて、ウェルジ
ャンクション位置から一定距離離して半導体基板に第１
導電形ウェルを形成し、ウェルジャンクション位置を間
に挟んで第１導電形ウェルと反対側にウェルジャンクシ
ョンから一定距離離して第２導電形ウェルを形成するこ
とを特徴とする。The present invention is characterized in that a well junction position where two wells are joined is defined, and an unimplanted region is formed between the wells on both sides of the well junction. It is assumed that. More specifically, the method of the present invention defines a well junction position where two wells are joined, and a first distance is provided to the semiconductor substrate at a certain distance from the well junction position.
A conductive type well is formed, and a second conductive type well is formed at a predetermined distance from the well junction on a side opposite to the first conductive type well with a well junction position interposed therebetween.

【０００８】[0008]

【発明の実施の形態】以下、図２を参照して本発明実施
形態の半導体デバイスの製造方法について詳しく説明す
る。まず、図２ａに示すように、半導体基板２０内に二
つのウェルが接合する箇所であるウェルジャンクション
位置を定めた後、基板２０の全面に第１フォトレジスト
を堆積してから、露光及び現像工程によってウェルジャ
ンクション位置から一方の側へ一定距離離れた位置で第
１フォトレジストを除去して、半導体基板１の表面が露
出されるように第１フォトレジストパターン２１を形成
する。その第１フォトレジストパターン２１をマスクと
して不純物イオンを注入してｎ型ウェル２２を形成す
る。すなわち、フォトレジストパターン２１はウェルジ
ャンクション位置からイオン注入領域まで一定距離のび
ている。このとき、それぞれの目的によって、従来同様
エネルギーと不純物量を調節して複数のｎ型ウェル２２
を形成する。不純物は燐Ｐを用いる。このように、第１
フォトレジストパターン２１はウェルジャンクション位
置からイオン注入領域まで伸びており、そのパターンを
マスクとして不純物イオンを注入するので、ウェルジャ
ンクション位置からある範囲で不純物イオンが注入され
ない未注入領域２５が形成される。逆に言えば、イオン
の横方向への拡散を考慮してなおかつ未注入領域２５が
残る程度にフォトレジストパターン２１をウェルジャン
クション位置からイオン注入領域へのばす。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a method for manufacturing a semiconductor device according to an embodiment of the present invention will be described in detail with reference to FIG. First, as shown in FIG. 2A, a well junction position where two wells are joined in a semiconductor substrate 20 is defined, a first photoresist is deposited on the entire surface of the substrate 20, and then an exposure and development process is performed. As a result, the first photoresist is removed at a position away from the well junction position to one side by a certain distance, and the first photoresist pattern 21 is formed so that the surface of the semiconductor substrate 1 is exposed. Using the first photoresist pattern 21 as a mask, impurity ions are implanted to form an n-type well 22. That is, the photoresist pattern 21 extends a certain distance from the well junction position to the ion implantation region. At this time, the energy and the amount of impurities are adjusted according to the respective purposes as in the conventional case, and the plurality of n-type wells 22 are formed.
To form As the impurity, phosphorus P is used. Thus, the first
The photoresist pattern 21 extends from the well junction position to the ion-implanted region. Impurity ions are implanted using the pattern as a mask, so that an unimplanted region 25 in which impurity ions are not implanted is formed in a certain range from the well junction position. Conversely, the photoresist pattern 21 is extended from the well junction position to the ion-implanted region so as to leave the unimplanted region 25 in consideration of the diffusion of ions in the horizontal direction.

【０００９】続いて、図２ｂに示すように、第１フォト
レジストパターン２１を除去した後、全面に第２フォト
レジストを堆積してから、露光及び現像工程によって前
記と同様にウェルジャンクション位置から新しいイオン
注入領域にまでのびるように選択的に第２フォトレジス
トを除去して、第２フォトレジストパターン２３を形成
する。その第２フォトレジストパターン２３をマスクと
して不純物イオンを注入してｐ型ウェル２４を形成す
る。前記同様ウェルジャンクション位置からある距離イ
オンが注入されない未注入領域２５が形成される。この
ｐ型不純物イオン注入は、それぞれの目的によってエネ
ルギーと不純物量を調節する。不純物はホウ素Ｂを用い
る。Subsequently, as shown in FIG. 2B, after the first photoresist pattern 21 is removed, a second photoresist is deposited on the entire surface. The second photoresist is selectively removed so as to extend to the ion-implanted region, and a second photoresist pattern 23 is formed. Using the second photoresist pattern 23 as a mask, impurity ions are implanted to form a p-type well 24. An unimplanted region 25 where ions are not implanted at a certain distance from the well junction position is formed in the same manner as described above. In this p-type impurity ion implantation, the energy and the amount of impurities are adjusted depending on the purpose. Boron B is used as an impurity.

【００１０】この２度のイオン注入によって、結局ウェ
ルジャンクション位置の両側に、ある幅の未注入領域２
５が形成される。イオンの横方向への不均一な拡散によ
ってその幅は正確には一定ではないが、ほぼ一定に制御
することができる。続いて、第２フォトレジストパター
ン２３を除去して、図２ｃに示すように、ｎ型ウェル２
２及びｐ型ウェル２４に熱処理拡散工程を実施す。この
熱拡散によってそれぞれの注入された不純物イオンが横
方向にも拡散され、ｎ型ウェル２２とｐ型ウェル２４が
接合し、ウェルジャンクションが垂直に形成される。[0010] By the two ion implantations, an unimplanted region 2 having a certain width is formed on both sides of the well junction position.
5 are formed. Due to the non-uniform diffusion of ions in the lateral direction, their width is not exactly constant, but can be controlled to be almost constant. Subsequently, the second photoresist pattern 23 is removed, and as shown in FIG.
A heat treatment diffusion step is performed on the second and p-type wells 24. Due to this thermal diffusion, each implanted impurity ion is also diffused in the lateral direction, the n-type well 22 and the p-type well 24 are joined, and a well junction is formed vertically.

【００１１】図３はマスクによるウエルを形成し、熱処
理で拡散した後のそれぞれの領域での特定の位置でのウ
ェル濃度のばらつきを示すグラフであり、図４は基本的
には図３と同じで、マスクによって形成させた未注入領
域によるウェルジャンクションが形成される位置のばら
つきを示すグラフである。横軸の０がジャンクション位
置でその右側がｎ型ウエルのそこからの距離、左側がｐ
型ウエルジャンクション位置からの距離を示す。単位は
μｍである。なお、濃度測定位置は任意に選んだ一定の
位置である。濃度はそれぞれ最大濃度値に対して相対値
で正規化した値である。半導体基板にｎ型ウェル及びｐ
型ウェルの形成の際、図３に示すように、従来はＰ+と
Ｂ+の不純物が互いに相殺されて特定の深さでばらつき
が多くなる。一方、マスクを利用してＰ+とＢ+の不純物
注入時、不純物が注入されない０．２或いは０．４の未
注入領域を持つ場合にはばらつきが少なく、したがって
安定的な垂直プロファイルを得る。FIG. 3 is a graph showing variations in well concentration at specific positions in respective regions after a well is formed by a mask and diffused by heat treatment. FIG. 4 is basically the same as FIG. 4 is a graph showing a variation in a position where a well junction is formed due to an unimplanted region formed by a mask. 0 on the horizontal axis is the junction position, the right side is the distance from the n-type well, and the left side is p.
Indicates the distance from the mold well junction position. The unit is μm. The concentration measurement position is a fixed position arbitrarily selected. Each density is a value normalized by a relative value with respect to the maximum density value. N-type well and p-type semiconductor substrate
In forming the mold well, as shown in FIG. 3, in the related art, the impurities of P + and B + cancel each other, and the dispersion increases at a specific depth. On the other hand, when using a mask to implant P + and B + impurities, if there is a 0.2 or 0.4 non-implanted region into which the impurity is not implanted, there is little variation and therefore a stable vertical profile is obtained.

【００１２】さらに詳しく説明すると、図４に示すよう
に、ｐタイプのドーピング濃度Ｎａ（ｘ）＝Ｎａ０（ｘ
≦−ｘｕ）と、Ｎａ（ｘ）＝Ｎａ０×ｅｘｐ（−（ｘ＋
ｘｕ）2／（２σ＿ｐ2））（ｘ＞−ｘｕ）であり、ｎタ
イプのドーピング濃度Ｎｄ（ｘ）＝Ｎｄ０（ｘ≧＋ｘ
ｕ）と、Ｎｄ（ｘ）＝Ｎｄ０×ｅｘｐ（−（ｘ−ｘｕ）
2／（２σ＿ｎ2））（ｘ＜ｘｕ）である。この時、前記
σ＿ｐは０．８であり、σ＿ｎは０．５であり、ｘｕは
未注入領域である。そして、Ｎａ０はｐ型ウェルのドー
ピング基準であり、Ｎｄ０はｎ型ウェルのドーピング基
準である。従って、未注入領域無しでｎ型ウェル及びｐ
型ウェルを形成すると、Ｎａ（ｘ＝ｘｊ−０．２）＝
０．４５、Ｎａ（ｘ＝ｘｊ−０．４）＝０．７５とな
り、Ｎｄ（ｘ＝ｘｊ＋０．２）＝０．４５、 Ｎｄ（ｘ
＝ｘｊ＋０．４）＝０．９となって、ウェルジャンクシ
ョンがｘ＝−０．６に形成される。そして、０．６の未
注入領域を持つｎ型ウェル及びｐ型ウェルを形成時する
と、Ｎａ（ｘ＝ｘｊ−０．２）＝０．４５、Ｎａ（ｘ＝
ｘｊ−０．４）＝０．７となり、Ｎａ（ｘ＝ｘｊ＋０．
２）＝０．６、Ｎａ（ｘ＝ｘｊ＋０．４）＝１．１とな
って、ウェルジャンクションがｘ＝−０．２に形成され
る。また、０．８の未注入領域を持つｎ型ウェル及びｐ
型ウェルを形成すると、Ｎａ（ｘ＝ｘｊ−０．２）＝
０．６、Ｎａ（ｘ＝ｘｊ−０．４）＝０．８となり、Ｎ
ｄ（ｘ＝ｘｊ＋０．２）＝０．６、Ｎｄ（ｘ＝ｘｊ＋
０．４）＝１．２となって、ウェルジャンクションがｘ
＝０に形成される。そして、１．２の未注入領域を持つ
ｎ型ウェル及びｐ型ウェルを形成すると、Ｎａ（ｘ＝ｘ
ｊ−０．２）＝０．１９、Ｎａ（ｘ＝ｘｊ−０．４）＝
０．３となり、Ｎｄ（ｘ＝ｘｊ＋０．２）＝０．２、Ｎ
ｄ（ｘ＝ｘｊ＋０．４）＝０．５となって、ウェルジャ
ンクションがｘ＝＋０．２に形成される。従って、０．
８の未注入領域を持つｎ型ウェル及びｐ型ウェルを形成
する場合、ウェルジャンクションが０に近く、ウェルジ
ャンクションの近所で高い値のドーピングを示すので、
最も優れた特性をあらわす。結果的に、垂直ウェルドー
ピングの特性長さ程度距離だけウェルマスクを利用して
未注入領域させたときに生成されるウェルジャンクショ
ン及びラッチ−アップ特性面で最適の模様を持つように
なる。More specifically, as shown in FIG. 4, a p-type doping concentration Na (x) = Na0 (x
≦ −xu) and Na (x) = Na0 × exp (− (x +
xu) 2 / (2σ_p 2 )) (x> −xu), and an n-type doping concentration Nd (x) = Nd0 (x ≧ + x
u) and Nd (x) = Nd0 × exp (− (x−xu)
2 / (2σ_n 2 )) (x <xu). At this time, σ_p is 0.8, σ_n is 0.5, and xu is a non-implanted region. Na0 is a doping standard for the p-type well, and Nd0 is a doping standard for the n-type well. Therefore, the n-type well and the p-type
When a mold well is formed, Na (x = xj-0.2) =
0.45, Na (x = xj-0.4) = 0.75, Nd (x = xj + 0.2) = 0.45, Nd (x
= Xj + 0.4) = 0.9, and a well junction is formed at x = -0.6. Then, when forming an n-type well and a p-type well having a non-implanted region of 0.6, Na (x = xj−0.2) = 0.45 and Na (x =
xj−0.4) = 0.7, and Na (x = xj + 0.
2) = 0.6, Na (x = xj + 0.4) = 1.1, and a well junction is formed at x = −0.2. Also, an n-type well having a non-implanted region of 0.8 and p
When a mold well is formed, Na (x = xj-0.2) =
0.6, Na (x = xj-0.4) = 0.8, and N
d (x = xj + 0.2) = 0.6, Nd (x = xj +
0.4) = 1.2 and the well junction is x
= 0. Then, when an n-type well and a p-type well having a non-implanted region of 1.2 are formed, Na (x = x
j-0.2) = 0.19, Na (x = xj-0.4) =
0.3, Nd (x = xj + 0.2) = 0.2, N
d (x = xj + 0.4) = 0.5, and a well junction is formed at x = + 0.2. Therefore, 0.
When forming an n-type well and a p-type well with 8 unimplanted regions, the well junction is close to 0, indicating high doping in the vicinity of the well junction,
Shows the most excellent properties. As a result, an optimum pattern is obtained in terms of well junction and latch-up characteristics generated when a non-implanted region is formed using a well mask by a distance corresponding to the characteristic length of vertical well doping.

【００１３】[0013]

【発明の効果】以上説明したように、本発明による半導
体デバイスの製造方法においては次のような効果があ
る。ウェルジャンクション位置の左右に一定の幅で不純
物が注入されない未注入領域が形成されるので、従来の
ようにウェルジャンクションの付近の互いに異なるタイ
プの不純物が相殺されて低いドーピング領域が生成され
ることを防止することができるので、ウェル抵抗特性を
安定化させることができる。従って、互いに異なるタイ
プのウェル形成時にラッチ−アップ特性を向上させるこ
とができる。さらに、不純物が注入されない未注入領域
領域が形成されることにより、設計者が望む位置及び深
さ方向に一定の位置に正確なウェルジャンクションを定
めることができる。As described above, the method of manufacturing a semiconductor device according to the present invention has the following effects. Since non-implanted regions are formed on the left and right of the well junction position where no impurity is implanted with a certain width, different types of impurities near the well junction are offset to generate a low doping region as in the related art. As a result, the well resistance characteristics can be stabilized. Therefore, the latch-up characteristics can be improved when forming wells of different types. Furthermore, by forming the non-implanted region region into which the impurity is not implanted, a precise well junction can be defined at a position desired by the designer and at a fixed position in the depth direction.

【図面の簡単な説明】[Brief description of the drawings]

【図１】 従来の半導体デバイスの製造方法を示す工程
断面図。FIG. 1 is a process sectional view showing a conventional method for manufacturing a semiconductor device.

【図２】 本発明実施形態の半導体デバイスの製造方法
を示す工程断面図。FIG. 2 is a process sectional view illustrating the method for manufacturing the semiconductor device of the embodiment of the present invention.

【図３】 マスクによるウェル濃度を示すグラフ。FIG. 3 is a graph showing well concentration by a mask.

【図４】 未注入領域形成によるウェルドーピングの改
善を示すグラフ。FIG. 4 is a graph showing improvement of well doping by forming an unimplanted region.

【符号の説明】[Explanation of symbols]

２０ 半導体基板 ２１ 第１フォトレジストパターン ２２ ｎ型ウェル ２３ 第２フォトレジストパターン ２４ ｐ型ウェル ２５ 未注入領域領域 Reference Signs List 20 semiconductor substrate 21 first photoresist pattern 22 n-type well 23 second photoresist pattern 24 p-type well 25 non-implanted region

フロントページの続き (58)調査した分野(Int.Cl.6，ＤＢ名) H01L 21/8238 H01L 27/092 Continuation of the front page (58) Field surveyed (Int.Cl. 6 , DB name) H01L 21/8238 H01L 27/092

Claims (3)

(57)【特許請求の範囲】(57) [Claims] 【請求項１】 一つの基板に複数のウェルを形成する半
導体デバイスの製造方法において、 二つのウェルを接合させるウェルジャンクション位置を
定めて、そのウェルジャンクションから一定距離離して
半導体基板に第１導電形ウェルを形成する段階と、 ウェルジャンクション位置を中心にして第１導電形ウェ
ルの反対側にウェルジャンクション位置から一定距離離
して第２導電形ウェルを形成する段階とからなることを
特徴とする半導体デバイスの製造方法。In a method of manufacturing a semiconductor device in which a plurality of wells are formed on one substrate, a well junction position for joining two wells is determined, and a first conductivity type is formed on the semiconductor substrate at a predetermined distance from the well junction. Forming a well, and forming a second conductivity type well at a predetermined distance from the well junction position on a side opposite to the first conductivity type well with the well junction position as a center. Manufacturing method. 【請求項２】 第１導電形ウェルを形成する方法は、半
導体基板上に第１フォトレジストを堆積する段階と、 露光及び現像工程によってウェルジャンクション位置か
ら一定距離離して第１フォトレジストを選択的に除去し
て、半導体基板が露出されるように第１フォトレジスト
パターンを形成する段階と、 第１フォトレジストパターンをマスクとして不純物イオ
ン注入を通じて第１導電形ウェルを形成する段階と、 第１フォトレジストパターンを除去する段階とからなる
ことを特徴とする請求項１記載の半導体デバイスの製造
方法。2. A method of forming a first conductivity type well, comprising: depositing a first photoresist on a semiconductor substrate; and selectively exposing the first photoresist at a predetermined distance from a well junction position by exposure and development processes. Forming a first photoresist pattern so that the semiconductor substrate is exposed, forming a first conductivity type well by implanting impurity ions using the first photoresist pattern as a mask, 2. The method according to claim 1, further comprising the step of removing the resist pattern. 【請求項３】 第２導電形ウェルを形成する方法は、半
導体基板上に第２フォトレジストを堆積する段階と、 露光及び現像工程によってウェルジャンクション位置か
ら一定距離離して第２フォトレジストを選択的に除去し
て、第１導電形ウェルと反対側の半導体基板が露出され
るように第２フォトレジストパターンを形成する段階
と、 第２フォトレジストパターンを除去する段階とからなる
ことを特徴とする請求項１記載の半導体デバイスの製造
方法。3. A method of forming a second conductivity type well, comprising: depositing a second photoresist on a semiconductor substrate; and selectively exposing the second photoresist at a predetermined distance from a well junction position by exposure and development processes. Forming a second photoresist pattern so that the semiconductor substrate opposite to the first conductivity type well is exposed, and removing the second photoresist pattern. A method for manufacturing a semiconductor device according to claim 1.
JP10273156A 1997-09-26 1998-09-28 Method for manufacturing semiconductor device Expired - Fee Related JP2967353B2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR49215/1997 1997-09-26
KR1019970049215A KR100249179B1 (en) 1997-09-26 1997-09-26 Method for manufacturing semiconductor device

Publications (2)

Publication Number Publication Date
JPH11163164A JPH11163164A (en) 1999-06-18
JP2967353B2 true JP2967353B2 (en) 1999-10-25

Family

ID=19521794

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10273156A Expired - Fee Related JP2967353B2 (en) 1997-09-26 1998-09-28 Method for manufacturing semiconductor device

Country Status (2)

Country Link
JP (1) JP2967353B2 (en)
KR (1) KR100249179B1 (en)

Also Published As

Publication number Publication date
JPH11163164A (en) 1999-06-18
KR19990026900A (en) 1999-04-15
KR100249179B1 (en) 2000-03-15

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