TW445592B - Design method of transistor in the fabricating process of dynamic random access memory - Google Patents

Abstract

The present invention discloses the method of forming transistor in the fabricating process of dynamic random access memory. This invention provides a metal oxide semiconductor structure, which can reduce P/N junction leakage current and raise the refresh time capability, and at least includes the following steps: providing a semiconductor substrate, which has at least one isolating device and the isolating device defines an adjacent active region on the semiconductor substrate; forming the first photoresist layer on semiconductor substrate and exposing the active region in the first direction; implanting the first conductive ion into semiconductor substrate to form a well region; implanting the second conductive ion into semiconductor substrate to form a field implant region; implanting the third conductive ion into semiconductor substrate to form a punchthrough implant region; removing the first photoresist layer; forming the second photoresist layer and exposing the active region in the second direction, in which the second direction is different from the first direction; implanting the fourth conductive ion to form a threshold implant region; and removing the second photoresist layer.

Description

4 4 5 5 9? _Case No. 89102461_ Year Month and Day_ V. Description of Invention (2) 5-1 Field of Invention: Special. , ≫ er method to set the body to crystallize the body of electricity to record the body to take the body of the secret machine to record the follow-up state to save the motive in the follow-up state is in the clear in the release of the original situation is different Sending 2-5 fast-required pieces of zero-element daughter conductance has increased the amount of increase, and the fast-rate brain brain electrical element due to the demand of popular demand is semi-specific. Lai Jin / Zeng's instantiation of the C-oxygen circuit belongs to the electro-metallic body, and the productiveness should be overweight. The body has a deep crystal, which is electrically effective. Field body memory. Introduction. It takes half as long to find the derivative of a derivative. The components of the production system are mainly composed of heavy-duty hybrids. The daily Ba-electricity efficiency of the electric field is already high, and the quality of the product is higher than that of semi-peroxane. The small and important weight is that the H0 element power of the ruler body is effective to the effect of the field on the body's guide semi-crystalline material sn. / ΛΊ Figure A shows the top view of the traditional metal oxide semiconductor process. Figure 1B shows the process flow of a conventional transistor. Firstly, the well pattern is defined by photoresist, and then the first P-type ions are implanted on the silicon substrate 100 to form the well implant region. In addition, a second P-type ion is implanted on the silicon substrate 1000 to form a field implanted region. Next, a third P-type ion is implanted on the silicon substrate 100 to form a penetrating implantation region. Finally, a fourth P-type ion is implanted on the broken substrate 100 to form the initial implantation region. The initial implantation zone is formed to implant a solid concentration of approximately 0 to 1 ο 18 liters per square centimeter. Finally, remove the photoresist. When the size of the dynamic random access memory is increased to 0.1 8 microns or more

Page 5 2001.04. 02.005 _ ^ ^ ^ 89102461_ year month day __ V. Description of the invention (3) Low level, the atomic concentration of the substrate of the transistor must be increased to 10 "solid atoms, in order to control the transistor Short channel effect (sh 〇rtcha η ne 1 effect). But this high concentration will introduce more junction leakage current to the P / N junction, thereby reducing the charging time capability. 5-3 Purpose and summary of the invention: According to The invention provides a method for manufacturing a dynamic random access memory transistor. In addition to controlling the short channel effect itself, it can also reduce the interface leakage current of the P / N interface in the bit line contact area and the storage node area. The invention provides a method for forming a transistor in a dynamic random access memory system. The method includes at least the following steps: a semiconductor substrate has at least one isolation element, and the semiconductor substrate has at least one isolation element. The active region is defined above; a first photoresist layer is formed on the semiconductor substrate, and the active region is exposed in a first direction; a first conductive ion is implanted in the semiconductor substrate to form A well implant; implanting a second conductive ion into the semiconductor substrate to form a field implant; implanting a third conductive ion into the semiconductor substrate to form a punchthrough implant); remove the first photoresist layer; then form a second photoresist layer to expose the active area in the second direction, and the second direction is different from the first direction; implant a fourth conductive ion to form an initial implantation area (Threshold implant); and removing the second photoresist layer.

Page 6 2001. 04.02.006 4 455 ο ρ _ mi 89102461_ year month day _fj._ V. Description of the invention (4) 5-4 The diagram is a brief description: The first A shows the traditional metal oxide semiconductor structure Top view of the process; Figure B shows the process flow chart of the traditional metal oxide semiconductor structure; Figure A shows the embodiment of the present invention, which shows the process of a metal oxide semiconductor structure Top view; Second: Figure B shows a process flow diagram of a metal oxide semiconductor structure shown in one embodiment of the present invention. Representative symbols of main parts: 10 substrate 12 active area 14 well implantation> field implantation area, penetration implantation area 20 initial implantation area 30 gate area 38 well area pattern definition 40 well implantation 42 field implantation Into 44 -ω- Beto Implant 45 Photoresist Removal 46 Define Initial Implant Area 48 Initial Implant 50 Photoresist Removal

Page 7 2001.04. 02.007 '4 455 9 ^ _ Case No. 89102461_ Year Month Day __ V. Description of the invention ¢ 5) I 0 0 sand substrate II 0 well implantation area, field implantation area, penetration implantation Area, initial implantation area 5-5 Detailed description of the invention: According to the description of one embodiment of the present invention, the second diagram A shows the top view of the process of the metal oxide semiconductor structure, and the second diagram B shows the Process flow chart of metal oxide semiconductor structure. First, a silicon substrate 10 having P-type conductivity is provided. A pad oxide layer having a thickness of about 100 to 300 angstroms is formed over the substrate 10 using a conventional oxidation technique. Next, a silicon nitride layer is grown on the pad oxide layer to a thickness of about 15O to 2500 Angstroms. On the silicon nitride layer, a layer of photoresist is used as a mask, and the conventional lithography technology is used to etch the silicon substrate 10 anisotropically to form a plurality of shallow trenches in the stone substrate 10. Here, an active area 12 is defined in the two shallow trenches 10 above the silicon substrate 10. Then remove the photoresist. In addition, a first oxide layer is deposited on the substrate 10, and generally, a grinding process such as chemical mechanical polishing (CMP) is performed. The silicon oxide layer is polished until the silicon nitride layer does not stop. Finally, the silicon nitride layer and the pad oxide layer are removed. Next, define the photoresist pattern in the well area (step 38), implant the first P-type ion in the silicon substrate 10 (step 40), and form a hafnium implantation area (we 1 1 im ρ 1 ant). 1 4. This well implantation method uses a collar as an ion source. The implantation energy is between 250 KeV and 400 KeV, and the implantation dose is about 101 to 1018 (solid atoms per square centimeter. Then , Implanting a second P-type ion (step 4 2),

Page 8 2001.04. 02.008 ^ ^ 5 ^ 89102461___ year, month, day, amendment_ 5. Description of the invention (6) A field implant 14 is formed. This field implant uses boron as an ion source, the implantation energy is between 100 KeV and 200 KeV, and the implant dose is about 101 atoms per square centimeter. Next, a third P-type ion is implanted (step 44) to form a punchthrough implant 14. This penetrating implant uses boron as an ion source, with an implantation energy between 50 KeV and 80 KeV, and an implantation dose of about 10 to 10 "atoms per square centimeter. Then remove the defining well area Photoresist (step 4 5). When the size of the dynamic random access memory is increased to 0.1 8 microns or lower, the atomic concentration of the transistor substrate must be increased to 101 atoms in order to control The short channel effect of the transistor. However, such a high transistor substrate atomic concentration will introduce more junction leakage current to the P / N junction, thereby reducing the charging time capability. Use gate implantation to replace the traditional Full-area implantation to reduce the leakage current (1 eakagecurrent) of the bit line contact window and storage node. In the embodiment 'formed on the silicon substrate 10-layer pattern conversion photoresist (step 46) to define the start The implanted area. Then, the pattern conversion photoresist layer is used as a photomask, and a fourth P-type ion is implanted (step 48) to form a threshold implant area 20. This initial implantation uses boron. As an ion source, the implantation energy is between 10KeV and 20KeV ' The injection dose is about 101 to 10 per square centimeter! «[Solid atom. Then remove the pattern conversion photoresist layer (step 50) 'gate structure 3 above the initial implantation area 20 Formation. Finally, a conventional semiconductor element is formed on the active area 12 of the substrate 10. The present invention provides a method for forming a transistor in a dynamic random access memory system. It includes at least the following steps: a semiconductor substrate Material has at least one isolation element, which defines an active area on the semiconductor substrate; forming a first light

Page 9 2001.04. 02. 009 4455 Case No. 89102461 Amended in May 5. Description of the invention (7) The resist layer is on the semiconductor substrate and the active area is exposed in the first direction; the first conductive ion is implanted in the semiconductor substrate To form a well implant; implant a second conductive ion into the semiconductor substrate to form a field implant; implant a third conductive ion into the semiconductor substrate to form a consistent implantation area (Punchthrough implant); removing the first photoresist layer; forming a second photoresist layer to expose the active area in the second direction, and the second direction is perpendicular to the first direction; implanting a fourth conductive ion to form an initial implant Area (threshold implant); and the removal of the second photoresist layer 0 The above is only a preferred embodiment of the present invention, and is not intended to limit the scope of patent application of the present invention; all others do not depart from the spirit disclosed by the present invention All school changes or modifications completed below shall be included in the scope of patent application described below.

Page 10 2001.04. 02.010

Claims (1)

4 4 5 5 _Case No. 89102461_ 年月 日 __ VI. Scope of Patent Application 1. A method for manufacturing dynamic random access memory, including at least the following steps: Provide a semiconductor substrate, the semiconductor substrate has at least one An isolation element is defined therein, the isolation element defines an adjacent active area on the semiconductor substrate; a first photoresist layer is formed on the semiconductor substrate, and the first photoresist layer exposes the active in a first direction Region; implanting a majority of first conductive ions in the semiconductor substrate to form a well region, implanting a majority of second conductive ions in the semiconductor substrate to form a field implantation region, implanting a majority of third conductive ions in the semiconductor substrate Forming a through penetration region in the semiconductor substrate; removing the first photoresist layer; forming a second photoresist layer on the semiconductor substrate, the second photoresist layer exposing the active area in a second direction The second direction is different from the first direction; implanting a majority of the fourth conductive ions to form an initial implantation region; and removing the second photoresist layer. 2. The method according to item 1 of the scope of patent application, wherein the above-mentioned first direction is perpendicular to the second direction. 3. The method as described in item 1 of the scope of patent application, wherein the above-mentioned second party Page 11 2001.04.02.012 4 45 5 d _ i 89102461_ year month day __ VI. Scope of patent application Forming at least a majority of bit line elements in this second direction. 4. The method according to item 1 of the scope of patent application, wherein the first direction includes at least a multi-digit element line element formed in the first direction. 5. The method according to item 1 of the scope of patent application, wherein the above-mentioned isolation element includes at least one shallow trench isolation element. 6. The method according to item 1 of the scope of patent application, wherein the above active area includes at least a storage node on it. 7. The method according to item 1 of the scope of patent application, wherein all of the above-mentioned conductive ions include at least ions of the same type. 8. A method for manufacturing a dynamic random access memory, comprising at least the following steps: providing a semiconductor substrate having a conductivity * the semiconductor substrate has at least one isolation element therein, and the isolation element is on the semiconductor substrate An adjacent active area is defined on the material; a first photoresist layer is formed on the semiconductor substrate, and the first photoresist layer exposes the active area in a first direction; and most of the first conductive areas having the conductivity are implanted. Conducting ions in the semiconductor substrate to form a well region; implanting a majority of second conductive ions having the conductivity into the semiconductor substrate Page 12: 2001.04.02.013 445592 _Case No. 891Q2461_Year Month Date_ί £. 6. The scope of the patent application should be guided by the substrate, and the nature of the third part should be introduced; the introduction of the electric field into the planting field has a Count in multiple shapes into the area of planting wood; Into the layer, block the light and pass through the shape. Divide by moving the layer of wood. Block the light. The first should be straight and vertical. In the semi-domain, the area in the moving layer is the main resistance to the second exposure of the first party to form a second form-Yu Xiangfang Kai Kai 1 to form a sub-ri to lead the fourth sex. The guide layer should have the second highest number of optical instruments and the number of entries. In addition to the planting area, the number of lines in the 8th line of the yuan should be included in the package. The method of the second aspect of the second aspect is the first aspect of the first aspect. The method as described in item 8 of the scope of patent application, wherein the first aspect includes at least a multi-digit element line element formed in the first direction. 1 i. The method according to item 8 of the scope of patent application, wherein the above-mentioned conductivity is P-type. Page 13 2001.04. 02.014