JP2962359B1 - Semiconductor integrated circuit - Google Patents

Abstract

A semiconductor integrated circuit capable of supplying an optimum voltage to an internal circuit following a change in an operating environment such as a temperature. A minimum operating voltage detection circuit includes a charge / discharge circuit including a capacitor connected to a power supply terminal.
1a is provided. Further, a charge / discharge control circuit 21b for controlling the charge / discharge circuit 21a is provided. In the reference circuit 11b, there are provided a first sample logic circuit 22a driven by a voltage supplied from the power supply terminal 2 and a second sample logic circuit 22b driven by a voltage stepped down by the charge / discharge circuit 21a. . Further, the first sample logic circuit 2 is provided in the minimum operating voltage detection circuit 11a.
An output comparison circuit 21c connected to 2a and the second sample logic circuit 22b is provided. Output comparison circuit 21c
Compares the output signals of the first sample logic circuit 22a and the second sample logic circuit 22b, and outputs the comparison result to the charge / discharge control circuit 21b.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit suitable for a semiconductor device driven by a power supply having a limited capacity such as a battery, and more particularly, to a semiconductor integrated circuit with low power consumption.

[0002]

2. Description of the Related Art Conventionally, in a large-scale integrated circuit (LSI) having an internal circuit such as a central processing unit (CPU), a digital signal processor (DSP), or a memory, an internal circuit is supplied with a voltage equivalent to a voltage supplied from the outside. The circuit was being driven. FIG. 5 is a block diagram showing a conventional semiconductor integrated circuit device. This conventional semiconductor integrated circuit device is referred to as a first conventional example.

In the first conventional example, an internal circuit 33 is connected to a power supply terminal 32, and a power supply voltage of 3 V supplied to the power supply terminal 32 is supplied to the internal circuit 33. In addition, as the internal circuit 33, for example, a CPU, a DSP, a memory, or the like is used.

In the first conventional example, a 3V-system input / output terminal 34a and a 5V-system input / output terminal 34b are provided, and a 3VI / O interface 35a is connected to the 3V-system input / output terminal 34a. The 5 VI / O interface 35b is connected to the system input / output terminal 34b.
The power supply terminal 32 is connected to a DC-DC converter 37 for converting a DC voltage of 3V to a DC voltage of 5V, and a 5VI / O interface 35b is connected to the DC-DC converter 37. On the other hand, 3VI /
The O interface 35a is directly connected to the power supply terminal 32.

In the first conventional example configured as described above, the internal circuit is driven by a voltage that cannot be changed and is equal to a voltage supplied from the outside. Therefore, wasteful power consumption due to the operating voltage margin is large.

Therefore, there has been proposed a semiconductor integrated circuit device in which a programmable step-down power supply circuit (semiconductor integrated circuit) is provided between a power supply terminal and an internal circuit. FIG. 6 is a block diagram showing a conventional semiconductor integrated circuit device. This conventional semiconductor integrated circuit device is referred to as a second conventional example. In the second conventional example shown in FIG. 6, the same components as those in the first conventional example shown in FIG. 5 are denoted by the same reference numerals, and detailed description thereof will be omitted.

In the second conventional example, a step-down power supply circuit 31 composed of a semiconductor integrated circuit which incorporates a fuse element and lowers a power supply voltage by cutting the fuse element is provided between a power supply terminal 32 and an internal circuit 33. ing. In addition, 3VI /
Between the O interface 35a and the internal circuit 33,
The first level shifter 36a is connected, and the second level shifter 36b is connected between the 5VI / O interface 35b and the internal circuit 33.

[0008] In the second conventional example configured as described above, the voltage supplied to the internal circuit can be set stepwise. Thereby, useless use of electric power is suppressed.

[0009]

However, since the voltage set in the second conventional example is stepwise, it is difficult to set it to an optimum value. Further, since the setting can be performed only once, there is a problem that it is not possible to follow an operating environment change such as a temperature change after the setting.

Japanese Unexamined Patent Publication No. Hei 8-234851 discloses a semiconductor integrated circuit for detecting a minimum operating voltage from a voltage value divided by a constant voltage value width by a plurality of resistance elements connected in series with each other. However, also in this semiconductor integrated circuit, the voltage to be set is stepwise, and it is difficult to set the voltage to an optimum voltage.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and an object of the present invention is to provide a semiconductor integrated circuit capable of supplying an optimum voltage to an internal circuit following changes in an operating environment such as temperature. Aim.

[0012]

A semiconductor integrated circuit according to the present invention is connected between a power supply terminal and an internal circuit and steps down a power supply voltage supplied to the power supply terminal from the outside and supplies the reduced voltage to the internal circuit. In a semiconductor integrated circuit, a first sample circuit driven by the power supply voltage, a second sample circuit having the same configuration as the first sample circuit, and a capacitor are provided. A drop voltage that drops with the lapse of time is output to the second sample circuit, and an output signal of the first sample circuit is compared with an output signal of the second sample circuit. A minimum operation voltage detection circuit for detecting a minimum operation voltage, and a step of reducing the power supply voltage to a predetermined voltage value in association with the minimum operation voltage and supplying the reduced voltage to the internal circuit And having a pressure circuit, a.

In the present invention, the minimum operating voltage is detected based on the comparison result between the output signal of the first sample circuit and the output signal of the second sample circuit from the continuously falling voltage. Therefore, an accurate minimum operating voltage can be obtained. Further, by repeatedly charging and discharging the capacitor and obtaining the comparison result as needed, an optimum minimum operating voltage can be obtained at each time. Therefore, even if the operating environment changes, no unnecessary power consumption occurs.

The minimum operating voltage detection circuit includes a charge / discharge circuit including the capacitor for charging and discharging the capacitor, a charge / discharge control circuit for controlling the charge / discharge circuit, and a charge / discharge control circuit for the first sample circuit. The output signal and the second
And an output comparison circuit for comparing the output signal of the sample circuit with the output signal of the sample circuit and transmitting the comparison result to the charge / discharge circuit.

Further, the charge / discharge control circuit transmits a signal for causing the capacitor to start discharging to the charge / discharge circuit when a predetermined time has elapsed from the start of charging of the capacitor, and A signal that causes the capacitor to stop discharging when the output signal of the circuit and the output signal of the second sample circuit do not match can be transmitted to the charge / discharge circuit.

Further, it is preferable that the voltage supplied from the step-down circuit to the internal circuit is a voltage obtained by adding a predetermined voltage to the minimum operating voltage.

Furthermore, it is preferable that the same clock frequency is supplied to the first sample circuit and the second sample circuit.

The minimum operating voltage detecting circuit may include a clock circuit for measuring an elapsed time from the start of charging of the capacitor.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a semiconductor integrated circuit according to an embodiment of the present invention will be specifically described with reference to the accompanying drawings. FIG. 1 is a block diagram showing a drive voltage control circuit as a semiconductor integrated circuit according to an embodiment of the present invention.

A drive voltage control circuit 1 as a semiconductor integrated circuit according to the present embodiment is connected to a power supply terminal 2. An internal circuit 3 is connected to the drive voltage control circuit 1. The 3 V power supply voltage supplied to the power supply terminal 2 is appropriately stepped down by the drive voltage supply circuit 1 at regular intervals and supplied to the internal circuit 3. Is done. As the internal circuit 3, for example, a central processing unit (CPU), a digital signal processor (DSP), a memory, or the like is used.

In the driving voltage supply circuit 1, a minimum operating voltage detection circuit 1a and a reference circuit 1b connected to a power supply terminal 2 are provided.
Further, a voltage regulator 1c connected to the minimum operating voltage detection circuit 1a is provided.

A capacitor is built in the minimum operating voltage detecting circuit 1a. The capacitor is charged by the power supply voltage supplied from the power supply terminal 2 and then discharged with a constant time constant. As a result, a continuously falling voltage value is obtained.

The reference circuit 1b includes a CPU or D
At least two critical paths, such as SPs, that require the highest processing speed are incorporated as samples. One sample operates with the power supply voltage supplied from the power supply terminal 2, and the other sample operates with the minimum operating voltage detection circuit 1a.
It operates with the voltage supplied from the. The same clock signal is supplied to both samples. Then, output signals from each sample are output to the minimum operating voltage detection circuit 1a. The minimum operating voltage detection circuit 1a takes an exclusive OR of these output signals and determines whether or not the sample operating by the voltage supplied from the minimum operation voltage detection circuit 1a malfunctions. To detect.

When it is detected that one sample in the reference circuit 1b is malfunctioning, the minimum operating voltage detection circuit 1a stops discharging the capacitor and holds the voltage at that time. Thereby, a minimum operating voltage value is obtained.

In the voltage regulator 1c, the power supply voltage supplied from the power supply terminal 2 is the minimum operating voltage detection circuit 1.
The voltage is reduced to a voltage obtained by adding a fixed value margin to the minimum operating voltage detected by a. Then, the reduced voltage is supplied to the internal circuit 3.

A 3V input / output terminal 4a and a 5V input / output terminal 4b are provided.
Is connected to a 3VI / O interface 5a,
A 5 VI / O interface 5b is connected to the V-system input / output terminal 4b. The power supply terminal 2 is connected to a DC-DC converter 7 for converting a DC voltage of 3V into a DC voltage of 5V.
Is connected to a 5VI / O interface 5b.
On the other hand, the 3VI / O interface 5a is directly connected to the power terminal 2. Further, a first level shifter 6a is provided between the 3VI / O interface 5a and the internal circuit 3.
And a second level shifter 6b is connected between the 5VI / O interface 5b and the internal circuit 3. Details of these configurations and operations will be described in the following specific examples.

Next, the embodiment configured as described above will be described more specifically. FIG. 2 is a block diagram showing a drive voltage control circuit according to a first specific example of the present invention.

In the first specific example, a minimum operating voltage detecting circuit 11a and a reference circuit 11b connected to the power supply terminal 2 and a voltage regulator 11c connected to the minimum operating voltage detecting circuit 11a are provided. Further, a transmitting circuit 18 connected to the power supply terminal 2 is provided.

A charge / discharge circuit 21 having a capacitor connected to the power supply terminal 2 is provided in the minimum operating voltage detection circuit 11a.
a is provided. The power supply voltage supplied from the power supply terminal 2 is reduced by discharging the capacitor. And
The voltage stepped down by the charge / discharge circuit 21a is applied to the reference circuit 11
b and the voltage regulator 11c as a reference voltage. Further, a charge start signal for starting charging of the capacitor based on a signal from the reference circuit 11b, a discharge start signal for starting discharging of the capacitor, and a discharge stop signal for stopping discharging of the capacitor are transmitted to the charging / discharging circuit 21a. Charge / discharge control circuit 21 for controlling circuit 21a
b is provided.

In the reference circuit 11b, a transmitting circuit 1 is provided.
8, a first sample logic circuit 22a and a second sample logic circuit 22b to which an operation signal having the same frequency as the system clock used in the system is supplied. Note that the first sample logic circuit 22a and the second sample logic circuit 22b are equivalent configuration logic circuits, and the sample logic circuits 22a and 22b are duplicates of the circuits whose signal timing is strictest among the internal circuits in the system. ing. The first sample logic circuit 22a is driven by a voltage supplied from the power supply terminal 2, and the second sample logic circuit 22b is driven by a voltage stepped down by the charge / discharge circuit 21a.

Further, an output comparison circuit 21c connected to the first sample logic circuit 22a and the second sample logic circuit 22b is provided in the minimum operating voltage detection circuit 11a. The output comparison circuit 21c is the first sample logic circuit 2
2a and the output signal of the second sample logic circuit 22b are compared, and the comparison result is output to the charge / discharge control circuit 21b.

In the first specific example, there is provided a timer circuit 19 for generating a signal having a constant period at a preset time interval and transmitting the signal to the charge / discharge control circuit 21b.

In the voltage regulator 11c, there is provided a voltage step-down circuit 23 for stepping down the power supply voltage supplied from the power supply terminal 2 to a voltage obtained by adding a margin to the reference voltage supplied from the charge / discharge circuit 21a. .

In the first specific example, a CPU circuit 13 having a built-in CPU is provided as an internal circuit. The voltage stepped down by the voltage step-down circuit 23 is supplied to the CPU circuit 13.

The 3V input / output terminal 4a has a 3VI
A 3V input / output circuit 15a is connected as an / O interface, and a 5V input / output circuit 15b is connected to a 5V input / output terminal 4b as a 5VI / O interface. A first voltage conversion circuit 16a is connected as a first level shifter between the 3V system input / output circuit 15a and the CPU circuit 13, and the 5V system input / output circuit 15b and the CP
A second voltage conversion circuit 16b is connected between the U circuit 13 and a second level shifter. Further, the transmission circuit 1
A booster circuit 17 is connected between the 8/5 V input / output circuit 15b as a DC-DC converter.

Next, the operation of the first example configured as described above will be described. FIG. 3 is a timing chart showing the operation of the first specific example. Note that the curved arrows in FIG. 3 indicate the relationship between one signal and another signal that changes due to its rise or the like.

In the first specific example, when the power supply of the system incorporating this specific example is turned on, the timer circuit 1
9 measures a preset fixed time.

When the predetermined time has elapsed since the system power was turned on, the timer circuit 19 sets the charge / discharge control circuit 2
A signal indicating the fact is transmitted to 1b. Then, the charge / discharge control circuit 21b receiving the signal transmits a charge start signal to the charge / discharge circuit 21a. The charge / discharge circuit 21a that has received the charge start signal starts charging the capacitor. As a result, the voltage output from the charge / discharge circuit 21a increases.

Thereafter, the timer circuit 19 measures a time sufficient for charging the capacitor, and when the time has elapsed, transmits a signal indicating that to the charge / discharge control circuit 21b. Then, the charge / discharge control circuit 21b having received the signal transmits a discharge start signal to the charge / discharge circuit 21a. The charge / discharge circuit 21a that has received the discharge start signal starts discharging the capacitor. When the discharge of the capacitor is started, the charge / discharge circuit 2
The voltage output from 1a drops. Then, the charge / discharge circuit 21a supplies this falling voltage as a reference voltage to the second sample logic circuit 22b.

The output comparison circuit 21c compares the output signals of the first sample logic circuit 22a driven by the power supply voltage and the second sample logic circuit 22b driven by the reference voltage supplied from the charging / discharging circuit 21a as needed. The comparison result signal is transmitted to the charge / discharge control circuit 21b. As the time elapses, the gate delay time increases with a drop in the drive voltage of the second sample logic circuit 22b, and the setup / hold time in the logic circuit cannot be satisfied. At this time, the output results of the first sample logic circuit 22a and the second sample logic circuit 22b do not match. Then, the charge / discharge control circuit 21b
Receives the signal indicating that the output results from the output comparison circuit 21c do not match, and outputs a discharge stop signal to the charge / discharge circuit 21c.
Send to a. The reference voltage at this time is regarded as the minimum operating voltage V ₀ of the CPU circuit 13. That is, it is considered that the CPU circuit 13 does not operate at a voltage lower than this. When detecting the minimum operation voltage V ₀ , the charge / discharge circuit 21 a supplies the minimum operation voltage V ₀ to the voltage step-down circuit 23.

The minimum operating voltage V ₀ voltage down converter 23 which is supplied with the stepping down the power supply voltage supplied from the power supply terminal 2 to the voltages V ₁ obtained by adding a margin ΔV minimum operating voltage V _0. Note that the margin ΔV is set in advance. The voltage step-down circuit 23 outputs the stepped-down voltage to the CPU circuit 1.
Supply 3

After that, the timer circuit 19
Transmits a signal for causing the charge / discharge control circuit 21b to transmit a charge start signal. In the first specific example, the above steps are repeated.

The booster circuit 17 boosts the power supply voltage of 3 V supplied from the power supply terminal to 5 V, and supplies this to the 5 V input / output circuit 15 b. The 5V input / output circuit 15b is
Interfaces a 5V signal input from the outside or output to the outside. Similarly, 3V input / output circuit 1
Reference numeral 5a interfaces a 3V-system signal input from the outside or output to the outside.

The first voltage conversion circuit 16a converts a signal used in the 3V system input / output circuit 15a into a voltage usable by the CPU circuit 13, that is, a voltage stepped down from the power supply voltage by the voltage step-down circuit 23. . Similarly, the second voltage conversion circuit 16b converts a signal used in the 5V input / output circuit 15b into a voltage usable by the CPU circuit 13.

As described above, in the first specific example, the optimum operating voltage is supplied to the CPU circuit 13 from the voltage step-down circuit 23 because the minimum operating voltage is detected at any time even during the operation of the system. You. Therefore, even when the operating environment such as the temperature changes, the minimum operating voltage V ₀ can be detected at the time following the change. As a result, a low voltage obtained by adding a margin ΔV to the minimum operation voltage V ₀ is supplied to the CPU circuit 13 as an internal circuit, which is suitable for reducing power consumption.

Next, a second specific example will be described. In the first specific example, the charge start time and the discharge start time of the charge / discharge circuit 21a are controlled by the charge / discharge control circuit 21b based on the measurement result by the timer circuit 19, assuming that the power supply voltage does not decrease. For this reason, even if the power supply voltage decreases, an erroneous output of the first sample logic circuit 22a is not detected, and an accurate operation may not be obtained. Therefore, the second specific example is provided with a means for monitoring a drop in the power supply voltage. FIG. 4 is a block diagram showing a drive voltage control circuit according to a second specific example of the present invention. FIG.
In the second specific example shown in FIG. 2, the same components as those in the first specific example shown in FIG. 2 are denoted by the same reference numerals, and detailed description thereof will be omitted.

The second specific example includes a first timer for transmitting a signal for causing the charge / discharge control circuit 21b to transmit a signal such as a charge start signal when a predetermined time has elapsed, as in the first specific example. A circuit 20a is provided. Further, a second timer circuit 20b for measuring a charging time to a specified voltage value in the charging / discharging circuit 21a is provided in the minimum operating voltage detecting circuit 11d.

In the second embodiment configured as described above, when the charging time to the specified voltage value measured by the second timer circuit 20b becomes longer than a predetermined time, the power supply voltage such as the battery voltage is reduced. A decrease is detected.
This prevents a malfunction due to a false output of the first sample logic circuit 22a.

[0049]

As described in detail above, according to the present invention,
Since the minimum operating voltage of the internal circuit can be accurately detected at any time, an optimum voltage can be supplied to the internal circuit at any time. Therefore, even if the operating environment changes, no unnecessary power consumption occurs, and the power consumption can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a drive voltage control circuit as a semiconductor integrated circuit according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a drive voltage control circuit according to a first specific example of the present invention.

FIG. 3 is a timing chart showing the operation of the first specific example.

FIG. 4 is a block diagram showing a drive voltage control circuit according to a second specific example of the present invention.

FIG. 5 is a block diagram showing a conventional semiconductor integrated circuit device (first conventional example).

FIG. 6 is a block diagram showing a conventional semiconductor integrated circuit device (second conventional example).

[Explanation of symbols]

 1; drive voltage control circuit 1a, 11a, 11d; minimum operating voltage detection circuit 1b, 11b; reference circuit 1c, 11c; voltage regulator 2, 32; power supply terminal 3, 33; internal circuit 4a, 4b, 34a, 34b; Output terminals 5a, 5b, 35a, 35b; I / O interfaces 6a, 6b, 36a, 36b; level shifters 7, 37; DC-DC converters 13; CPU circuits 15a, 15b; input / output circuits 16a, 16b; Booster circuit 18; transmission circuit 19, 20a, 20b; timer circuit 21a; charge / discharge circuit 21b; charge / discharge control circuit 21c; output comparison circuit 22a, 22b; sample logic circuit 23; voltage step-down circuit 31;

Claims (6)

(57) [Claims] 1. A semiconductor integrated circuit connected between a power supply terminal and an internal circuit, which lowers a power supply voltage externally supplied to the power supply terminal and supplies the reduced voltage to the internal circuit, wherein the semiconductor integrated circuit is driven by the power supply voltage. A first sample circuit, a second sample circuit having the same configuration as the first sample circuit, and a second sample circuit which includes a capacitor, and discharges the capacitor to reduce a voltage drop with time. A minimum operating voltage detection circuit that compares the output signal of the first sample circuit with the output signal of the second sample circuit and detects a minimum operating voltage of the internal circuit based on the comparison result; A step-down circuit for reducing the power supply voltage to a predetermined voltage value in association with the minimum operating voltage and supplying the reduced voltage to the internal circuit. circuit. 2. The charge / discharge circuit comprising the capacitor for charging and discharging the capacitor; a charge / discharge control circuit for controlling the charge / discharge circuit; 2. The semiconductor integrated circuit according to claim 1, further comprising: an output comparison circuit that compares an output signal with an output signal of the second sample circuit and transmits a result of the comparison to the charge / discharge circuit. 3. The charge / discharge control circuit sends a signal to the charge / discharge circuit to cause the capacitor to start discharging when a predetermined time has elapsed from the start of charging the capacitor, and 3. The semiconductor according to claim 2, wherein a signal that causes the capacitor to stop discharging is transmitted to the charge / discharge circuit when an output signal of the circuit and an output signal of the second sample circuit do not match. 4. Integrated circuit. 4. The voltage supply circuit according to claim 1, wherein the voltage supplied from the step-down circuit to the internal circuit is obtained by adding a predetermined voltage to the minimum operation voltage. The semiconductor integrated circuit according to the above. 5. The semiconductor integrated circuit according to claim 1, wherein the same clock frequency is supplied to the first sample circuit and the second sample circuit. . 6. The circuit according to claim 1, wherein the minimum operating voltage detection circuit includes a clock circuit that measures an elapsed time from when the charging of the capacitor is started. Semiconductor integrated circuit.