JP2962183B2 - Phase locked loop circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase locked loop circuit (PLL circuit), and more particularly to a PLL circuit capable of maintaining a narrow band and having a wide supplementary range.

[0002]

2. Description of the Related Art It is well known that this kind of PLL circuit is roughly divided into a phase comparator, a voltage controlled oscillator (VCO), and a loop filter.

FIG. 3 shows a conventional configuration example of such a PLL circuit. In the figure, a phase comparator 102 which takes in a reference clock pulse from a reference clock pulse input terminal 101 and compares the phase with a comparison signal, and a phase comparator 1
02, a low-pass filter 103 for filtering the phase error signal from the second amplifier 02, an amplification circuit 105 for forming a control signal from an output signal from the low-pass filter 103 and a reference voltage from the reference voltage generation circuit 104, A voltage controlled oscillator (VCO) 106 that generates an output signal corresponding to the control signal and supplies the output signal to an external terminal 107 , and a frequency dividing circuit 108 that divides the output signal from the VCO 106 by 1 / N to generate a comparison signal. Is what you do.

In the PLL circuit configured as described above, V
The CO 106 oscillates with N times the frequency f _s of the reference clock pulse input to the input terminal 101 as the center frequency. The oscillation frequency f _o is is divided by frequency divider 108, the reference clock frequency f _s and approximately the same frequency f _o
Has been.

In such a state, the input terminal 101
The reference clock pulse (frequency f_s) Rank
The signal is input to the phase comparator 102. In the phase comparator 102,
A frequency obtained by dividing the output from the VCO 6 by N by the frequency dividing circuit 108
Number f_oPhase is compared with the clock pulse of
Outputs an error signal. The phase error signal is a low-pass filter 1
03, the error voltage V_e
Becomes This error voltage V_eWas amplified by the amplifier 105
Later, it is input to the VCO 106. At this time, the error voltage
V_eIs the output frequency f of the VCO 106_oTo the frequency f_o
And frequency f_sControl the VCO 106 in a direction to reduce the difference between
You. Therefore, the frequency f_oAnd frequency f _sIs close enough
If the frequency f_oIs the frequency f_sAnd lock the frequency
And the phase difference disappears. That is, the input frequency f_sN
The double frequency is output from the output terminal 107.

As described above, in the conventional PLL circuit,
In order to obtain good jitter characteristics, it is necessary to narrow the PLL band sufficiently. However, when the band is narrowed in this way, the capture range of the PLL becomes narrow, and it is difficult to simultaneously obtain good jitter characteristics and a wide supplementary range (capture range).

[0007] In order to solve this problem, is obtained by incorporation of the control voltage input to the voltage controlled oscillator, or the characteristics of the low pass filter in the variable, the voltage applied to the low pass filter so that the variable (Japanese Patent Laid-Open No. 4-2961)
No. 17, JP-A-60-186147). Alternatively, a plurality of low-pass filters having different characteristics are prepared, and switched according to the state of the signal (Japanese Patent Laid-Open No. 2-1).
Japanese Patent Application Laid-Open No. 2-12741 discloses a method in which a control voltage of another path is used in accordance with an input signal.
812, Japanese Patent Application Laid-Open No. 1-243622, etc.).

[0008]

SUMMARY OF THE INVENTION However, the conventional P
In the LL circuit, since the characteristics and the like of the low-pass filter are changed by the voltage or the like input to the voltage controlled oscillator or according to the input reference signal, the output signal is deviated from the reference. There is a disadvantage that it cannot be detected accurately.

It is an object of the present invention to provide a PLL circuit having good jitter characteristics and a wide supplementary range.

[0010]

According to the first aspect of the present invention, (a) an error signal is detected by detecting a phase difference between an input reference signal and a comparison signal obtained by dividing an output signal by a predetermined division value. a phase comparator for forming, (b) a low-pass filter for extracting a low frequency component of the error signal from the phase comparator, (c)
An amplifier for amplifying the extracted signal of the low-pass filter,
(D) detecting a beat frequency based on a frequency difference between the input reference signal and the comparison signal, identifying that the beat frequency has exceeded a set value, and generating a sweep control signal having information indicating the state of the beat frequency; the beat frequency detection circuit which outputs, (e) sweep from the beat frequency detecting circuit
The first control signal and the second control signal
A voltage control circuit for forming a control signal and an NPN type
Connect the emitter of the transistor to the input terminal of the voltage-controlled oscillator.
Then, connect the collector to a positive power supply,
Supply a first control signal to its base, and
The second voltage supply means is an emitter of the PNP transistor.
To the input terminal of the voltage-controlled oscillator, and the collector to the negative terminal.
Power supply, and a second connector on its base.
Control signal and voltage control
The positive polarity side in response to the first control signal from the circuit.
A first voltage supplier that outputs a voltage as a frequency control voltage
And a second control signal from the voltage control circuit.
Output the voltage on the negative side as the frequency control voltage
2 and a frequency control means for controlling the control voltage from the amplifier.
And a resistor that outputs the control voltage.
The sweep circuit forcibly sweeps the frequency control voltage when the sweep control signal with the information that the beat frequency is higher than the set value is input from the output circuit, or the sweep control voltage with the information that the beat frequency is lower than the set value phase but a sweep circuit for outputting a control voltage itself from the amplifier as a frequency control voltage when the input and a voltage controlled oscillator for controlling the frequency of the output signal in response to the frequency control voltage from (to) the sweep circuit A synchronous loop circuit is provided.

That is, according to the present invention, when a beat is generated between the reference signal and the comparison signal, the beat is detected by the beat frequency detection circuit to form a sweep control signal. When this sweep control signal is input to the sweep circuit, the sweep circuit sweeps the frequency control voltage to positive and negative polarities,
The oscillation frequency of the voltage controlled oscillator is varied. Thereby, the frequency is locked.

[0012] In the second aspect of the present invention, the input (i)
Comparison signal obtained by dividing the reference signal and output signal
Phase comparator that detects the phase difference from the signal and forms an error signal
And (b) the low frequency component of the error signal from this phase comparator
(C) the low-pass filter that extracts
An amplifier that amplifies the extracted signal and (d) a reference signal
Input and a first flip-flop that uses the comparison signal as the clock input.
Flip-flop circuit and output of first flip-flop circuit
Use the rising edge of the signal as a trigger input and pulse for a predetermined time.
A monostable multivibrator for output and a monostable
The output signal from the table multivibrator is
Output signal from the first flip-flop circuit
A second flip-flop circuit for clock input;
The beat due to the frequency difference between the input reference signal and the comparison signal
Detects the frequency and sets the beat frequency to the set value.
And identify the beat frequency and change the beat frequency
Beat frequency detection that outputs a sweep control signal with
Output circuit and (e) the beat frequency detection circuit
Control with information that the default frequency is higher than the set value
Forcibly sweeps the frequency control voltage when a signal is input
Or that the beat frequency is below the setting
When the sweep control voltage with
Sweep to output control voltage itself as frequency control voltage
Circuit and the frequency control voltage from this sweep circuit.
Voltage controlled oscillator that controls the frequency of the output signal
A phase locked loop circuit is provided.

[0013] In the third aspect of the present invention, the sweep circuit includes a
The first code is based on the sweep control signal from the
A control signal and a second control signal.
Voltage control circuit, and a first control from the voltage control circuit.
The voltage on the positive polarity side is set as the frequency control voltage according to the
And a first voltage supply means for outputting a voltage
The voltage on the negative polarity side is changed in frequency according to the second control signal.
Second voltage supply means for outputting as a number control voltage;
A resistor that outputs the control voltage from the circuit as a frequency control voltage
An armor is provided.

[0014]

[0015]

[0016]

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below with reference to embodiments.

FIG. 1 shows a PLL circuit according to an embodiment of the present invention. In the figure, a phase comparator 12 that takes in a reference clock pulse from a reference clock pulse input terminal 11 and compares the phase with a comparison signal, and a low-pass filter 1 that filters a phase error signal from the phase comparator 12
3, an amplifier circuit 15 to form a control voltage V _c and a reference voltage from the output signal and the reference voltage generating circuit 14 from the low-pass filter 13 takes in the control voltage V _c from the amplifier circuit 15, sweep control signal when the S _c is input to output a control voltage V _cc which forcibly sweep control voltage V _c, or a control voltage V _cc remains of the control voltage V _c inputted when the sweep control signal S _c is not input a sweep circuit 16 for outputting a voltage controlled oscillator (VCO) 18 to be supplied to the external output terminal 17 to generate an output signal corresponding to the frequency control voltage V _cc from the sweep circuit 16, the output signal from the VCO 18 1 / N A frequency dividing circuit 19 which divides the frequency into a comparison signal,
With obtaining the beat frequency of the comparison signal from the reference clock pulse and the frequency divider circuit 19 comprises a beat frequency detector 20 to form a sweep control signal S _c when it detects that the beat frequency is equal to or less than the set Things.

Further, the sweep circuit 16 includes a voltage control circuit 61 to form a first control signal and a second control signal based on the sweep control signal S _c from the beat frequency detection circuit 20, the voltage control circuit 61 The positive-side voltage in response to the first control signal of
a first voltage supply unit 62 for outputting as _cc, and the second voltage supply unit 63 for outputting a negative side of the voltage in response to the second control signal from the voltage control circuit 61 as a frequency control voltage V _cc, the control voltage V _c from the amplifier circuit 15 consists of resistors 64 and outputting a frequency control voltage V _cc.

The first voltage supply unit 62, NPN type transistors a positive voltage source (not shown) the collector of Q _1, the are connected to input terminals of the VCO18 emitter, the voltage control circuit to the base 61 From the first control signal.

The second voltage supply means 63 connects the collector of the PNP transistor Q ₂ to a negative voltage source (not shown), the emitter of which is connected to the input terminal of the VCO 18, and the base thereof from the voltage control circuit 61. The second control signal can be supplied.

FIG. 2 shows an example of the configuration of the beat frequency detection circuit. In the figure, input terminals 21 and 2
2 is connected to the data (D) input terminal and the clock (C) input terminal of the flip-flop circuit 23. The Q output terminal of the flip-flop circuit 23 is connected to the input terminal of the monostable multivibrator 24 and the clock (C) input terminal of the flip-flop circuit 25. The output terminal of the monostable multivibrator 24 is connected to the data (D) input terminal of the flip-flop circuit 25. The Q output terminal of the flip-flop circuit 25 is connected to the output terminal 26.

In the embodiment configured as described above, the communication
Normally, as in the conventional PLL circuit, the reference clock pulse
Will be locked. Therefore, the input reference frequency
Number f _sAnd the output signal of the VCO 18
Divided clock frequency f_oThere is no difference. This and
Frequency f_sAnd frequency f_oBetween the beat frequency
No numbers occur. Therefore, the beat frequency detection circuit 20
Provides information that the beat frequency is below a certain set value.
Sweep control voltage S_cIs controlled by the voltage control circuit of the sweep circuit 16.
Give to road 61. The voltage control circuit 61 has this information.
Sweep control voltage S _cOf the first voltage supply means 62 based on
Transistor Q₁And the transistor of the second voltage supply means 63
Star Q_TwoGenerates a voltage that turns off both,
Transistor Q₁, Q_TwoSupply to the base. Accordingly
And transistor Q₁, Q_TwoDoes not operate, and the amplifier circuit 15
Control voltage V output from_cIs the frequency through resistor 64
Number control voltage V_ccIs output as

Next, when the PLL is unlocked,
Will be explained. When the PLL is unlocked, the input frequency f
_sBetween the reference clock pulse and the output frequency.
Number f _sAnd the frequency f of the comparison signal_oBetween the beat frequency
Occur. When such a frequency difference further increases, the
The port frequency is also higher. Beat frequency detection circuit 2
0 means this beat frequency is higher than a certain set value
Detect that.

[0025] This detecting operation, referring to FIG. 2, first, a reference signal of a frequency f _s (clock pulse) is input to the input terminal 21, the comparison signal of the frequency f _o to the input terminals 22 Is entered. Both frequency f _s, f _o
Are equal, Q of the flip-flop circuit 23 is
The output signal of the output terminal does not change. However, when the two frequencies f _s and f _o do not match, the output signal of the Q output terminal of the flip-flop circuit 23 changes to “1” or “0”, and the rate of the change is determined by the monostable multivibrator 24. When the time exceeds, the flip-flop circuit 25 is set and the Q of the flip-flop circuit 25
From the output terminal, and outputs the sweep control voltage S _c which means that is higher than a certain set value beat frequency. Such a sweep control voltage _Sc is supplied to the voltage control circuit 61 of the sweep circuit 16.

In the voltage control circuit 61, the sweep control voltage S _c
First, the transistor Q of the first voltage supply means 62
Only ₁ is turned on, and the control voltage of the VCO 18 is forcibly and slowly increased. When the control voltage V _cc which is applied to the VCO18 reaches the power supply voltage, turn and turn off the transistors to Q ₁ first voltage supply unit 62, the transistor Q ₂ of the second voltage supply unit 63 as an on VCO1
8 lower the control voltage. When the control voltage V _cc applied to the VCO 18 reaches the power supply voltage of the negative voltage source again, the transistor Q ₂ is turned off again, and the transistor Q ₁ is turned on to increase the control voltage V _{cc of the} VCO 18.

Such an operation is repeated until the input / output beat frequency falls below the set value. When the beat frequency is equal to or less than the set value, the beat frequency detection circuit 20
The sweep control voltage S _c having the information from the sweep circuit 16
To the voltage control circuit 61. In the voltage control circuit 61 ,
Steady state Like, it is an off both of the transistors Q ₁ and transistor Q _2.

According to this embodiment, the beat frequency between the frequency f _s of the reference clock pulse and the clock frequency f _o of the comparison signal obtained by dividing the output of the VCO 18 by N is monitored.
When this beat frequency exceeds a certain set value, VCO
18 forcibly changing the control voltage _Vcc and continuing this operation until the beat frequency falls below the set value.
Even if the band maintenance is narrow, a wide cabure range can be obtained.

[0029]

As described above, claims 1 and 2
According to the invention described in Item 2 , when a beat is generated between the reference signal and the comparison signal, the beat frequency is detected by the beat frequency detection circuit to form a sweep control signal, and the signal is supplied to the voltage controlled oscillator by the signal. an input frequency control voltage is swept to the positive and negative polarity, since the variable and is <br/> not the oscillation frequency of the voltage controlled oscillator, can detect changes in the precise reference signal and the output signal, and the PLL circuit Even if the characteristic is narrow, a wide cabture range can be obtained.

Further, according to the first aspect of the present invention, the signal applied to the voltage controlled oscillator can be alternately swept by the sweep circuit between the positive and negative electrodes. Also, the first voltage supply means
An NPN transistor, and a second voltage supply.
The supply means is constituted by a PNP transistor.
This simplifies the circuit configuration.

According to the second aspect of the present invention,
The frequency detection circuit uses the reference signal as the data input and compares
First flip-flop circuit using signal as clock input
And the rising of the output signal of the first flip-flop circuit
Monostable multivibration with a trigger input
And the output signal from the monostable multivibrator.
Signal from the first flip-flop circuit
Second flip-flop using the output signal of the second clock as a clock input
And the beat frequency can be detected accurately.
Wear.

According to the third aspect of the present invention, the number of sweeps
Signal applied to the voltage controlled oscillator alternates between positive and negative
Can be swept.

[0033]

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a block diagram showing a frequency detection circuit used in the embodiment.

FIG. 3 is a block diagram showing a conventional PLL circuit.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 12 Phase comparator 13 Low-pass filter 14 Reference voltage generation circuit 15 Amplification circuit 16 Sweep circuit 17 External output terminal 18 Voltage controlled oscillator (VCO) 19 Divider circuit 20 Beat frequency detection circuit 23 First flip-flop circuit 24 Monostable multi Vibrator 25 Second flip-flop circuit 61 Voltage control circuit 62 First voltage supply means 63 Second voltage supply means 64 Resistor Q ₁ NPN transistor Q ₂ PNP transistor

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H03L 7/06-7/14

Claims (3)

(57) [Claims] 1. A phase comparator for detecting a phase difference between an input reference signal and a comparison signal obtained by dividing an output signal by a predetermined division value to form an error signal, and an error from the phase comparator. A low-pass filter for extracting a low-frequency component of the signal; an amplifier for amplifying the extracted signal of the low-pass filter; a beat frequency based on a frequency difference between an input reference signal and the comparison signal; A beat frequency detection circuit that outputs a sweep control signal having information indicating the beat frequency state, and a sweep control signal from the beat frequency detection circuit .
The first control signal and the second control signal
The voltage control circuit to be formed and the NPN transistor
To the input terminal of the voltage-controlled oscillator,
Polarity power supply, and the base
Providing a control signal, and providing the second voltage supply
The stage oscillates the voltage-controlled oscillation of the emitter of the PNP transistor
To its input terminal and its collector to the negative power supply.
And connect a second control signal to its base.
Supply from the voltage control circuit.
The frequency of the positive polarity side is changed according to the control signal of 1.
First voltage supply means for outputting as a control voltage;
Negative electrode according to the second control signal from the pressure control circuit
Second voltage for outputting the voltage on the neutral side as a frequency control voltage
Supply means, and a control voltage from the amplifier
And a resistor that outputs the pressure
When the sweep control signal with the information that the beat frequency is higher than the set value is input from the path , the frequency control voltage is forcibly swept, or the sweep control voltage with the information that the beat frequency is lower than the set value is A sweep circuit that outputs the control voltage itself from the amplifier as a frequency control voltage when input, and a voltage controlled oscillator that controls the frequency of the output signal according to the frequency control voltage from the sweep circuit. A phase locked loop circuit characterized by the above. 2. The method according to claim 1, wherein the input reference signal and the output signal are
The phase difference from the comparison signal divided by the division value is detected, and the error signal is detected.
And a low frequency component of an error signal from the phase comparator.
A low-pass filter, an amplifier for amplifying the extracted signal of the low-pass filter, and the reference signal as a data input;
A first flip-flop circuit serving as a clock input;
Trigger on rising edge of output signal of lip-flop circuit
Monostable multiple that outputs a pulse for a predetermined time as force
Multivibrator and monostable multivibrator
Output signal from the first flip-flop as the data input
The second is to use the output signal from the flop circuit as the clock input.
And an input reference signal and the flip-flop circuit.
When the beat frequency due to the frequency difference from the comparison signal is detected
In both cases, this beat frequency has exceeded the set value.
Sweep with identification and information indicating beat frequency status
A beat frequency detection circuit that outputs a control signal , and the beat frequency is set to a set value from the beat frequency detection circuit.
Sweep control signal with information indicating that
Sometimes the frequency control voltage is forcibly swept, or
Control signal with information that the
When the pressure is input, the control voltage from the amplifier is
A sweep circuit for outputting a signal as a frequency control voltage, and the output signal according to the frequency control voltage from the sweep circuit.
A voltage-controlled oscillator for controlling the frequency of the signal
A phase locked loop circuit characterized by the above . 3. A sweep circuit according to claim 1, wherein said sweep circuit is a first sweep control circuit based on a sweep control signal from a beat frequency detection circuit.
Form a control signal and a second control signal
Voltage control circuit, and a first control signal from the voltage control circuit.
And outputs the voltage on the positive polarity side as a frequency control voltage.
In response to a second control signal from the voltage control circuit.
Output the voltage on the negative polarity side as the frequency control voltage
And a control voltage from the amplifier circuit as a frequency control voltage.
3. The method of claim 2, further comprising the step of:
The above-mentioned phase locked loop circuit.