JPH08163113A - Error detection circuit, clock regeneration circuit using the detection circuit, and delay lock circuit - Google Patents

Abstract

PURPOSE: To correctly output the signal that converges the error of the frequency or phase at a high communication speed by integrating the charge pump output to eliminate the unnecessary high frequency components and securing the necessary information. CONSTITUTION: A 4-stage delay circuit 17 is used as a DLL circuit in place of a voltage control oscillator to generate the clocks Φ0 to Φ3 having the phases shifted from each other by a fixed degree to an input clock Φ. Then an integration circuit 15 is connected to the output terminal of a charge pump 12 and an external terminal 23. The delay times of delay circuits DL1 to DL4 of the circuit 17 are controlled by the output of a loop filter 13, and the phase difference between the input clock Φ of the circuit DL1 and the output clock Φ0 of the circuit DL4 is converged to 2π. Then the output charge CH of the pump 12 is integrated by the circuit 15 so that the unnecessary high frequency components included in a PLL loop are eliminated and only the necessary information are outputted. As a result, the parasitic inductance and the capacity of the terminal 23 are reduced and the output waveform distortions are decreased despite a high speed signal DAT.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an error detection circuit for detecting an error in the frequency or phase of a clock with respect to a serial signal, a clock recovery circuit and a delay lock circuit using the error detection circuit.

[0002]

2. Description of the Related Art FIG. 9 shows a conventional clock recovery circuit 10. This circuit is a PLL circuit for reproducing a clock CLK that is potentially included in the serial signal DAT, and includes an error convergence pulse generation circuit 11 and a charge pump 1.
2, the loop filter 13 and the voltage controlled oscillator 14 are connected in a ring.

An error converging pulse generating circuit 11, a charge pump 12, and an operational amplifier circuit 13 of a loop filter 13.
1 and the voltage controlled oscillator 14 are the semiconductor integrated circuit 20.
Is built into. In order to determine the characteristics of the loop filter 13 according to the communication speed of the signal DAT, the resistors 132 and 133 and the capacitor 134 of the loop filter 13 are externally attached to the semiconductor integrated circuit 20. 21 to 24 are
It is an external terminal of the semiconductor integrated circuit 20. A crystal resonator (not shown) is externally attached to the voltage controlled oscillator 14.

The error-convergence pulse generation circuit 11 has an up pulse * UP and an up-pulse * UP for converging the frequency error of the reproduction clock CLK with respect to the serial signal DAT within a predetermined range or the phase error to a constant value (0 or π / 2). Down pulse D
Generate WN. When the frequency of the reproduction clock CLK with respect to the serial signal DAT is low or the phase is delayed, the up pulse * UP is output, and in the opposite case, the down pulse DWN is output.

The charge pump 12 has an up pulse * U
The amount of charge q proportional to the pulse width of P is discharged, and the amount of charge q proportional to the pulse width of the down pulse DWN is sucked. To make this relationship accurate, charge pump 1
It is necessary to fully swing the output of No. 2 between the potential VCC and the potential -VCC of the power supply line.

[0006]

The output of the charge pump 12 has parasitic inductance and parasitic capacitance due to the relationship between the external terminal 23, the bonding wire connected to the external terminal 23, these bonding wires and terminals, and the package. To do. Communication speed of serial signal DAT is 1 Gbp
When it becomes about s or more, these parasitic inductance and parasitic capacitance cannot be ignored and the output of the charge pump 12 cannot be fully swung. For this reason,
The output waveform of the charge pump 12 is distorted, and the charge pump 12 cannot achieve the function of discharging / sucking an amount of charges proportional to the input pulse width.

Such a problem occurs even when the entire loop filter is built in a semiconductor integrated circuit for the purpose of miniaturization. This is because when the communication speed becomes high, the high speed operation is limited by the parasitic capacitance such as the output wiring of the charge pump 12. In view of such problems, an object of the present invention is to provide an error detection circuit capable of more accurately outputting a signal for converging an error in frequency or phase under a high communication speed, and a clock using the error detection circuit. It is to provide a reproducing circuit and a delay lock circuit.

[0008]

In the error detection circuit according to the present invention, in response to the input of the serial signal and the clock, information for converging the frequency error or the phase error of the clock with respect to the serial signal is provided. An error-converging pulse generation circuit that outputs a pulse including a charge pump, a charge pump that moves electric charge through an output end in response to an input of the pulse, and an input end connected to the output end of the charge pump,
An integrating circuit that integrates the amount of electric charge moving through the input end and outputs the integrated amount as an error signal from the output end.

The error-converging pulse generation circuit has a constant output pulse width and discharges or sucks an amount of charge proportional to the number of output pulses via a charge pump, and an output pulse width is indefinite. In some cases, an amount of charges corresponding to the width (usually approximately proportional to the width) is discharged or sucked through the charge pump. According to the present invention, the output of the charge pump is integrated by the integrator circuit, unnecessary high frequency components are removed, and necessary information remains. Therefore, the output of the integrator circuit includes parasitic capacitance or parasitic inductance due to wiring or the like. However, the influence is reduced, and the signal for converging the error of the frequency or the phase can be more accurately output under the high communication speed.

In the first aspect of the present invention, the integrating circuit is
An operational amplifier circuit that amplifies the potential difference between the two input terminals, a reference potential is applied to one of the two input terminals, and the other of the two input terminals is coupled to the output terminal of the charge pump; A capacitor connected between the other and the output end of the operational amplifier circuit. In the second aspect of the present invention, the charge pump has complementary output terminals for outputting a pair of complementary signals, and the integrator circuit amplifies a potential difference between the non-inverting input terminal and the inverting input terminal to perform non-inverting. An operational amplifier circuit that outputs from an output terminal and an inverting output terminal, and the non-inverting input terminal and the inverting input terminal are coupled to the complementary output terminal of the charge pump;
A first connected between the non-inverting input and the inverting output
A capacitor and a second capacitor connected between the inverting input and the non-inverting output.

In a third aspect of the present invention, the error detection circuit is included in a semiconductor integrated circuit, and the output end of the integration circuit is connected to an external terminal. In the clock recovery circuit according to the fourth aspect of the present invention, any one of the error detection circuits described above, a loop filter having an input end connected to the output end of the integration circuit, and an input end connected to the output end of the loop filter. ,
A voltage controlled oscillator circuit for generating the reproduced clock having a frequency according to an input voltage. The loop filter is
It is for adjusting the loop bandwidth of the PLL.

In the delay lock circuit according to the fifth aspect of the present invention,
Any one of the above error detection circuits, a loop filter having an input end connected to the output end of the integration circuit, and a plurality of delay circuits for delaying the signal supplied to the data input end according to the signal at the control input end. The clocks are supplied in series to the data input terminals of the delay circuits at the first stage, and the outputs of the delay circuits at the final stage are supplied as the serial signals to the error-converging pulse generation circuit, and the delays of the plurality of stages are delayed. And a multistage delay circuit to which the output signal of the loop filter is supplied to the control input terminal of the circuit.

According to the circuit of the fourth or fifth aspect of the present invention, the loop filter has an external circuit or the communication speed is high, so that the parasitic capacitance of the output wiring of the charge pump is a problem. Even in such a case, it can be used under a high communication speed for the above reason.

[0014]

Embodiments of the present invention will be described below with reference to the drawings. In the drawings, the same or similar components are denoted by the same or similar reference numerals. [First Embodiment] FIG. 1 shows a clock recovery circuit 10A of the first embodiment. This circuit 10A includes a charge pump 12
9 is different from the clock recovery circuit 10 in FIG. 9 in that the integration circuit 15 is connected between the output end of the circuit and the external terminal 23 of the semiconductor integrated circuit 20A.

The integrating circuit 15 is a known active CR integrating circuit, and has an operational amplifier circuit 151 whose non-inverting input terminal is connected to the ground line, an inverting input terminal of the operational amplifier circuit 151, and an output terminal of the charge pump 12. Resistor 1 connected between
52 and a capacitor 153 connected between the inverting input terminal and the output terminal of the operational amplifier circuit 151, and the output terminal of the operational amplifier circuit 151 is connected to the external terminal 23. The resistor 152 is for current limitation and is, for example, 10 kΩ. The capacitor 153 only needs to be able to store a small amount of electric charge, and is, for example, 1 pF. On the other hand, the capacitance of the capacitor 134 is relatively large, for example, 0.1 μF.

The error converging pulse generation circuit 11 is
The output pulse width is constant and the error convergence is controlled by the number of pulses, and the error width is controlled by the pulse width.
There are types. The error converging pulse generation circuit 11, the charge pump 12, and the integration circuit 15 constitute an error detection circuit.

FIG. 2 shows the output signals * UP and DWN of the error convergence pulse generating circuit 11, the output charge CH of the charge pump 12 and the output potential VO of the integrating circuit 15. In this example, the pulse widths of the signals * UP and DWN are constant. In response to one up pulse * UP, the charge CH is transferred from the power supply line having the potential VCC to the PNP transistor 12
It is accumulated in the capacitor 153 through 1 and the resistor 152, and its charge amount increases by q. As a result, the potential VO
Is reduced. Since the loop filter 13 is an inverting output type, the input potential of the voltage controlled oscillator 14 rises and the output frequency of the voltage controlled oscillator 14 rises as the potential VO drops. Similarly, the charge CH is transferred from the capacitor 153 to the resistors 152 and N in response to one down pulse DWN.
It is discharged to the power supply line of potential -VCC through the PN transistor 122, which is the reverse of the above case.

By such an operation, the frequency error of the reproduction clock CLK with respect to the serial signal DAT converges within a predetermined range or the phase error converges to a constant value (0 or π / 2). In order to make the amount of the charge CH proportional to the pulse width, the output of the charge pump 12 is the potential VCC and the potential −V of the power supply line.
Full swing with CC. The charge CH has a pulse waveform and includes a high frequency component unnecessary in the PLL loop. By integrating the charge CH in the integrating circuit 15,
The component is removed, and necessary information is output from the integrating circuit 15. Therefore, the influence of the parasitic inductance and the parasitic capacitance existing in the external terminal 23 is reduced, and the distortion of the waveform output from the external terminal 23 is significantly reduced even if the communication speed of the serial signal DAT is as high as about 1 Gbps or more. it can.

[Second Embodiment] FIG. 3A shows a phase error detection circuit of the second embodiment which is used in place of the error convergence pulse generation circuit 11, charge pump 12 and integration circuit 15 in FIG. Indicates. Error convergence pulse generation circuit 11A
Is a well-known exclusive OR gate, and reproduction clocks CLK and RZ (Re
turn to Zero) signal DAT is supplied. Reference numeral 11a is an equivalent resistance of the output stage of the error-converging pulse generation circuit 11A. Since this resistance plays the role of the resistor 152 in FIG. 1, the integrating circuit 15A does not include the resistor 152.

FIG. 3B shows waveforms of the RZ signal DAT, the reproduction clock CLK, the output charge amount UD of the exclusive OR gate 11A, and the output potential VO of the integrating circuit 15A. The charge amount UD is a pulse that fluctuates above and below 0, and is a potential VO when integrated by the integration circuit 15A.
Is the phase error π / 2 + ΔE of the serial signal DAT.
When E is negative as shown, the output decreases and the output of the loop filter 13 in FIG. 1 increases, and ΔE converges to zero. When ΔE is positive, the potential VO rises and ΔE converges to zero.

The output stage of the exclusive NOR gate 11A performs full swing between the power supply voltages as in the charge pump 12 of FIG. 1 and discharges an amount of charge proportional to the positive pulse width to obtain a negative pulse width. It functions as a charge pump because it draws a proportional amount of charge. Therefore, it can be said that the exclusive NOR gate 11A is composed of the exclusive OR gate of the portion excluding the output stage and the charge pump that is the output stage.

[Third Embodiment] FIG. 4 shows a phase error detection circuit of a third embodiment which is used in place of the error-convergence pulse generation circuit 11, charge pump 12, and integration circuit 15 in FIG. The error converging pulse generation circuit 11B is a known improved Hodge circuit, and includes the D flip-flop 11
1 to 114 are connected in cascade, and an exclusive OR gate 115, an exclusive NOR gate 116, 117
The two inputs of the exclusive OR gate 118 are connected to the data input D and the non-inverting output Q of the D flip-flops 111 to 114, respectively.

The NRZ signal DAT is supplied to the data input terminal D of the D flip-flop 111 and reproduced clock CL
K is supplied to the clock input terminals CK of the D flip-flops 111 and 113, and the reproduction clock * CLK obtained by inverting the logic of the reproduction clock CLK is the D flip-flop 1
It is supplied to clock inputs CK of 12 and 114. The output of the exclusive OR gate 115 contains phase error information. Since the edge of the serial signal DAT shifts in the time axis direction due to the tail portion of the pulse overlapping the adjacent pulse in the dense portion of the serial signal DAT, phase jitter occurs in the reproduced clock CLK. , The outputs of gates 116, 117 and 118 are used.

An adder circuit 16 is connected between the output end of the error convergence pulse generation circuit 11B and the input end of the integration circuit 15A. The adder circuit 16 includes diodes 161 to 164 for flowing charges in only one direction, and resistors 165 to 168 for adding charge amounts. Resistors 165-168
Have the same resistance value. The resistors 165 to 165 of the adder circuit 16
Since 168 also serves as the resistor 152 in FIG.
The integrating circuit 15A has no resistor.

FIG. 5 shows the operation of the phase error detection circuit configured as described above. In the figure, Q1 to Q4 are outputs of the D flip-flops 111 to 114, respectively, and V1 to V4 are outputs of the gates 115 to 118, respectively. Gate 115-
The output of 118 performs full swing between the power supply voltages like the charge pump 12 of FIG. Further, an amount of electric charge proportional to the difference between the positive pulse width of the outputs of the exclusive OR gates 115 and 118 and the negative pulse width of the outputs of the exclusive NOR gates 116 and 117 is discharged from the adder circuit 16, or It is sucked into the adder circuit 16.

Therefore, the output stage of the gates 115 to 118 and the adder circuit 16 constitute a charge pump, and the circuit of FIG. 4 has the error convergence pulse generation circuit 11B.
It can also be said that the configuration is such that the error converging pulse generation circuit, the charge pump, and the integrating circuit 15A in the part excluding the output stages of the gates 115 to 118 are connected in cascade. [Fourth Embodiment] FIG. 6 shows a delay lock circuit 1 according to the fourth embodiment.
Indicates 0B.

This circuit is a DLL (Delay) using a four-stage delay circuit 17 in place of the voltage controlled oscillator 14 of FIG.
Locked Loop) circuit for generating a plurality of clocks φ0 to φ3 whose phases are shifted from each other by a certain amount with respect to the input clock φ. Similar to the case of FIG. 1, the configuration is publicly known except that the integrating circuit 15 is connected between the output end of the charge pump 12 and the external terminal 23. 20B
Is a semiconductor integrated circuit.

The 4-stage delay circuit 17 controls the delay times of the delay circuits DL1 to DL4 by the output of the loop filter 13, and the phase difference between the input clock φ of the delay circuit DL1 and the output clock φ0 of the delay circuit DL4 is 2π. Converge to. FIG. 7 shows delay circuits DL1 to DL for the input clock φ when the phase error converges to zero.
Output clocks φ1 to φ3 and φ0 of L4 are shown.

[Fifth Embodiment] FIG. 8 shows a PLL circuit or D
The error detection circuit of a 5th example used for a LL circuit is shown. This circuit uses a complementary input / output type integration circuit 15B and a complementary output type charge pump 12A for high speed operation. The complementary input / output type operational amplifier circuit 151A is
A capacitor 15 is provided between the inverting input terminal and the non-inverting output terminal.
3A is connected, a capacitor 153B is connected between its non-inverting input terminal and its inverting output terminal, and its inverting and non-inverting input terminals are respectively connected to complementary output terminals of the charge pump 12A via resistors 152A and 152B. It is connected.

It is assumed that the widths of the up pulse UP and the down pulse DWN output from the error convergence pulse generation circuit 11C are constant. The output potentials VO and * VO of the integrating circuit 15B are equal to each other in the initial state, and are 0V, for example. In response to one up pulse UP from the error convergence pulse generation circuit 11C, the charge pump 12A
Discharges and inhales a certain amount of electric charge q that moves in the direction of the arrow in the figure from its complementary output end. As a result, the integration circuit 15
The output potential VO of B decreases by ΔV and the output potential * VO increases by ΔV. For one down pulse DWN, the reverse operation is performed.

When such an error detection circuit is used in the circuit of FIG. 1 or 6, the loop filter 13 also needs to be of the complementary input type. In addition, the present invention includes various modifications. For example, in FIG. 1 or 6, PNP
A constant current source is connected between the emitter of the transistor 121 and the power supply line VCC, and between the emitter of the NPN transistor 122 and the power supply line -VCC, respectively.
The input / output current of the charge pump may be constant, and in this case, the resistor 152 of the integrating circuit 15 is unnecessary.

The error converging pulse generation circuit 11 has
An error converging pulse generator of various known phase error detection circuits or frequency error detection circuits can be used. The voltage controlled oscillator 14 may be a separate semiconductor integrated circuit, or the loop filter 13 may be entirely incorporated in the semiconductor integrated circuit for downsizing.

[0033]

As described above, according to the error detecting circuit of the present invention, the output of the charge pump is integrated by the integrating circuit, unnecessary high frequency components are removed, and necessary information remains. The effect that even if the output contains parasitic capacitance or parasitic inductance, its effect will be small, and the signal for converging the error in frequency or phase can be output more accurately under high communication speed. Play.

According to the clock recovery circuit and the delay lock circuit using this error detection circuit, the loop filter has an external circuit and the communication speed is high, so that the parasitic capacitance of the output wiring of the charge pump or the like. Even when the above problem occurs, there is an effect that it can be used at a high communication speed for the above reason.

[Brief description of drawings]

FIG. 1 is a diagram showing a clock recovery circuit according to a first embodiment of the present invention.

FIG. 2 is a waveform chart showing the operation of the circuit of FIG.

3A is a diagram showing a phase error detection circuit according to a second embodiment of the present invention, and FIG. 3B is a waveform diagram showing the operation of FIG.

FIG. 4 is a diagram showing a phase error detection circuit according to a third embodiment of the present invention.

5 is a waveform chart showing the operation of the circuit of FIG.

FIG. 6 is a diagram showing a delay lock circuit according to a fourth embodiment of the present invention.

7 is a diagram showing input / output signals of a four-stage delay circuit in FIG.

FIG. 8 is a diagram showing an error detection circuit according to a fourth embodiment of the present invention.

FIG. 9 is a diagram showing a conventional clock recovery circuit.

[Explanation of symbols]

 10, 10A Clock reproduction circuit 10B Delay lock circuit 11, 11A to 11C Error convergence pulse generation circuit 12 Charge pump 13 Loop filter 14 Voltage controlled oscillator 15, 15A, 15B Integration circuit 131, 151, 151A Operational amplification circuit 16 Addition circuit 17 4-stage delay circuit 20, 20A semiconductor integrated circuit

Claims (6)

[Claims] 1. An error converging pulse generation circuit that outputs a pulse containing information for converging a frequency error or a phase error of a clock with respect to the serial signal in response to the input of the serial signal and the clock, and the pulse of the pulse. A charge pump that moves charge through the output in response to an input, and an input connected to the output of the charge pump that integrates the amount of charge that moves through the input and calculates the error from the output. An error detection circuit comprising: an integration circuit that outputs a signal. 2. The integrator circuit amplifies a potential difference between two input terminals, a reference potential is applied to one of the two input terminals, and the other of the two input terminals is coupled to the output terminal of the charge pump. 2. The error detection circuit according to claim 1, further comprising: an operational amplifier circuit, and a capacitor connected between the other of the two input terminals and an output terminal of the operational amplifier circuit. 3. The charge pump has complementary output terminals for outputting a pair of complementary signals, and the integrator circuit amplifies a potential difference between the non-inverting input terminal and the inverting input terminal to form a non-inverting output terminal. An operational amplifier circuit that outputs from an inverting output terminal, the non-inverting input terminal and the inverting input terminal are coupled to the complementary output terminal of the charge pump, and is connected between the non-inverting input terminal and the inverting output terminal. First done
A second capacitor connected between the capacitor and the inverting input and the non-inverting output
The error detection circuit according to claim 1, further comprising: a capacitor. 4. A semiconductor integrated circuit, comprising the error detection circuit according to claim 1, wherein the output end of the integration circuit is connected to an external terminal. 5. The error detection circuit according to claim 1, an input terminal connected to an output terminal of the integration circuit, and an input terminal connected to an output terminal of the loop filter. And a voltage controlled oscillator circuit which is connected and generates the reproduced clock having a frequency according to an input voltage. 6. The error detection circuit according to claim 1, a loop filter having an input end connected to an output end of the integration circuit, and a signal supplied to a data input end. A plurality of stages of delay circuits that delay according to the signal at the input end are connected in cascade, the clock is supplied to the data input end of the delay circuit at the first stage, and the output of the delay circuit at the final stage is the error-converging as the serial signal. A multi-stage delay circuit which is supplied to a pulse generation circuit for use, and the output signal of the loop filter is supplied to the control input terminal of each of the delay circuits of the plurality of stages.