JP2953431B2 - High-level synthesis device and recording medium thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a high-level synthesis apparatus for automatically generating a logic circuit from a behavioral level description.

[0002]

2. Description of the Related Art In recent years, LSI circuit design has become more and more complicated, and advanced functions and performance are required. In addition, the required development period is short, and it is desired to improve the design productivity in order to cope with them. For this reason, recently, a high-level synthesis apparatus that describes a logic circuit at an operation level and automatically generates connection data (logic circuit diagram and the like) at a logic gate level from the operation level description has been used. In this high-level synthesis device, the operation to be designed is described by an operation description language provided exclusively.

FIG. 7 is a block diagram showing a configuration of a conventional high-level synthesis apparatus. FIGS. 8A and 8B are diagrams for explaining the operation of the high-level synthesis apparatus shown in FIG. 7, in which FIG. 8A shows an example of the behavioral level description, and FIG. 8B shows the output from the translator shown in FIG. FIG. 4 is a data flow diagram illustrating an example of internal data according to the first embodiment. FIG. 9 is a data flow diagram showing an example of internal data output from the scheduling processing section shown in FIG.

[0004] In FIG. 7, the conventional high-level synthesis apparatus receives an operation level description as shown in FIG.
A translator 72 that creates internal data that can be represented by a data flow diagram as shown in (b), an arithmetic time library 73 in which arithmetic times of arithmetic units that perform predetermined arithmetic processing are recorded, and a logical circuit that generates logic A constraint condition storage unit 74 in which design constraint conditions such as a processing time (the number of clocks) and a desired operation time (clock cycle) of the operation time required for each operation unit to operate at the processing time are recorded;
The internal data output from the translator 72 is used as an input, and the operation time of each operation unit recorded in the operation time library 73 and the design constraint conditions recorded in the constraint condition storage unit 74 are referenced to consider sharing of resources. In addition, each operation unit is allocated so as to be within the processing time required for the logic circuit, and registers required for the operation process are allocated to each operation unit (see FIGS. 9A and 9B; ), And a synthesizing unit 76 that generates a logic circuit at a logic gate level from the internal data output from the scheduling processing unit 75.

In such a configuration, in the conventional high-level synthesis apparatus, for example, in order to reduce the processing time and the scale of the synthesized logic circuit, for example, the scheduling processing unit 7
In No. 5, the operation order of the operation level description was changed, the operation was shared, and the like.

[0006]

However, in the above-described conventional high-level synthesizing apparatus, the scheduling process is performed in units of arithmetic units, so that the operation time is specified by design constraints, for example, as in a multi-bit arithmetic unit. If the clock cycle is longer than the clock cycle, the arithmetic unit becomes a critical path, and the generated logic circuit does not operate at a desired frequency.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems of the prior art, and requires an arithmetic unit requiring an arithmetic operation time longer than a desired time (clock cycle) given as a design constraint condition. It is an object of the present invention to provide a high-level synthesis device that generates a logic circuit that operates at a desired frequency even when the description is in the operation level description.

[0008]

To achieve the above object, a high-level synthesis apparatus according to the present invention is a high-level synthesis apparatus for automatically generating a logic circuit from a behavioral level description. A translator that analyzes and creates internal data for synthesizing a desired logic circuit, and a computing unit that performs a predetermined computation process from the internal data are all extracted, and the computing time of the computing unit is determined by the logic circuit. It is determined whether the operation time is within the desired time required to operate at the frequency. A bit decomposing unit for decomposing the data into operation units, and assigning each operation unit to a processing time required for the logic circuit based on a processing result of the bit decomposition processing unit; Wherein the scheduling processing unit which allocates respective registers required for each operation unit, and a synthesizing unit for generating a logic circuit of the logic gate level from the processing result of the scheduling processing unit, to have to.

A recording medium according to the present invention is a recording medium in which a program for automatically generating a logic circuit from a behavioral level description is recorded. A translator process for creating internal data for synthesis, and all the arithmetic units that perform predetermined arithmetic processing are extracted from the internal data, and the arithmetic time of the arithmetic unit is set to operate the logic circuit at a desired frequency. Bit decomposition for judging whether or not the required time is within the required time, and decomposing the operation unit requiring the operation time exceeding the desired time into a plurality of operation units having the number of bits within the desired time. From the processing results of the bit separation processing unit, processing units are allocated so as to be within the processing time required for the logic circuit, and registers necessary for the processing are A scheduling process for allocating to each calculator, is obtained by recording a program for executing a combining process, to high-level synthesis apparatus for generating a logic circuit of the logic gate level from the processing result of the scheduling processing unit.

The high-level synthesizer configured as described above has
The bit decomposition processing unit extracts all the arithmetic units that perform the predetermined arithmetic processing from the internal data, and determines whether the arithmetic time of the arithmetic units is within a desired time required to operate the logic circuit at a desired frequency. It is determined whether or not each of the calculation units requires a calculation time exceeding the desired time, and the calculation unit is decomposed into a plurality of calculation units having the number of bits within the desired time. Therefore, since the operation time of all the arithmetic units falls within the desired time, an accurate scheduling process can be performed.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

The high-level synthesis apparatus according to the present invention has a configuration in which a bit decomposition processing section is added to a stage preceding the scheduling processing section of the conventional high-level synthesis apparatus shown in FIG. The bit disassembly processing unit compares the operation time of each operation unit with the clock cycle specified by the design constraint condition, and determines the operation unit that requires an operation time longer than the clock period by the number of bits for which the operation time falls within the clock period. A bit decomposition process for decomposing into a plurality of arithmetic units is performed.

FIG. 1 is a block diagram showing the configuration of a high-level synthesis apparatus according to the present invention.

In FIG. 1, the high-level synthesis apparatus of the present invention comprises:
A translator 1 that parses the input operation level description and creates internal data represented by a data flow diagram and the like; an operation time library 3 in which operation times of operation units that perform predetermined operation processing are recorded; Design constraints such as the processing time (the number of clocks) of the logic circuit to be generated and the desired operation time (hereinafter referred to as a clock cycle) required for each operation unit to operate with the processing time are recorded. Constraint condition storage unit 4 and operation time library 3
Time and constraint condition storage unit 4 of each computing unit recorded in
A bit decomposition processing unit 2 for performing a bit decomposition process of the arithmetic unit when the operation time of the arithmetic unit is equal to or longer than the clock cycle with reference to the design constraint conditions recorded in A scheduling processing unit 5 for performing a scheduling process by inputting data and referring to the operation time of each operation unit recorded in the operation time library 3 and the design constraints recorded in the constraint condition storage unit 4; And a synthesizing unit 6 for generating a logic circuit at a logic gate level from the internal data output from the logic circuit 5.

In such a configuration, the operation of the high-level synthesis apparatus according to the present invention will be described next with reference to FIGS.

FIG. 2 is a flowchart showing a processing procedure of the bit decomposition processing section shown in FIG. FIG. 3 is a diagram for explaining the operation of the high-level synthesis device shown in FIG. 1, and FIG.
Is a diagram showing an example of the behavioral level description, FIG. 4B is a data flow diagram showing an example of internal data output from the translator, and FIG. 4C is a diagram showing an example of internal data output from the bit decomposition processing section. It is a data flow diagram shown.

In FIG. 2, the bit decomposition processing unit 2 extracts all the arithmetic units that perform predetermined arithmetic processing from the internal data output from the translator 1 (Step S).
1) The operation time of each operation unit is compared with the clock cycle with reference to the contents of the operation time library 3 (step S2). Next, the operation unit whose operation time is equal to or longer than the clock period is decomposed into a plurality of operation units each having the number of bits whose operation time falls within the clock period (step S3).

For example, when the translator 1 outputs internal data as shown in FIG. 3B with respect to the behavior level description shown in FIG. 3A, the bit decomposition processing unit 2 outputs the data output from the translator 1. From the internal data, the first
3 (FIG. 3B) and a second computing unit (FIG. 3B).
(B) are extracted (step S1). Here, when the operation time of each of the first arithmetic unit and the second arithmetic unit is equal to or longer than the clock cycle (step S2), the bit decomposition process 2 performs the first operation as shown in the data flow diagram of FIG. Is decomposed into 'and', and the second operator is decomposed into 'and' (step S3).

In FIG. 3C, Am to Em indicate signals composed of upper bits (including the MSB) of the signals A to E, respectively, and Al to El indicate the signals A to El, respectively.
A signal composed of lower bits including the LSB of E is shown.

In the configuration of the high-level synthesis apparatus according to the present embodiment, the translator 1, the bit decomposition processing unit 2,
Each processing executed by the scheduling processing unit 5 and the synthesis unit 6 may be performed by a computer including a CPU. In that case, the computer has a recording medium (not shown) in which a processing program for high-level synthesis is recorded, and each processing procedure for high-level synthesis described above is executed according to the processing program recorded in the recording medium. . Here, the recording medium may be a magnetic disk, a semiconductor memory, or another recording medium.

[0021]

Next, embodiments of the present invention will be described with reference to the drawings.

FIGS. 4A and 4B are diagrams for explaining the operation of the embodiment of the high-level synthesis apparatus according to the present invention. FIG. 4A shows the relationship between the operation time of the arithmetic unit and the clock cycle, and FIG. FIG. 3C is a data flow diagram showing internal data output from the translator, and FIG. 3C is a data flow diagram showing internal data output from the bit decomposition processing section. FIG. 5 is a diagram for explaining the operation of the embodiment of the high-level synthesis device of the present invention. FIG. 5A is a data flow diagram showing an example of internal data output from the scheduling processing unit, and FIG. It is a data flow figure showing other examples of internal data outputted from a scheduling processing part. FIG. 6 is a diagram showing a configuration of a logic circuit generated by the synthesis unit shown in FIG. 1. FIG. 6A is a block diagram of a logic circuit generated when there is no bit decomposition processing unit. 5B is a block diagram of a logic circuit generated by the internal data shown in FIG. 5B, and FIG. 5C is a block diagram of a logic circuit generated by the internal data shown in FIG. It is.

In this embodiment, the operation level description input to the high-level synthesis device includes a 100-bit adder of z (99down0) = x (99down0) + y (99downto0) (1). An example in which the calculation time of the delay time is Delay1 will be described.

The 100-bit adder is decomposed into two 50-bit adders whose operation time is Delay2 by the bit decomposing unit 2, and Delay1, Delay
It is assumed that y2 and the clock cycle T have a relationship as shown in FIG.

When the translator 1 outputs internal data as shown in the data flow diagram of FIG. 4 (b), the bit decomposition processing unit 2 sets 100bi in which Delay1> T holds.
The t adder is divided into two 50 bits where Delay2 <T.
A bit decomposition process for decomposing the data into adders is performed, and based on the internal data output from the translator 1, internal data as shown in FIG.

Next, the scheduling processing unit 5 performs a scheduling process with reference to the contents of the calculation time library 3 and the constraint condition storage unit 4, and performs a scheduling process as shown in FIG. 5 (a) or 5 (b). Outputs internal data including registers R1 to R8 and selectors SEL1 to SEL3.

The combining section 6 outputs a logic circuit as shown in FIG. 6B based on the internal data shown in FIG. Also, based on the internal data shown in FIG.
A logic circuit as shown in FIG.

When the bit separation processing unit 2 is not provided as in the conventional high-level synthesis apparatus shown in FIG.
A logic circuit as shown in FIG. 6A is output for the internal data as shown in the data flow diagram of FIG.

Therefore, the operation time required for the operation time longer than the clock period, such as a multi-bit operation unit, is divided into a plurality of operation units within the clock period by the operation time. In the clock cycle. Therefore, since accurate scheduling processing can be performed, a logic circuit that satisfies design constraints can be generated even if there is an operation level description including an arithmetic unit that requires an operation time longer than a desired clock cycle.

FIGS. 4C, 5A, and 5
In (b), xm to zm indicate signals composed of upper bits (including the MSB) of the signals x to z, respectively, and x
1 to z1 indicate signals composed of lower bits including the LSB of the signals x to z, respectively.

[0031]

Since the present invention is configured as described above, the following effects can be obtained.

An arithmetic unit which requires an operation time exceeding a desired time, such as a multi-bit arithmetic unit, is decomposed into a plurality of arithmetic units having the number of bits within which the operation time can be accommodated within the desired time. The time can be set within the desired time. Therefore, since accurate scheduling processing can be performed, a logic circuit that satisfies design constraints can be generated even for an operation level description having an operation unit that requires an operation time longer than a desired time.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a high-level synthesis device according to the present invention.

FIG. 2 is a flowchart illustrating a processing procedure of a bit decomposition processing unit illustrated in FIG. 1;

3A and 3B are diagrams for explaining the operation of the high-level synthesis device shown in FIG. 1; FIG. 3A shows an example of a behavior level description;
FIG. 2B is a data flow diagram showing an example of internal data output from the translator, and FIG. 2C is a data flow diagram showing an example of internal data output from the bit decomposition processing section.

4A and 4B are diagrams for explaining the operation of the embodiment of the high-level synthesis apparatus according to the present invention, wherein FIG. 4A shows the relationship between the operation time of a computing unit and a clock cycle, and FIG. FIG. 4C is a data flow diagram showing the internal data output from the bit decomposition processing unit, and FIG.

FIG. 5 is a diagram for explaining the operation of the embodiment of the high-level synthesis device of the present invention. FIG. 5A is a data flow diagram showing an example of internal data output from the scheduling processing unit, and FIG. FIG. 8 is a data flow diagram showing another example of internal data output from the scheduling processing unit.

6A and 6B are diagrams illustrating a configuration of a logic circuit generated by a synthesis unit illustrated in FIG. 1; FIG. 6A is a block diagram of a logic circuit generated when there is no bit decomposition processing unit; (B)
5 is a block diagram of a logic circuit generated by the internal data shown in FIG. 5B, and FIG. 5C is a block diagram of a logic circuit generated by the internal data shown in FIG.

FIG. 7 is a block diagram illustrating a configuration of a conventional high-level synthesis device.

8 is a diagram for explaining the operation of the high-level synthesis device shown in FIG. 7; FIG. 8A is a diagram showing an example of a behavior level description;
FIG. 2B is a data flow diagram showing an example of internal data output from the translator shown in FIG.

FIG. 9 is a data flow diagram illustrating an example of internal data output from the scheduling processing section illustrated in FIG. 7;

[Explanation of symbols]

 Reference Signs List 1 translator 2 bit decomposition processing unit 3 operation time library 4 constraint condition storage unit 5 scheduling processing unit 6 synthesis unit

Claims (2)

(57) [Claims] 1. A high-level synthesis apparatus that automatically generates a logic circuit from a behavioral level description, comprising: a translator that parses an input behavioral level description and creates internal data for synthesizing a desired logic circuit; And extracting all arithmetic units that perform predetermined arithmetic processing from the internal data, and determining whether the arithmetic time of the arithmetic unit is within a desired time required to operate the logic circuit at a desired frequency. And a bit decomposition processing unit that decomposes an operation unit that requires an operation time longer than the desired time into a plurality of operation units of a number of bits that can be processed within the desired time; and a process performed by the bit decomposition processing unit. Based on the result, a scheduler for allocating each arithmetic unit so as to be within the processing time required for the logic circuit and allocating registers required for the arithmetic processing to each arithmetic unit. A high-level synthesis device, comprising: a processing unit; and a synthesis unit that generates a logic circuit at a logic gate level from a processing result of the scheduling processing unit. 2. A recording medium on which a program for automatically generating a logic circuit from a behavioral level description is recorded. The recording medium parses an inputted behavioral level description and stores internal data for synthesizing a desired logic circuit. A translator process to be created, and all arithmetic units that perform a predetermined arithmetic process are extracted from the internal data, and the arithmetic time of the arithmetic unit is within a desired time required to operate the logic circuit at a desired frequency. A bit decomposition process for determining whether or not there is any of them, and decomposing an operation unit requiring an operation time exceeding the desired time into a plurality of operation units having a number of bits within the operation time within the desired time; Based on the processing results of the sections, each operation unit is allocated so as to be within the processing time required for the logic circuit, and registers necessary for the operation processing are allocated to each operation unit. A recording medium that stores a program for causing a high-level synthesis device to execute a scheduling process to attach, and a synthesis process to generate a logic circuit at a logic gate level from a processing result of the scheduling processing unit.