JP2002222228A - High order synthesizing system and high order synthesizing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To produce hardware with enhanced circuit parallel operability by providing minimum constraint information without changing an operation description to be an input of high order synthesizing, a register transfer level description to be an output, or the like. SOLUTION: This system has a C/DFG generating part (an operation description analyzing part) 103 analyzing the operation description 101 describing an operation of an object logical circuit or the like, a constraint analyzing part 104 analyzing a constraint or the like of the operation of the object logical circuit or the like to an input signal and an output signal, a displaying/editing part 108 displaying an analysis result of the constraint or the like and modifying it, and synthesizing parts 105-107 performing high order synthesizing based on an analysis result by the C/DFG generating part 103, the analysis result by the constraint analyzing part 104 or an editing result of the displaying/editing part 108. A displaying part displays variables during description and the input and output signals of the logical circuit per cycle or it displays them on a CDFG diagram in coordination with the input and output signals.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high-level synthesis system and a high-level synthesis method used for designing a logic circuit or the like and automatically synthesizing a logic circuit from an operation description.

[0002]

2. Description of the Related Art In designing a logic circuit such as a system LSI, an RTL (Register Transfer Level) is described from an operation description.
l) High-level synthesis is performed when moving to design. As the high-level synthesis, for example, a hardware logic circuit (Register Transfar Level H) that performs parallel operation by inputting an algorithm description (operation description) in a software programming language of a sequential operation such as C / C ++ language is input.
DL (Hardware Description Language) description or Gat
Some generate eLever HDL (Hardware Description Language) description.

In this high-level synthesis, constraints ("circuit operation timing constraints on input signals", "output signal update timing constraints", etc.) conventionally specified include "input terminal signals, their bit widths, output terminal signals, and their bit Width, operating clock frequency (or one cycle time).

The circuit operation realized in this case includes:
The value of the input signal is set, and a circuit operation equivalent to the algorithm description function is executed, and the result is the value of the output signal. That is, a circuit is generated that assumes that the input signal does not change during the execution of the circuit operation. You.

However, in general, in designing a logic circuit, when an increase in the number of circuit gates is suppressed by hardware, an overall parallel operation, an improvement in processing throughput, and the like are performed, a time division setting of an input signal and a pipeline operation are performed. I want to realize circuit operation such as input setting for.

[0006]

However, at present, in order to realize the above-described circuit operation, the input / output structure of the hardware must be changed to the register transfer level HD.
There is a problem that it is necessary to manually design an L description or the like, and the work is complicated.

Therefore, the present invention improves the circuit parallel operability by giving the minimum necessary constraint information without changing the operation description as the input of the high-level synthesis or the register transfer level description as the output. It is an object to provide a high-level synthesis system and a high-level synthesis method capable of generating hardware.

[0008]

SUMMARY OF THE INVENTION The present invention has been made in order to solve the above-mentioned problem, and in a high-level synthesis system used for designing a logic circuit or the like, an operation description describing the operation of a target logic circuit or the like is provided. An operation description analysis unit for analyzing, a constraint analysis unit for analyzing constraints on operations of input signals and output signals of the target logic circuit and the like, a display unit for displaying an analysis result of the constraints and the like, and analysis of the constraints and the like An editing unit for correcting the result, and a synthesizing unit for performing high-level synthesis based on the analysis result by the behavioral description analyzing unit and the analysis result by the constraint analyzing unit or the editing result in the editing unit. It is.

According to another aspect of the present invention, in a high-level synthesis method used for designing a logic circuit, an operation description describing an operation of a logic circuit to be designed is analyzed, and an operation for an input signal and an output signal of the logic circuit is performed. Analyzing the constraint, displaying the analysis result of the constraint, correcting the analysis result of the constraint based on the display, analyzing the operation description, the analysis result of the constraint, or editing in the editing unit. High-level synthesis is performed based on the result.

According to these inventions, by giving or changing the minimum necessary constraint information as a constraint without changing the operation description which is the input of the high-level synthesis, the parallel operation of the circuit can be performed. It is possible to generate hardware in consideration of the hardware configuration and operation.

In the present invention, it is preferable that the editing unit has an interface unit for correcting an analysis result of the restriction or the like by an operation on a screen displayed by a display unit.

In the case where an interface section for correcting constraints by operation on the screen is provided, the analysis results are displayed graphically, so that the constraints can be visually confirmed and the correction work is easy. become. In particular, when the interface unit is provided, the correspondence between the data transfer input signal and the output signal operation can be displayed on a data flow graph, and the cycle timing of the input signal and the output signal of the hardware for the data transfer operation can be displayed. Can be easily grasped and confirmed, and more appropriate hardware input signal and output signal cycle timing and hardware conversion can be realized.

According to the present invention, the display unit displays, in the operation description, a variable in an operation description which is a constraint on an input signal and an output signal of the target logic circuit and the like, and an input signal and an output signal of the target logic circuit and the like. , A function of displaying each cycle operation can be provided.

In this case, the operation description which is an input of the high-level synthesis is not changed, and each cycle operation of the input / output timing is designated as a constraint, so that hardware considering the hardware configuration and operation of the circuit can be realized. Can be generated.

Further, in the present invention, the display unit may be provided with a function of displaying, on a data flow diagram, the correspondence between the scheduling, the variables in the operation description, and the input and output signals of the hardware. .

In this case, by displaying each cycle operation of the operation description and the hardware input signal and output signal on a data flow graph, the specified cycle operation can be easily understood and confirmed. It is possible to change designation of a constraint in consideration of an operation description and generate hardware in consideration of a constraint operation.

Further, in the present invention, the display section may be provided with a function of displaying the input signal and the output signal of the target logic circuit etc. in association with each other on the data flow diagram.

In this case, on the data flow graph display, each input / output terminal is distinguished and displayed, so that transmission / reception of signals to / from each variable in the operation description and resource relationship of each input / output terminal can be performed. It is possible to easily grasp the collision of the input / output terminal resources, that is, the resource shortage, or the redundancy of the input / output terminal resources, that is, the possibility of sharing the resources.

Also, in the present invention, the display unit includes:
A function may be provided on the data flow diagram for displaying the correspondence between the presence / absence of the holding of the input signal and the output signal value of the target logic circuit and the presence / absence of the updating.

In this case, the data holding operation over the clock cycle is explicitly displayed on the data flow graph on the data flow graph, so that the internal operation of the hardware and the input / output terminals given by the restrictions are performed. , It is possible to easily understand and confirm the relationship between the transmission and reception of the value, and to change the designation of the constraint in consideration of the operation description and generate the hardware in consideration of the constraint operation.

Further, in the present invention, the display unit includes
On the data flow diagram, a function for displaying the correspondence between the variable in the operation description and the data transfer input signal and output signal operation of the hardware may be provided.

In this case, on the data flow graph,
By modifying the correspondence between the variables in the behavioral description and the input and output signals of the hardware, it is easy to convert the behavioral description into hardware by high-level synthesis and the relationship between the cycle timing of the input and output signals of the hardware. It is possible to realize more appropriate hardware input signal and output signal cycle timing and hardware conversion.

Further, in the present invention, the display unit has a function of displaying an analysis result by the constraint analysis unit as a state transition diagram, and the editing unit corrects the state transition diagram displayed on the display screen. Thus, it is preferable to provide a function of correcting the analysis result such as the restriction.

In this case, the input signal and output signal operation given as the constraint designation are displayed as a state transition diagram.
And, by being able to make corrections, it is easy to confirm and correct the constraints.

[0025]

DESCRIPTION OF THE PREFERRED EMBODIMENTS [Configuration of High-Level Synthesis System] A first embodiment of a high-level synthesis system of the present invention will be described below. FIG. 1 is a block diagram illustrating the configuration of the high-level synthesis system according to the present embodiment.

As shown in FIG. 1, the high-level synthesis device according to the present embodiment includes a C / DFG generation unit 103 and a constraint analysis unit 1.
04, a scheduling unit 105, a hardware location unit 106, an RTL description generation unit 107, a display / editing unit 108, a display 109, and an input device 110.

The C / DFG generation unit 103 is an operation description analysis unit for analyzing the input operation description 101. In the present embodiment, the C / DFG generation unit 103 performs the operation description 10 based on the analysis result.
1 generates a data flow graph showing the data dependency between variables in the constraint analysis unit 104 and the scheduling unit 1
05 is output.

Here, the operation description 101 represents what operation the logic circuit to be designed performs.
FIG. 2 is a simple example of a behavioral description, which is an input for high-level synthesis and corresponds to the behavioral description 101 in FIG. In the operation description shown in FIG.
2, and that a2 and a3 are multiplied to output variables b1 and b2, respectively.

The constraint analysis unit 104 is a constraint analysis unit for analyzing the input constraint specification 102. In this embodiment,
Based on the analysis result here, the variables and the like of the data flow graph generated from the behavioral description 103 and the constraint specification 102
And outputs the corresponding data flow graph and constraint to the display / editing unit 108.

Here, the constraint specification 102 is an operation description 1
3 shows input / output terminal information of a hardware module of a logic circuit to be designed and variables in 01. FIG. 3 is an example of the constraint designation, and corresponds to the constraint designation 102 in FIG. However, the example of constraint specification shown in FIG.
, A2 and a3 are designated as input terminals having a bit width of 16 bits, and variables b1 and b2 are designated as output signals having a bit width of 16 bits. This is a level constraint designated in the conventional high-level synthesis.

In the display / editing unit 108, when there is a modification and addition to the data flow graph and the constraint in the display / editing unit 108, the changed information is reflected in the constraint designation description 102.

The scheduling section 105 constitutes a synthesizing section for performing high-level synthesis. The scheduling section 105 obtains the data flow graph from the C / DFG generating section 103 and applies the data flow graph to the constraints obtained from the display / editing section 108 in the logic circuit. Adjust the number of clocks. The result of scheduling by the scheduling unit 105 is output to the hardware location unit 106.

The hardware location unit 106 also constitutes a synthesizing unit, and the scheduling unit 105
And the display / editing unit 1
Circuit assignment is performed based on the data flow graph acquired from step 08. The result of the hardware location by the hardware location unit 106 is output to the RTL description generation unit 107.

The RTL description generation unit 107 also constitutes a synthesis unit, performs high-level synthesis processing based on the hardware location result, and outputs the RTL description 111.

The display / edit section 108 is a display section for displaying the analysis result of the constraint and the like, and is an editing section for correcting the analysis result of the constraint and the like. That is, in the present embodiment, graphic data is generated based on the data flow graph and the constraint input from the constraint analysis unit 104, displayed on the display 109, and displayed on the display 109 by the input device 110. It has an interface unit for modifying and adding to.

In the display / editing unit 108,
If the data flow graph and the constraints have been modified, the changed information is sent to the C / DFG generation unit 103,
The output to the scheduling unit 105 and the hardware location unit 106 and the constraint analysis unit 104
And is reflected in the constraint specification description 102.

The display 109 includes the display / editing unit 10
Based on the graphic data generated in step 8, the data flow graph and the state of the constraint are visually displayed. The input device 110 is an external input interface to the present system, and uses a keyboard, a mouse, and the like.

[Operation of High-Level Synthesis System] The high-level synthesis system having the above-described configuration according to the present embodiment operates as follows. Here, the operation description and constraint specification shown in FIGS. 2 and 3 will be described as an example.

First, the constraint designation 102 as shown in FIG.
Is input to the constraint analysis 104, and the behavioral description 101 as shown in FIG. 2 is input to the C / DFG generation unit 103.

Next, the behavior description 101 is analyzed by the C / DFG generation unit 103, and the behavior description 10
1 generates a data flow graph showing the data dependency between variables in the constraint analysis unit 104 and the scheduling unit 1
05 is output.

FIG. 4 is a control data flow graph generated by the C / DFG generator 103. As shown in the figure, in the data flow in the present embodiment, input variables a1 and a2 and a2 and a3 are multiplied at nodes 201 and 202, respectively, and input variables b1 and b
2 is described.

On the other hand, the constraint analysis unit 104
2 is analyzed, and the variables and the like of the data flow graph generated from the operation description 103 are associated with the constraints that are the analysis results of the constraint specification 102, and the corresponding data flow graph and constraints are displayed / edited. Output to the unit 108. The display / editing unit 108 generates graphic data based on the data flow graph and the constraints, and displays the graphic data on the display 109.

Further, the data flow graph is represented by C / D
The FG generation unit 103 outputs the result to the scheduling unit 105, and the scheduling result is output to the hardware location unit 106.

Here, the control section is not shown in the data flow graph in the present embodiment. Also,
The result of the synthesis is a combinational circuit, which is an operation within one clock without a clock and a control unit. The data flow graph after being scheduled by the scheduling unit 105 in FIG. 1 is the same as that in FIG.

Then, the hardware location unit 10
6 is output to the RTL description generation unit 107, and the RTL description generation unit 10
At 7, the RTL description 111 of the logic circuit is output. FIG. 5 is an example of a logic circuit diagram of the logic circuit synthesized here. The input variables a1 and a2 and a2 and a3 are
The multipliers 203 and 204 respectively multiply and output the output variables b1 and b2.

In the display / editing section 108, the input device 110 can correct or add restrictions on the displayed graphic. And a display / editing unit 10
8, when there is a correction addition to the data flow graph and the constraint, the changed information is output to the C / DFG generation unit 103, the scheduling unit 105, and the hardware location unit 106, and the change is reflected. High-level synthesis is continued. The change information is also output to the constraint analysis unit 104 and is reflected in the constraint specification description 102.

[Editing Operation] An example of actually editing the above-described constraint specification will be described below. Here, instead of the above-described constraint designation in FIG. 3, the constraint is designated as shown in FIG.

In the constraint specification shown in FIG. 6, the input terminal a declares a bit width of 16 bits, the input terminal reset declares the bit width of the input variables a1, a2 and a3 in the operation description as DummyIn, The output terminal b declares the bit width of the output variables b1 and b2 in the operation description as a 16-bit bit width and DummyOut, and the timing of transfer of the input terminal and the input variable, and the output terminal and the output variable.

Here, in the first cycle, the value of the input terminal a is given to the variable a1, and in the second cycle, the value of the input terminal a is given to the variable a2, and the value of the variable b1 is given to the output terminal b.
In the third cycle, the value of the input terminal a is given to the variable a3, and the value of the variable b2 is given to the output terminal b. Then, the operation in the first cycle is repeated. And an input terminal which is a reset signal
When the reset becomes zero, the operation in the first cycle is synchronized with the clock, and the value of the input terminal a is given to the variable a1.

FIGS. 7 and 8 show constraints specifying different timings. FIG. 9 is a logic circuit diagram showing an example of a result synthesized by the constraint designation of FIG.

When the constraint designation of FIG. 6 is given as described above, the display / editing unit 108
FIG. 10 shows a data flow graph as shown in FIG. FIG. 10 shows on the data flow graph the transfer relationship and the cycle timing of the values of the input / output terminals given as constraints with respect to the operation description shown in FIG. 2 and the data flow graph shown in FIG. ing.

More specifically, as shown in FIG. 9, CLK and reset are input to the control circuit 205 as input signals, and the control circuit 205 controls the timing control circuit 2.
06 and 207 adjust the timing of transferring the input variables to the multiplier 208.

More specifically, the timing control circuits 206 and 207 pass the value of the input terminal a as a variable a1 to the multiplier 208 in the first cycle, and then change the value of the input terminal a to the variable in the second cycle. Multiplier 208 as a2
And the value of the variable b1 is output from the output terminal b. Further, in the third cycle, the value of the input terminal a is passed to the multiplier 208 as the variable a3, and the value of the variable b2 is passed to the output terminal b.

The logic circuit shown in FIG.
As shown in (2), the multiplication processing and data input / output performed by the multiplier 208 described above are displayed as nodes 209 and 210.

[Operation and Effect of High-Level Synthesis System] As described above, according to the high-level synthesis system according to the present embodiment, the operation description 101 which is an input of the high-level synthesis is not changed in the display / editing unit 108, and By giving or changing the minimum constraint information, it is possible to generate hardware (RTL description) in consideration of the hardware configuration and operation such as the parallel operability of the circuit. The constraints are analyzed and displayed graphically, which facilitates checking and correcting the constraints.

According to the present embodiment, the specified cycle operation can be easily understood by displaying each cycle operation of the operation description and the hardware input signal and output signal on a data flow graph. In addition to confirmation, it is possible to change the designation of a constraint in consideration of the operation description and generate hardware in consideration of the constraint operation.

Further, according to the high-level synthesis system according to the present embodiment, the operation description which is the input of the high-level synthesis is not changed, and each cycle operation of the input / output timing is specified as a constraint, thereby realizing the hardware of the circuit. Hardware that considers the configuration and operation can be generated.

[Modifications] The present invention is not limited to the above-described embodiment, and the following modifications can be made.

(Modification 1) For example, when a data flow graph corresponding to an operation description and a cycle operation related to the transfer of the value of an input / output terminal corresponding to a constraint are displayed together as a data flow graph, FIG. As shown, each input terminal, each output terminal, and each bidirectional input / output terminal may be assigned to each column of the data flow graph display and displayed.

More specifically, as shown in the figure, the multiplication process performed by the multiplier is displayed as nodes 211 and 212, the input corresponding thereto is displayed in the left column a, and the output is displayed in the right column b. I do.

According to such a modification, the input / output terminals are distinguished and displayed on the data flow graph display, so that signals can be transmitted / received to / from each variable in the operation description and the resources of each input / output terminal can be used. Relationships can be easily understood,
It is possible to understand the collision of the input / output terminal resources, that is, the resource shortage, or the redundancy of the input / output terminal resources, that is, the possibility of resource sharing.

(Modification 2) When displaying a data flow graph, as shown in FIG. 12, an operation in which a variable such as an input variable or an output variable holds a data value over a clock cycle is referred to as a data flow graph. You may make it display on a flow graph.

For example, in the figure, the multiplication process performed by the multiplier is displayed as nodes 213 and 214, and the input and output to and from the nodes are displayed in a time-series manner for each cycle, and data retention between cycles is displayed. It is displayed as marks 313 and 314.

According to such a modification, the data holding operation over the clock cycle is displayed on the data flow graph on the data flow graph, so that the internal operation of the hardware and the input given by the constraint are restricted. It is possible to easily understand and confirm the relationship between the transfer of the values of the output terminals, change the designation of constraints in consideration of the operation description, and generate hardware in consideration of the constraint operation.

(Modification 3) When the constraints shown in FIG. 13 are specified for the operation description shown in FIG. 2, the data flow graph becomes as shown in FIG. Here, in the scheduling unit of the high-level synthesis, when the time of the operation processing (nodes 215 and 216) of the 16-bit multiplier is estimated, the operation processing time is longer than the period 10 ns of the clock CLK, and the operation processing of the 16-bit multiplier is performed. Outputs a message that two cycles are required.

On the other hand, a designer who is executing high-level synthesis can correct the constraint on the data flow graph display. As shown in the data flow graph shown in FIG. Is changed from the second cycle to the first cycle.

In FIG. 15, the variable a2 of the portion that passes the value of the input terminal in2 shown in the second cycle in FIG. 14 to the input variable a2 is dragged by the designer from the second cycle to the first cycle. It is corrected so that the value of the input terminal in2 is passed to the input variable a2 in the first cycle. In FIG. 15, nodes 217 and 218 representing the arithmetic processing by the multiplier reflect the fact that the arithmetic processing of the 16-bit multiplier takes two cycles.
It is shown that it takes two cycles across the clock break.

FIG. 16 shows a display of the same data flow graph in which the display options are changed so that the data value retention over the clock cycle and the data transfer relationship with the arithmetic unit and the like are indicated by marks. This is one of the display examples in the case of "1".

In this data flow graph display, the values of the variables a1 and a2 in the first cycle are input to the multiplier (node 221), and the values of the variables a1 and a2 in the first cycle are held in the second cycle, respectively. (Marks 221, 222, 223 a), being input to the multiplier, the value of the variable a 2 is held even in the third cycle (mark 223 b), and the value of the variable a 3 and the value of the variable a 2 are multiplied by the multiplier ( Node 220), the values of the variables a3 and a2 in the third cycle are held (marks 224 and 225) in the fourth cycle, respectively, and are input to the multiplier (node 220). ing.

FIG. 17 is an example of a constraint specification output reflecting the constraint specification modified in the data flow graph of FIG. Then, a logic circuit as shown in FIG. 18 is generated based on the constraint specification thus modified. That is, as shown in the figure, the timing control circuits 227 and 228 are controlled by the control circuit 226,
The output from these timing control circuits 227 and 228 is optimized for a simple structure in which the output is input to a multiplier 229.

According to such a modification, the correspondence between the variables in the operation description and the input and output signals of the hardware is modified on the data flow graph, whereby the operation description by the high-level synthesis is implemented in hardware. The relationship between the conversion and the cycle timing of the input signal and the output signal of the hardware can be easily grasped and confirmed, and more appropriate cycle timing of the input signal and the output signal of the hardware and the conversion to hardware can be realized.

(Modification 4) In the case where a data transfer input / output operation as shown in FIG. 22 is realized with respect to the operation description shown in FIG. 2, the following changes can be made.

In FIG. 22, an input signal req_in is a signal for notifying data transfer, and after req_in has a value of 1, input data is continuously input to input d_in, and req_in
Returns to the value 0, the input data transfer to d_in stops. Further, the result of the arithmetic processing is continuously output as an output signal d_out in each clock cycle. d_out
An output signal req_out is output as a signal notifying that data is output from. FIG. 19 shows an example of a constraint specification for generating hardware for such a data transfer input / output operation.

In the constraint designation shown in FIG. 19, seven states (State S0
~ State S6), the signal input / output operation in the standby state or each data processing state and the designation of the next state are shown. The data flow graph display of FIG. 20 shows the correspondence between the variable in the operation description, the input signal and the output signal terminal, and the arithmetic processing (the same as that described in FIG. 10 of the above-described embodiment or FIG. 11 of the first modification). This is a data flow graph displaying the nodes 230 and 231).

FIG. 21 shows an example in which, in the data flow graph display of FIG. 20, other input / output operations given by designating constraints are also displayed on the data flow graph. In the data flow graph display of FIG. 20, in the constraint specification of FIG.
The data flow graph of the operation corresponding to each state of State S1, State S2, StateS3, and State S6 is displayed.

In FIG. 21, a data flow graph in which the states of State S4, State S2, and State S3 are inserted in the portion indicated by a frame 334, that is, State S1, State S2, and Stat
The data flow graph of the operation corresponding to each state of eS3, State S4, State S2, State S3, and State S6 is displayed.

By changing the display designation, the State S
1, State S2, State S3, State S4, State S2, State S
The data flow graph of the operation corresponding to each state of 5 can be displayed, and the data flow graph corresponding to each of the other transitionable states can be displayed.

FIG. 23 is a simplified logic circuit diagram of the logic circuit synthesized in this case. That is, as shown in FIG.
7, 238 and 240, the multiplier 2
It controls the data input to and output from 39.

According to such a modification, each state sequence corresponding to the data transfer input / output operation can be displayed on the data flow graph, so that the variables in the operation description and the operation description by high-level synthesis can be implemented in hardware. Conversion and
The relationship between the data transfer operation of the input signal and the output signal of the hardware can be easily grasped and confirmed, and the more appropriate cycle timing of the input signal and the output signal of the hardware and the conversion to hardware can be realized.

(Fifth Modification) In the fourth modification, when the constraint designation shown in FIG. 19 is given, the constraint designation may be analyzed and a state transition diagram as shown in FIG. 24 may be displayed. . In FIG. 24, an arrow indicating a transition relationship between the respective states (S0 to S6) and a transition condition (req_in) are displayed.

According to such a modification, by displaying the state transition operation of the given constraint as a state transition diagram, the state transition relationship of the constraint operation can be easily grasped, and the appropriate constraint operation can be performed. , And appropriate hardware input signal and output signal cycle timing and hardware conversion in consideration of the restricted operation.

[0082]

According to the high-level synthesis system of the present invention, in the current high-level synthesis, the operation description which is the input of the high-level synthesis is not changed (as is, the algorithm operation description of the software) and is output. By giving the minimum necessary constraint information as a constraint without changing the register transfer level description and the like, it is possible to generate hardware with improved circuit parallel operability.

Further, according to the present invention, the given constraint is analyzed and graphically displayed, so that the constraint can be easily corrected while visually confirming the constraint.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a schematic configuration of a high-level synthesis system according to an embodiment.

FIG. 2 is an explanatory diagram showing an operation description example according to the embodiment;

FIG. 3 is an explanatory diagram illustrating an example of a constraint specification according to the embodiment;

FIG. 4 is a data flow graph according to the embodiment, which is displayed based on the operation description example and the constraint specification example shown in FIGS. 2 and 3.

5 is a logic circuit diagram according to the present embodiment, which is synthesized based on the data flow graph shown in FIG.

FIG. 6 is an explanatory diagram showing an example of a constraint specification corrected in this embodiment.

FIG. 7 is an explanatory diagram showing a constraint specification example according to the embodiment, and is an explanatory diagram showing a constraint specification example in which different timings are corrected as constraints.

FIG. 8 is an explanatory diagram showing a constraint designation example according to the embodiment, and is an explanatory diagram showing a constraint designation example in which different timings are modified as constraints.

9 is a logic circuit diagram of a logic circuit synthesized based on the modified constraint designation shown in FIG. 6 in the present embodiment.

FIG. 10 is a data flow graph displayed based on the constraint designation shown in FIG. 6 in the present embodiment.

FIG. 11 is a data flow graph displayed in the first modification.

FIG. 12 is a data flow graph displayed in Modification Example 2.

FIG. 13 is an explanatory diagram illustrating an example of a constraint specification according to a third modification.

FIG. 14 is a data flow graph before modification displayed in Modification Example 3.

FIG. 15 is a data flow graph after correction displayed in Modification Example 3.

FIG. 16 is a data flow graph diagram in which display options are changed and displayed in Modification Example 3.

FIG. 17 is an explanatory diagram illustrating a constraint specification example according to a third modification.

FIG. 18 is a logic circuit diagram of a logic circuit synthesized in Modification Example 3.

FIG. 19 is an explanatory diagram illustrating an example of constraint specification according to Modification Example 4.

FIG. 20 is a data flow graph displayed in Modification Example 4.

FIG. 21 is a data flow graph displayed in Modification Example 4.

FIG. 22 is an explanatory diagram showing a relationship between an input signal and an output signal in a fourth modification.

FIG. 23 is a logic circuit diagram of a logic circuit synthesized in Modification Example 4.

FIG. 24 is a state transition diagram when the constraint designation of FIG. 19 is given in the fifth modification.

[Explanation of symbols]

101: operation description 102: constraint specification 103: C / D
FG generation unit (operation description analysis unit) 104: constraint analysis unit
105: scheduling unit (synthesizing unit) 106: hardware location unit (synthesizing unit) 107: RTL description generating unit (synthesizing unit) 108: display / editing unit (display unit,
Editing unit) 109 Display unit (display unit) 110
... input device 111 ... RTL description

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Seiichi Nishio 1st address, Komukai Toshiba-cho, Saiwai-ku, Kawasaki-shi, Kanagawa Prefecture Inside the Toshiba Microelectronics Center Co., Ltd. No. 1 Toshiba-cho F-term in Toshiba Microelectronics Center Co., Ltd. (reference) 5B046 AA08 BA02 DA06 GA01 HA05 HA09

Claims (9)

[Claims] 1. A high-level synthesis system used for designing a logic circuit, comprising: an operation description analysis unit for analyzing an operation description describing an operation of a logic circuit to be designed; and an operation for an input signal and an output signal of the logic circuit. A constraint analysis unit for analyzing the constraint, a display unit for displaying the constraint analysis result, an editing unit for correcting the constraint analysis result, an analysis result by the operation description analysis unit, and an analysis by the constraint analysis unit A high-level synthesis system comprising: a high-level synthesis unit that performs high-level synthesis based on the result or the editing result in the editing unit. 2. The editing unit according to claim 1, wherein the editing unit includes an interface unit that corrects an analysis result of the constraint by an operation on a screen displayed by a display unit.
2. The high-level synthesis system according to 1. 3. The display unit displays, in each cycle operation, a variable in an operation description that is a restriction on an operation related to an input signal and an output signal to the logic circuit, and an input signal and an output signal of the logic circuit. 3. The high-level synthesis system according to claim 1, having a function. 4. The display unit has a function of displaying, on a data flow diagram, a correspondence between a scheduling, a variable in an operation description, and an input signal and an output signal of hardware. 4. The high-level synthesis system according to any one of 1 to 3. 5. The high-level synthesis system according to claim 4, wherein the display unit has a function of displaying the input and output signals of the logic circuit in association with each other on a data flow diagram. 6. The display unit according to claim 1, wherein the display unit has a function of distinguishing, on a data flow diagram, a correspondence between an input signal and an output signal value of the logic circuit and whether the input signal and the output signal value are updated or not. Item 6. The high-level synthesis system according to item 4 or 5. 7. The display unit according to claim 4, wherein the display unit has a function of displaying, on a data flow diagram, a correspondence between a variable in an operation description and a data transfer input signal and an output signal operation of hardware. 7. The high-level synthesis system according to any one of items 1 to 6. 8. The display unit has a function of displaying an analysis result by the constraint analyzing unit as a state transition diagram, and the editing unit corrects the constraint by modifying the state transition diagram displayed on a display screen. 8. The high-level synthesis system according to claim 1, wherein the system has a function of correcting the analysis result. 9. A high-level synthesis method used for designing a logic circuit, comprising: analyzing an operation description describing an operation of a logic circuit to be designed; analyzing an operation constraint on an input signal and an output signal of the logic circuit; Displaying the analysis result of the constraint, correcting the analysis result of the constraint based on the display, and performing high-level synthesis based on the analysis result of the operation description and the analysis result of the constraint or the result of the correction. A high-level synthesis method characterized by performing.