JP2952146B2 - Driving method of display device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the driving of a matrix type display device in which, for example, a liquid crystal is used as a display medium and a scanning line driving element and a signal line driving element are connected to or built around a display area on a substrate. In particular, a COG in which these driving elements are directly mounted on a pattern of a substrate
The present invention relates to a method for driving a matrix display device suitable for a (Chip On Glass) display device.

[0002]

2. Description of the Related Art FIG. 9 is a circuit diagram showing a simplified structure of a conventional matrix type display device. A plurality of gate lines 7 serving as scanning lines and a plurality of source lines 8 serving as signal lines are formed orthogonally to each other on a transparent insulating substrate 2 made of glass or the like constituting the display device 1.

Pixels 3 are provided in the form of a matrix near each intersection between the gate line 7 and the source line 8, and each pixel 3 has a thin film transistor (hereinafter abbreviated as "TFT") functioning as a switching element. 4) is formed. Each gate line 7 has one horizontal TFT.
Four gate electrodes are connected to the source line 8 and source electrodes of the TFT 4 for one vertical line are connected to the source line 8, respectively.

Further, at one end of the transparent insulating substrate 2 in the lateral direction of the outer periphery of the display element 1, a gate line driving element for driving the scanning line, that is, a gate driving circuit 5, is disposed. 7 are connected to each other. The display element 1 on the transparent insulating substrate 2
A source line driving element for driving the signal line, that is, a source drive circuit 6 is arranged at one end in the outer peripheral vertical direction, and one end of each source line 8 is connected to the element.

The gate drive circuit 5 is supplied with a gate driver drive signal from the control circuit 14, and receives an ON power supply, an OFF power supply,
A logic power supply is provided. In the source drive circuit 6,
A source driver drive signal is supplied from the control circuit 14, and a + power source,
Power is provided;

FIG. 10 is a timing chart of each signal in the display device. The gate driving circuit 5 applies a scanning signal having a waveform indicated by reference numeral 11 to sequentially turn on the TFTs to the gate line 7, while the source driving circuit 6 applies the scanning signal of the gate line 7 which is currently conducting. By applying one video data signal 10 via the source line 8, data is sequentially written to the picture elements 3.

Thereafter, a signal for turning off the TFT 4 of the gate line 7 is applied from the gate drive circuit 5 until the next scanning, and the data written in the picture element 3 is held. The display operation of the matrix display device is performed by repeating this operation.

[0008]

However, the above-mentioned matrix display device has the following problems.
Since the plurality of gate lines 7 and the plurality of source lines 8 are orthogonal to each other, the scanning signal applied to the gate lines 7 and the video data signal 10 applied to the source lines 8
May interfere with or affect each other as coupling noise, and in some cases, may even affect the driving elements.

Here, in the liquid crystal display device, the video data signal 10 applied to the source line 8 usually has a maximum amplitude of 6 to 10 Vp-p and a frequency of several to prevent deterioration of the liquid crystal, increase contrast and reduce flicker. In many cases, AC driving is performed at a frequency of KHz to several tens of KHz with the polarity inverted for each horizontal line. With respect to the scanning signal 11 applied to the gate line 7, as disclosed in, for example, Japanese Patent Publication No. 2-7444, the TFT 4 is turned on for a certain period in accordance with the number of gate lines, and during other periods,
That is, a DC (direct current) signal of a voltage level that brings the TFT 4 into a non-conductive state until the next scanning is generally used.

Further, the scanning signal 11 is obtained by calculating the T
Since it is necessary to make the FT 4 sufficiently conductive / non-conductive, the difference between the conductive voltage and the non-conductive voltage is set to about 15 to 30 V within the breakdown voltage range of the gate drive circuit 5.

In such a liquid crystal display device, a problem in the mutual influence of the scanning signal 11 and the video data signal 10 is that the video data signal 10 is maintained in a non-conductive state until the next scanning. Reference numeral 10 denotes an instantaneous voltage drop 12 and an instantaneous voltage rise 13 received by the scanning signal 11 at the timing of switching from “H” (= high level) to “L” (= low level). Becomes

Due to the instantaneous voltage rise 13 during the period in which the TFT 4 is maintained in the non-conductive state, the non-conductive voltage level of the TFT 4 of each picture element 3 is increased, the margin for the TFT characteristics is reduced, and there is a problem in display quality and reliability. Occurs.

The instantaneous voltage drop 12 received by the scanning signal 11 at the timing when the video data signal 10 falls from "H" to "L" is transmitted to the gate drive circuit 5 through the gate line 7, so that the gate drive circuit 5 can cause device destruction due to over withstand voltage.

In particular, a COG in which the gate drive circuit 5 and the source drive circuit 6 are directly mounted on the transparent insulating substrate 2 in order to realize fine pitch connection, low cost and high reliability connection.
In the display device of the system, the resistance obtained by adding the connection resistance and the pattern wiring resistance of the transparent insulating substrate 2 to the input terminal line 9 of the gate drive circuit 5 is added, and the instantaneous voltage drop 12 and instantaneous voltage rise 13 Larger 2-6V
And even more serious problems.

As a countermeasure against the breakdown voltage of the gate drive circuit 5, the non-conduction voltage level and the conduction voltage level of the instantaneous voltage drop 12 may be changed. However, the scanning signal 11 applied to the gate line 7 is limited to each picture element. It is necessary to make the TFT 4 of the third TFT sufficiently conductive / non-conductive, and as described above, the reduction of the non-conductive margin of the TFT 4 due to the instantaneous voltage rise 13 is emphasized, so that the potential difference is reduced. This is difficult in terms of display quality and reliability, and cannot be a solution to the problem.

For these reasons, there is a limit in improving the display quality and reliability in the conventional matrix display device, and this is a serious problem particularly in the COG connection type matrix display device. .

An object of the present invention is to provide a method for driving a driving circuit based on an instantaneous voltage drop received by a scanning signal at a timing when the polarity of a video data signal is switched from "H" to "L", regardless of the mounting method of the driving circuit. A display is performed by suppressing and preventing adverse effects and suppressing a decrease in a non-conduction margin of a switching element due to an instantaneous voltage rise applied to a scanning signal at a timing when the polarity of a video data signal rises from “L” to “H”. An object of the present invention is to provide a method for driving a matrix display device, which can significantly improve quality and reliability.

[0018]

According to the present invention, a plurality of scanning lines and a plurality of signal lines are formed on a substrate so as to intersect with each other, and a switching element is provided at each of the picture elements provided near each intersection. In the driving method of the formed matrix type display device, a scanning signal for turning on a switching element is applied to a plurality of scanning lines in a line-sequential manner, and the polarity is changed for each horizontal line in synchronization with the application timing of the scanning signal. The video data signal to be switched is applied to the signal line, the switching element is turned on, the video data is written, and then the switching element is applied to the signal line during the period in which the switching element is kept off until the next scan. The phase is opposite to the timing at which the polarity of the video data signal switches every horizontal line, the timing of polarity switching is earlier, and the switching element is maintained in a sufficiently non-conductive state. A rectangular wave having an effective value, a method of driving a display device characterized in that it applied to the scanning lines.

[0019]

According to the present invention, during the period in which the switching element is kept in the non-conductive state, the signal applied to the scanning line is a rectangular wave whose phase is inverted with respect to the video data signal and whose polarity switching timing is earlier. So, for example,
When the polarity of the video data signal switches from “H” to “L”, the scanning signal has already been switched to the “H” level. At this time, the minimum voltage level due to the instantaneous voltage drop received by the scanning signal becomes shallow at least about 波 of the amplitude of the rectangular wave.

When the polarity of the video data signal switches from "L" to "H", the scanning signal has already been switched to the "L" level. At this time, the maximum voltage level due to the instantaneous voltage rise received by the scanning signal is at least about の of the amplitude of the rectangular wave.

Further, since it is not necessary to consider the instantaneous voltage drop as the minimum voltage level of the scanning signal, the conduction / non-conduction voltage difference of the switching element may be increased as necessary within the breakdown voltage range of the drive circuit. it can.

[0022]

FIG. 1 is a circuit diagram showing a simplified structure around a display element 21 in a matrix type display device driven by the driving method of the present invention. The display device,
A so-called active matrix type display element 21 in which a plurality of picture elements 23 are arranged in a matrix, a gate drive circuit 2
5, including a source drive circuit 26, a control circuit 39, and a plurality of power supply circuits 38 and 40. A plurality of gate lines 27 serving as scanning lines and a plurality of source lines 28 serving as signal lines are formed orthogonal to each other on a transparent insulating substrate 22 made of glass or the like constituting the display element 21.

Pixels 23 are provided in a matrix in the vicinity of each intersection between the gate line 27 and the source line 28. Each pixel 23 has a thin film transistor (hereinafter abbreviated as “TFT”) 24 as a switching element. Are formed. Each gate line 27 has one horizontal line T
The gate electrode of the FT 24 has one vertical line on each source line 28.
The source electrodes of the TFTs 24 for the lines are connected respectively.

Further, a gate driving circuit 25 for driving the scanning lines is disposed at one end of the transparent insulating substrate 22 in the horizontal direction, and one end of each gate line 27 is connected. A source drive circuit 26 for driving a signal line is disposed at one end of the transparent insulating substrate 22 in the vertical direction, and one end of each source line 28 is connected to the source drive circuit 26. The gate drive circuit 25 and the source drive circuit 26 are specifically connected on the wiring pattern of the transparent insulating substrate 22 by COG connection.

FIG. 2 is a block diagram showing a configuration example of the gate drive circuit 25. The gate driving circuit 25 outputs the gate-on signal while sequentially shifting the gate-on signal by the shift register 35, and outputs the gate-on signal to the level shifter 36.
After that, the signal is output to each gate line 27 via the output buffer 37.

The gate drive circuit 25 receives a conduction power supply voltage, a non-conduction power supply voltage, a logic power supply voltage from a gate drive power supply circuit 38, and a gate drive circuit drive signal from a control circuit 39. Is done. The conductive power supply voltage and the non-conductive power supply voltage are selectively applied to the gate line 27 by the output buffer 37,
The display element 21 is driven. The power supply voltage for logic is used as a power supply voltage for driving a logic circuit.

FIG. 3 is a block diagram showing a configuration example of the source drive circuit 26. The source drive circuit 26 sequentially stores the video data signals supplied from a video data signal source (not shown) in the sample and hold circuit 42 by the sampling signal output from the shift register 41, and stores the stored video data signals at one time. Output buffer 4
After the transfer to No. 3, the TFT 24 is turned on by the gate signal to output to each source line 28.

The source drive circuit 26 is supplied with a source drive circuit drive signal from the control circuit 39 and a positive power supply voltage and a negative power supply voltage from the source drive power supply circuit 40. The positive power supply voltage and the negative power supply voltage are selectively applied to the source line 28 by the output buffer 43 to drive the display element 21.

FIG. 4 is a block diagram showing a configuration example of the control circuit 39. The control circuit 39 controls the NT
A source driver drive signal, based on a composite synchronization signal conforming to the SC (National Television System Committee) system or the PAL (Phase Alternation by Line) system,
A gate driver drive signal and a polarity inversion signal FRPV are created and output. The composite synchronization signal is provided to a phase comparison circuit 45 and a vertical synchronization signal separation circuit 46. The phase comparison circuit 45 compares the phase of the output of the horizontal counter 49 with the phase of the composite synchronization signal. The output of the phase comparison circuit 45 is provided to a low-pass filter (LPF) 47. The output of the LPF 47 is provided to a VCO (Voltage-Controlled Oscillator) 48.

The clock signal from VCO 48 is applied to horizontal counter 49. The horizontal counter 49 has a VCO
The clock signal from 48 is counted, the count value is output to the gate circuit 50, and a pulse is output each time the count value reaches a predetermined count value. The pulse from the horizontal counter 49 is provided to the phase comparison circuit 45, the vertical counter 51, and the flip-flop (FF) 52. The gate circuit 50 generates a source driver drive signal based on each output (count value) of the horizontal counter 49 and the vertical counter 51.

The vertical synchronizing signal separating circuit 46 separates the vertical synchronizing signal from the composite synchronizing signal and supplies the same to the vertical counter 51. The vertical counter 51 counts output pulses from the horizontal counter 49 and is reset by an output (vertical synchronization signal) from the vertical synchronization signal separation circuit 46. The output of the vertical counter 51 is supplied to the gate circuit 50 and the gate circuit 53.
Given to. The gate circuit 53 generates a gate driver driving signal and a polarity inversion signal FRPV based on each output from the vertical counter 51 and the flip-flop 52.

FIG. 5 is a block diagram showing a configuration example of the power supply circuit 38 for gate drive. Gate drive power supply circuit 38
Generates a power supply for non-conduction based on the polarity inversion signal FRPV, and also generates a power supply for conduction and a power supply for logic. Since the power supply for conduction and the power supply for logic are both DC constant voltages, the description of the circuit configuration for making them is omitted.

The polarity inversion signal FRPV is applied to the delay circuit 55. The delay circuit 55 delays the polarity inversion signal FRPV by a predetermined period, generates an inversion signal FRPT, and provides the inverted signal FRPT to the booster circuit 56. The booster circuit 56 adjusts the inverted signal FRPT to a predetermined potential and outputs it as a non-conduction power supply.

FIG. 6 is a circuit diagram showing a configuration example of the delay circuit 55. The delay circuit 55 includes an inverter 60, a resistor 6
1, a capacitor 62 and a buffer 63. The polarity inversion signal FRPV is inverted by the inverter 60, delayed by a time constant determined by the resistor 61 and the capacitor 62, inverted and input to the buffer 63, and output as the inverted signal FRPT.

FIG. 7 is a circuit diagram showing a configuration example of the booster circuit 56. The inverted signal FRPT is input to the negative terminal of the comparator 66 via the resistor 65. The low voltage obtained by the resistance division of the variable resistor 67 is input to the + terminal of the comparator 66. A voltage + V is applied to one end of the variable resistor 67, and a voltage -V is applied to the other end. Comparator 66
Is output to transistors 69 and 70 via a resistor 68.
Given to each base. The emitter of the transistor 69 and the emitter of the transistor 70 are connected.
The voltage + V is applied to the collector of the transistor 60. The voltage −V is applied to the collector of the transistor 70. The collector of the transistor 69 and the
The terminal is connected via a resistor 71. An electrolytic capacitor 72 is connected in series between a connection point 77 of each emitter of the transistors 69 and 70 and an output terminal 78. A capacitor 75 is connected between the connection point 77 and the electrolytic capacitor 72 via resistors 73 and 74. The anode of the Zener diode 76 is connected between the electrolytic capacitor 72 and the output terminal 78. The voltage −V is supplied to the cathode of the Zener diode 76.

FIG. 8 is a timing chart of each signal in the driving method of the present invention. The gate drive circuit 25
A scanning signal having a waveform indicated by reference numeral 31 for turning on the TFT 24 is sequentially applied to the gate line 27, while the source drive circuit 26 supplies the video data for one gate line 27 which is currently on. By applying the signal 30 via the source line 28, data is sequentially written to the picture element 23. Thereafter, a signal for turning off the TFT 24 of the gate line 27 is applied from the gate drive circuit 25 until the next scanning, so that the pixel 2
3 written data is retained. By repeating this operation, the display operation of the matrix type display device is performed.

Here, after the TFT 24 is turned on and video data is written, the polarity of the video data signal 30 applied to the signal line is maintained during the period in which the TFT 24 is kept off until the next scanning. A rectangular wave whose phase is opposite to the timing of switching of “H” and whose switching timing of “H” and “L” is earlier is applied to the scanning line.

Further, the rectangular wave has an effective value for keeping the TFT 24 sufficiently non-conductive, and its amplitude is at least at the timing when the video data signal 30 switches from "H" to "L". , And the video data signal 30 is changed from "L" to "H".
Is set to be larger than the instantaneous voltage rise 33 received by the scanning signal 31 at the rising timing.

As described above, in the present embodiment, when the video data signal 30 switches from "H" to "L", the scanning signal 31 has already been switched to the "H" level. At this time, the instantaneous voltage drop 3
2 is smaller than the conventional minimum voltage level by at least about 少 な く と も of the amplitude of the rectangular wave, thereby preventing the gate drive circuit 25 from being damaged due to exceeding the withstand voltage.

The video data signal changes from "L" to "H".
, The scanning signal has already been switched to the “L” level. At this time, the maximum voltage level due to the instantaneous voltage rise 33 received by the scanning signal is at least about の of the amplitude of the rectangular wave, and T
It is possible to prevent the non-conduction margin of the FT from decreasing.

Further, the gate drive circuit 25 has an effective value for keeping the TFT 24 sufficiently non-conductive, and it is not necessary to consider the instantaneous voltage drop 32 as the minimum voltage level of the scanning signal 31. The conduction / non-conduction voltage difference between the TFTs 24 can be increased as necessary within the breakdown voltage range described above, and a large margin can be provided for display quality and TFT 24 characteristics.

Further, in the COG connection matrix display device in which the connection resistance and the pattern wiring resistance of the transparent insulating substrate 22 are added to the input terminal line 29 of the gate drive circuit 25 and the instantaneous voltage drop 32 is enlarged. The operation of the gate drive circuit 25 and the resistance specification for the display quality can be afforded, and the advantages of the COG connection system, that is, the fine pitch, low cost, and high reliability connection can be enjoyed.

In the above embodiment, the case where the present invention is applied to the driving method of the COG connection type matrix display device has been described. However, the TAB (Tape Automated Bonding) type driving circuit is mounted by COF (Chip On Film). The present invention can be applied to a case or a case where a driving element is formed on an insulating transparent substrate.

As the TFT used in the present invention, an insulated gate field effect transistor using amorphous silicon, polysilicon, Te or the like as a semiconductor material is generally used.

[0045]

As described above, according to the present invention, during the period in which the switching element is maintained in the non-conductive state, the scanning signal applied to the scanning line inverts the phase of the video data signal and switches the polarity. Is a rectangular wave whose timing is earlier, for example, when the polarity of the video data signal switches from “H” to “L”, the scanning signal has already been switched to the “H” level. Thus, the minimum voltage level due to the instantaneous voltage drop received by the scanning signal is:
At least about half of the amplitude of the rectangular wave becomes shallower, and it is possible to prevent element damage due to excess withstand voltage of the drive circuit.

For example, when the polarity of the video data signal changes from "L" to "H", the scanning signal has already been changed to the "L" level. At this time, the maximum voltage level due to the instantaneous voltage rise received by the scanning signal is at least about の of the amplitude of the rectangular wave, and the non-conduction margin of the switching element can be prevented from decreasing.

Further, since it is not necessary to consider the instantaneous voltage drop as the minimum voltage level of the scanning signal, the conduction / non-conduction voltage difference between the switching elements can be increased as necessary within the withstand voltage range of the drive circuit. As a result, a large margin can be provided for the display quality and the characteristics of the switching element.

[Brief description of the drawings]

FIG. 1 is a simplified circuit diagram showing a configuration example of a matrix type display device driven by a driving method of the present invention.

FIG. 2 is a block diagram illustrating a configuration example of a gate drive circuit 25.

FIG. 3 is a block diagram illustrating a configuration example of a source drive circuit 26;

FIG. 4 is a block diagram illustrating a configuration example of a control circuit 39.

FIG. 5 is a block diagram showing a configuration example of a gate drive power supply circuit 38;

6 is a circuit diagram showing a configuration example of a delay circuit 55 shown in FIG.

FIG. 7 is a circuit diagram showing a configuration example of a booster circuit 56 shown in FIG.

FIG. 8 is a timing chart of each signal in the driving method of the present invention.

FIG. 9 is a simplified circuit diagram showing a configuration of a conventional matrix type display device.

FIG. 10 is a timing chart of each signal in the display device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 21 Display element 22 Transparent insulating substrate 23 Picture element 24 Thin film transistor 25 Gate drive circuit 26 Source drive circuit 27 Gate line 28 Source line 30 Video data signal 31 Scan signal 32 Instantaneous voltage drop 33 Instantaneous voltage rise

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. ⁶ , DB name) G02F 1/133 550

Claims (1)

(57) [Claims] 1. A matrix display device in which a plurality of scanning lines and a plurality of signal lines are formed on a substrate so as to intersect, and a switching element is formed in each of picture elements provided near each intersection. In the driving method of (1), a scanning signal for turning on a switching element in a line-sequential manner is applied to a plurality of scanning lines, and a video data signal whose polarity is switched for each horizontal line in synchronization with the application timing of the scanning signal is applied to a signal line. After the switching element is turned on and video data is written, the video data signal applied to the signal line is applied to each horizontal line during a period in which the switching element is kept in a non-conductive state until the next scanning. The timing at which the polarity switches to
A method of driving a display device, characterized in that a rectangular wave having a reverse phase, a fast polarity switching timing, and an effective value for keeping a switching element sufficiently non-conductive is applied to a scanning line.