JP2947847B2 - Semiconductor storage device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and particularly useful for a dynamic RAM (random access memory) having a relatively large storage capacity. It is about technology.

[Conventional technology]

As the capacity of dynamic RAM and the like has been increasing, MPR (Multi Purpose
Register: Multi-purpose register) and data matching circuit (Comp
arator) and matching (Match) line extraction MOSFETs (insulated gate field effect transistors) are provided corresponding to the data lines, and the normality of the memory cells is determined in word line units depending on whether or not the verification line is pulled out to a low level. A line mode test method has been proposed.

For the line mode test method, see, for example, “ISSCC:
International Solid-State Circuits Conferense Digest of Technical Papers (Digest O
f Technical Papers) SESSION XVI, pp. 244-245
Page.

[Problems to be solved by the invention]

The inventors of the present application have clarified that the conventional line test mode system described above has the following two problems. That is, (1) In the line test mode method, as described above, the MPR corresponding to the unit amplifier circuit of the sense amplifier, the data matching circuit, and the matching line extracting MOSFET are provided corresponding to each data line, and the extracting MOSFET is It is designed to have a relatively large size in order to quickly extract charges stored in a relatively large capacity of the verification line. As a result, the layout area of the dynamic RAM increases, the chip size increases, and cost reduction is hindered.

(2) The method of performing a function test of a memory cell in units of word lines as in the line test mode is effective when the number of memory cells coupled to each word line is large.
If the number of memory cells coupled to each data line is large and the absolute number of word lines is large, the number of tests increases, which is relatively disadvantageous.

An object of the present invention is to provide a semiconductor memory device such as a dynamic RAM capable of performing a function test of a memory cell in a data line direction. Another object of the present invention is to improve the efficiency of a functional test of a dynamic RAM or the like having a relatively large column address space while suppressing an increase in required layout area, and to reduce the cost.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means for solving the problem]

The outline of a typical invention disclosed in the present application will be briefly described as follows. That is,
A reference bit, a data collation circuit, and a check bit are provided for each data line, and a function test of the memory cell is performed. (A) The check bit is reset, and test data is written to all reference bits.

(B) This test data is transferred to the memory cell under test in word line units.

(C) The test data transferred to the memory cell under test is read out in word line units, and is compared and collated with the original test data held in the reference bits by the corresponding data collation circuit.

(D) The corresponding check bit is selectively rewritten according to the result of the comparison by the data comparison circuit.

(E) After repeating the above items (b) to (d) for all the word lines, by reading the check bit,
Determine the normality of all memory cells coupled to the corresponding data line.

The procedure is as follows. At this time, the reference bit and the check bit are constituted by dynamic memory cells, and the data holding means for holding the original test data during the period of the comparison / matching operation is, for example, the data of the memory array on the opposite side in the shared sense form. Implemented using lines.

(Operation)

According to the above-described means, it is possible to realize a dynamic RAM or the like that can perform the function tests of the memory cells in the data line direction while suppressing an increase in the layout required area. This makes it possible to increase the efficiency of a functional test of a dynamic RAM or the like having a relatively large column address space and promote cost reduction.

〔Example〕

FIG. 2 shows a dynamic RA to which the present invention is applied.
A block diagram of one embodiment of M is shown. Also, the first
FIG. 2 is a circuit diagram showing one embodiment of the memory array of the dynamic RAM of FIG. 2 and its peripheral circuits. An outline of the configuration and operation of the dynamic RAM according to this embodiment will be described with reference to these drawings. The circuit elements shown in FIG. 1 and the circuit elements constituting each block shown in FIG. 2 are not particularly limited by a known semiconductor integrated circuit manufacturing technique, but may be formed on a single semiconductor substrate such as single crystal silicon. Formed. In FIG. 1, the MOSFET with an arrow on its channel (back gate) portion is a P-channel type and an N-channel MOSFET without an arrow.
Are shown separately from

Although not particularly limited, the dynamic RAM of this embodiment has a relatively large storage capacity. For this reason, the dynamic RAM is provided with a dedicated test mode for performing functional tests of the memory cells in the data line direction in order to efficiently perform product tests. In this example,
Although dynamic RAM is not particularly limited, WCBR (▲
The test mode is started by executing the ▼ ・ ▲ ▼ before ▲ ▼) cycle, and the CBR (▲
The test mode is released by executing the (before ▲) or ROR (▲ ▼ only refresh) cycle.

In FIG. 2, the dynamic RAM employs, although not particularly limited to, a shared sense amplifier system, and a pair of memory arrays ARYL arranged so as to occupy most of the semiconductor substrate surface.
And ARYR, and a pair of data matching circuits DCL and DCR and a sense amplifier SA arranged between these memory arrays.

Although not particularly limited, as shown in FIG. 1, the memory array ARYL includes m word lines WL1 to WLm arranged in parallel in a vertical direction and n word lines arranged in parallel in a horizontal direction.
A set of complementary data lines D L1 to D Ln (here, for example, the non-inverted data line DL 1 and the inverted data line ▼ are collectively represented as a complementary data line D L1. Hereinafter, the same applies to the complementary signal and the complementary signal line) And At the intersections of these word lines and complementary data lines, m × n dynamic memory cells composed of an information storage capacitor Cs and an address selection MOSFET Qm are arranged in a grid. Memory array AR
The drains of the address selection MOSFETs Qm of the m memory cells arranged at the same column address of YL are alternately coupled to the non-inverted or inverted data lines of the corresponding complementary data lines D L1 to D Ln with a predetermined regularity. Is done. The gates of the address selection MOSFETs Qm of the n memory cells arranged at the same row address are commonly coupled to corresponding word lines WL1 to WLm, respectively. Although not particularly limited, a predetermined plate voltage VPL is commonly supplied to the other electrode of the information storage capacitor Cs of each memory cell.

Similarly, the memory array ARYR is not particularly limited,
M word lines WR1 to WRm and n arranged orthogonally
A set includes complementary data lines D R1 to D Rn and m × n dynamic memory cells arranged in a grid at intersections of these word lines and complementary data lines. Drain of the m MOSFETQm address selection of the memory cells arranged in the same column address of the memory array ARYR is alternately with a predetermined regularity to the non-inverted or inverted data lines of the corresponding complementary data D R1 to D Rn Be combined. Also, an address selection MOSF for n memory cells arranged at the same row address
The gates of ETQm are commonly coupled to corresponding word lines WL1 to WLm, respectively.

The word lines WL1 to WLm and WR1 to WRm of the memory arrays ARYL and ARYR are coupled to a common row address decoder RAD, but are not limited thereto, and are selectively selected. On the other hand, the complementary data lines D L1 to D Ln of the memory array ARYL
Although not particularly limited, is coupled to a corresponding unit circuit of the data collation circuit DCL, and further coupled to a corresponding unit circuit of the sense amplifier SA. Similarly, the complementary data lines D R1 to D Rn of the memory array ARYR are coupled to corresponding unit circuits of the data comparison circuit DCR, and further coupled to corresponding unit circuits of the sense amplifier SA.

Data matching circuit DCL includes n unit circuits provided corresponding to the complementary data lines D R1 to D Ln memory array ARYL. These unit circuits are not particularly limited, but as shown in FIG. 1, four N-channel MOSFETs Q1
Exclusive OR circuit EO consisting of 3-Q16 and a pair of shared
And MOSFETs Q17 and Q18, respectively.

Of these, the gates of the shared MOSFETs Q17 and Q18
Although not particularly limited, the timing signal φsl is commonly supplied. The timing signal φsl is selectively set to a high level when the left memory array IARY is accessed, whereby the complementary data line D L1
To D Ln are selectively coupled to corresponding unit circuits of the sense amplifier SA.

On the other hand, MOSFETs Q13 and Q14 that constitute the exclusive logic circuit EO
Are the corresponding complementary data lines of the memory array ARYL
D L1 to D Ln are coupled to the inverted or non-inverted data lines, and the commonly coupled sources are coupled to the collation control line CLN as the output node n1 of the exclusive OR circuit EO.
Coupled to the circuit ground potential via channel MOSFET Q34. The drains of the MOSFETs Q15 and Q16 are coupled to the non-inverting input / output nodes D1 to Dn or the inverting input / output nodes ▲ ▼ to ▲ ▼ of the corresponding unit circuit of the sense amplifier SA outside the corresponding shared MOSFETs Q17 and Q18, The common coupled gate is coupled to the collation control line CLP and then coupled to the circuit power supply voltage via the P-channel MOSFET Q3.

Although not particularly limited, a timing signal φdcl is commonly supplied to the gates of the MOSFETs Q3 and Q34. Here, although not particularly limited, the timing signal φdcl is normally set to the high level, and temporarily set to the low level at a predetermined timing when the dynamic RAM is set to the test mode. When timing signal φdcl is at a high level, MOSFET Q3 is turned off and MOSFET Q34 is turned on. Therefore, MOSFETs Q15 and Q16 are both turned off, and output node n1 of exclusive logic circuit EO is forced to low level. When the timing signal φdcl is set to the low level, both the MOSFETs Q15 and Q16 are turned on, and the forced ground of the output node n1 is released. Therefore, the exclusive OR circuit EO is in an operating state, and the data held in the corresponding complementary data lines D L1 to D Ln of the memory array ARYL and the read data amplified by the corresponding unit circuit of the sense amplifier SA are exchanged. It acts as a data matching circuit for comparison and matching.

As will be described later, when the dynamic RAM is in the test mode, the data collation circuit DCL connects the memory array A on the opposite side.
Used for functional testing of memory cells that make up RYR. At this time, the corresponding reference bit is temporarily held in each complementary data line of the memory array ARYL, and the complementary input / output nodes D1 to Dn of each unit circuit of the sense amplifier SA have:
The read data of the selected memory cell of the memory array ARYR, that is, the read data of the memory cell under test is amplified and held. The output node n1 of the exclusive OR circuit EO is kept at low level when these data match, and is selectively set at high level when they do not match.

Each unit circuit of the data collation circuit DCL further includes, but not limited to, a pair of check bit memory cells in a dynamic memory cell form. These memory cells include a check bit capacitor Cc and a check bit selection MOSFET Qc. The drain of each check bit selection MOSFET Qc is coupled to the non-inverted or inverted data line of the corresponding complementary data line D L1 to D Ln of the memory array ARYL, and its gate is connected to the check bit word line WCL1.
Alternatively, they are commonly connected to WCL2. Although not particularly limited, these check bit word lines are coupled to a row address decoder RAD, and when the dynamic RAM is set to the test mode, the complementary internal address signal a x0 of the least significant bit is set.
In the selected state. On the other hand, the check bit selection MOSFET Qc of each check bit capacitor Cc
The electrode coupled to the source of the
It is coupled to the ground potential of the circuit via ETQ11 or Q12, and a predetermined plate voltage VPL is commonly supplied to the other electrode. After the gates of MOSFETs Q11 and Q12 are commonly coupled,
It is coupled to the corresponding output node n1 of the exclusive OR circuit EO.

As described later, the memory cells for check bits include:
At the beginning of the test mode, a logic "1", that is, a high-level check bit is written. Also,
The output node n1 of the exclusive OR circuit EO is, as described above,
When the data read from the memory cell under test of the memory array ARYR does not match the corresponding reference bit, it is selectively set to the high level. At this time, the high level written in the check bit memory cell is pulled out when the corresponding MOSFET Q11 or Q12 is turned on, and is set to logic "0", that is, low level. Each check bit of the data collation circuit DCL can be read through a normal read path of a memory cell constituting the memory array ARYL.

Similarly, data matching circuit DCR includes n unit circuits provided corresponding to the complementary data D R1 to D Rn of the memory array ARYR. These unit circuits have the same circuit configuration as the unit circuit of the data matching circuit DCL, and include a pair of shared MOSFETs Q26 and Q27, an exclusive OR circuit EO including four MOSFETs Q28 to Q31, and a pair of check bits. It includes a memory cell and MOSFETs Q32 and Q33 for extracting the memory cell.

Of these, the shared MOSFETs Q26 and Q27 are selectively turned on when the timing signal φsr is set to the high level, and the exclusive OR circuit EO is selectively activated when the timing φdcr is set to the low level. It is said. The data matching circuit DCR is connected to the memory array ARYL on the opposite side.
Is subjected to a functional test of the memory cell constituting
Each complementary data line of the memory array ARYR temporarily holds a corresponding reference bit. Each check bit is selectively extracted when the data read from the selected memory cell of the memory array IARY, that is, the memory cell under test and the corresponding reference bit do not match, and the check bit is set to logic “0”, that is, low level. Is done.

Next, the sense amplifier SA is not particularly limited,
As shown in the figure, there are provided n unit circuits provided corresponding to the respective complementary data lines of the memory arrays ARYL and ARYR.
These unit circuits include P-channel MOSFETs Q1 and Q2 and an N-channel MOSFET Q1 as illustrated in FIG.
Unit amplifier circuit USA consisting of 9 and Q20 and unit precharge circuit UPC consisting of three N-channel MOSFETs Q21-Q23
Respectively.

Of these, MOS that constitutes each unit precharge circuit UPC
The FETs Q21 to Q23 are not particularly limited, but the dynamic type R
When AM is in the non-selected state and the timing signal φpc is set to the high level, it is selectively turned on. as a result,
Complementary input / output nodes D1 to Dn of the corresponding unit circuit are set to a half precharge level HVC which is set to a half of the power supply voltage of the circuit.

On the other hand, each unit amplifier circuit USA of the sense amplifier SA is selectively supplied with the power supply voltage of the circuit via the common source line SP and the ground potential of the circuit via the common source line SN at the same time. The operation state is set. In this operation state, each unit amplifier USA is output from the selected memory cell of the memory array ARYL via the shared MOSFET Q17 and Q18 or from the selected memory cell of the memory array ARYR via the shared MOSFET Q26 and Q27. The small read signal is amplified to be a high level or low level binary read signal. Each unit amplifier circuit USA of the sense amplifier SA is also used for write and read operations of a check bit provided in the data collation circuits DCL and DCR and a reference bit described later.

Each unit circuit of the sense amplifier SA further includes a column switch including N-channel MOSFETs Q24 and Q25, and a pair of reference bit memory cells including a capacitor Cr and a selection MOSFET Qr.

Of these, MOSFETs Q24 and Q
25 is selectively turned on when the data line selection signals Y1 to Yn supplied from the column address decoder CAD are alternatively set to a high level. Thus, the corresponding unit circuits of the sense amplifier SA are selectively connected to the complementary common data lines C D.

On the other hand, the memory cells for reference bits are the memory cells for check bits and the memory arrays ARYL and
Like the ARYR memory cell, the memory cell is a dynamic memory cell, and the corresponding reference bit word line WQ1 or WQ1.
When Q2 is set to the high level, it is selectively set to the selected state. In this embodiment, the capacitor Cr constituting the reference bit memory cell is not particularly limited,
It is designed to have twice the capacity (information storage capacity) as compared to the information storage capacitor Cs constituting the memory cells of the memory arrays ARYL and ARYR. Although not particularly limited, the reference bit word lines WQ1 and WQ2 are coupled to the row address decoder RAD, and are selectively selected according to the complementary internal address signal a x0 of the least significant bit when the dynamic RAM is in the test mode. It is said.

In FIG. 2, although not particularly limited, the row address decoder RAD is supplied from the row address buffer RAB to the i +
One-bit complementary internal address signals a x0 to a xi are supplied, and a timing signal φx is supplied from a timing generation circuit TG.

The row address decoder RAD outputs the timing signal φ
When x is set to a high level, it is selectively activated. In this operation state, the row address decoder RA
D decodes the complementary internal address signals a x0 to a xi and selectively sets a corresponding word line of the memory array ARYL or ARYR to a high level selection state. When the dynamic RAM is set to the test mode, the row address decoder RAD selectively sets the check bit word line of the data comparison circuit DCL or DCL and the reference bit word line of the sense amplifier SA to a high level selection state. It has both functions. In this embodiment, selection of the memory array ARYL or ARYR and data matching circuit DCL or DCR is not particularly limited, performed according to the complementary internal address signals a xi of the most significant bit, check bit word lines WCL1
Or WCL2, WCR1 or WCR2 and the selection of the reference bit word lines WQ1 or WQ2 is performed according to the least significant bit complementary internal address signals a x0.

The row address buffer RAB captures and holds the row address signal transmitted from the address multiplexer AMX according to the timing signal φar supplied from the timing generation circuit TG. Moreover, these row address signals to form the complementary internal address signals a x0~ a xi Based supplied to the row address decoder RAD.

Although the address multiplexer AMX is not particularly limited, the dynamic RAM is set to the normal operation mode and the low-level timing signal φre
When f is supplied, X address signals AX0 to AXi supplied in a time-division manner via external terminals A0 to Ai are selected and transmitted to the row address buffer RAB as the row address signals. When the dynamic RAM is in the refresh mode and the timing signal φref is set to the high level, the refresh address signals ar0 to ari supplied from the refresh address counter RFC are selected and the row address signal is sent to the row address buffer RAB as the row address signal. introduce.

The refresh address counter RFC performs a stepping operation according to the timing signal φrc supplied from the timing generation circuit TG when the dynamic RAM is set to the CBR refresh mode, although not particularly limited. As a result, the refresh address signals ar0 to ari are formed and supplied to the address multiplexer AMX.

On the other hand, to the column address decoder CAD, although not particularly limited, the (i + 1) -bit complementary internal addresses a y0 to a yi are supplied from the column address buffer CAB, and the timing signal φy is supplied from the timing generation circuit TG.

The column address decoder CAD is selectively activated by setting the timing signal φy to a high level. In this operating state, the column address decoder CAD decodes the complementary internal address signals a y0~ a yi, the corresponding data line selection signal Y1~Yn and alternatively a high level. As described above, these data line selection signals are supplied to the gates of the switch MOSFETs Q24 and Q25 constituting the column switches of the sense amplifier SA.

The column address buffer CAB converts Y address signals AY0 to AYi supplied in a time-division manner through the external terminals A0 to Ai,
Timing signal φ supplied from timing generation circuit TG
Acquire and retain according to ac. Further, based on these Y address signals, complementary internal address signals a y0 to a yi are formed and supplied to the column address decoder CAD.

Complementary common data lines C D is not particularly limited, is coupled to the data input-output circuit I / O.

Although not particularly limited, the data input / output circuit I / O includes a data input buffer and a data output buffer. The input terminal of the data input buffer is coupled to the data input terminal Din, and the output terminal of the input terminal is connected to the complementary common data line Cin.
D. The data input buffer is supplied with the timing signal φw from the timing generation circuit TG.

The data input buffer is selectively activated by setting the dynamic RAM to the write mode and setting the timing signal φw to the high level. In this operation state, the data input buffer is connected to the data input terminal Di.
forming a complementary write signals in accordance with write data supplied via the n, complementary common data line via the C D, the sense amplifier memory cell and the data matching circuit for the reference bit of the SA DCL or DCR check bits or memory Supply to selected memory cells in array ARYL or ARYR. Although not particularly limited, when the timing signal φw is at a low level, the output of the data input buffer is in a high impedance state.

On the other hand, the input terminal of the data output buffer is coupled to a complementary common data lines C D, and an output terminal a data output terminal
Combined with Dout. The data output buffer is supplied with a timing signal φr from the timing generation circuit TG.

The data output buffer is selectively activated when the dynamic RAM is set to the read mode and the timing signal φr is set to the high level. In this operation state, the data output buffer is connected to the data signal circuit DCL.
Alternatively, the complementary common data line C is output from a check bit of DCR or a selected memory cell of the memory array ARYL or ARYR.
The binary read signal output via D is further amplified and sent out via a data output terminal Dout.

The timing generation circuit TG includes row address strobe signals ▲ ▼,
Based on the column address strobe signal ▼ and the write enable signal ▼, the various timing signals described above are formed and supplied to each part of the dynamic RAM.

FIG. 3 is a processing flowchart of one embodiment of the test mode of the dynamic RAM shown in FIG. Also,
FIG. 4 is a state transition diagram of one embodiment of the test mode shown in FIG. The outline of the test mode of the dynamic RAM according to the present embodiment and the features thereof will be described with reference to these drawings. FIGS. 3 and 4 illustrate a case where a functional test is performed on the memory cells constituting the left memory array IARY. In the following description, the information storage capacitor Cs is used as a memory array.
ARYL or ARYR memory cells or their contents are referred to, and check bit capacitors Cc and reference bit capacitors Cr are used to refer to check bits and reference bits or their contents.

In FIG. 3, the test mode of the dynamic RAM is not particularly limited, but includes six steps (STEP) A.
To G separately.

That is, when the dynamic RAM is set to the test mode, the reset processing of the check bit Cc is first performed in step A, although there is no particular limitation. At this time,
Check bit data of logic “1” is supplied to the dynamic RAM via the data input terminal Din. Further, to the address input terminals A0 to Ai, a selection signal for designating the data collation circuit DCR on the opposite side and the check bit word line WCR1 or WCR2 as a row address are sequentially supplied, and a column address of the data collation circuit DCR is supplied as a column address. Y address signals AY0 to AYi for designating a unit circuit are sequentially supplied. Check bit data is stored in the data input / output circuit I /
O from via the complementary common data lines C D and the sense amplifier SA, sequentially written in the check bits Cc data verification circuit DCR, are retained. The write operation is repeated for the number of check bits, that is, n cycles. As a result, as shown in FIG. 4, all the check bits Cc of the data matching circuit DCR are reset to logic "1", that is, high level.

Next, in step B, the reference bit write operation is repeatedly executed for n cycles. At this time, although not particularly limited, test data of logic “1” or “0” is supplied to the dynamic RAM via the data input terminal Din in a predetermined combination. The address input terminals A0 to Ai are sequentially supplied with a selection signal for designating the reference bit word line WQ1 or WQ2 as a row address, and a complementary signal for designating a unit or a path of the sense amplifier SA as a column address. Internal address signal a y0 ~
a yi are supplied sequentially. Test data of a logical "1" or "0", via a complementary common data line C D from the data input-output circuit I / O, are sequentially written to the reference bit Cr of the sense amplifier SA, is maintained.

The test data held in each reference bit Cr of the sense amplifier SA is stored in the memory array ARYL in step C.
Is transferred to the memory cells constituting the memory cells, that is, the memory cells under test (test bits) in word line units. At this time, X address signals AX0 to AXi for designating the words WL1 to WLm of the memory array IARY are sequentially supplied as row addresses to the address input terminals A0 to Ai of the dynamic RAM.

In the dynamic RAM, the corresponding word lines WL1 to WLm of the memory array ARYL are sequentially set to a high-level selection state, and at the same time, the word line for the reference bit of the sense amplifier SA according to the X address signal AX0 of the least significant bit.
WQ1 or WQ2 is selectively set to the high level.
Further, the timing signal φsl is set to the high level in accordance with the X address signal AXi of the most significant bit, and the shared MOSFET Q1
7 and Q18 are turned on.

As described above, the capacitor Cr forming the memory cell for the reference bit is designed to have twice the information storage capacity as the information storage capacitor Cs forming the memory cell of the memory array ARYL. Therefore, the test data held in the corresponding reference bit Cr of the sense amplifier SA is included in the n test bits Cs coupled to the selected word line of the memory array ARYL, as shown in FIG. The data is forcibly and simultaneously transferred in word line units. These transfer operations are repeatedly executed by the number of word lines of the memory array ARYL, that is, m cycles.

On the other hand, the test data held in each reference bit Cr of the sense amplifier SA is supplied to the corresponding complementary data lines D R1 to D R of the memory array ARYR by step D of one cycle.
It is simultaneously transcribed to Rn. At this time, the dynamic RAM
In, the timing signal φsr is set to high level and
MOSFETs Q26 and Q27 are turned on, and unit amplifier circuits USA of sense amplifier SA are simultaneously turned on. For this reason, as shown in FIG. 4, the test data Cr held in each reference bit is a binary signal of a high level or a low level on the corresponding complementary data lines D R1 to D Rn of the memory array ARYR on the opposite side. A read signal is held on these complementary data lines.

The test data written in each memory cell of the memory array ARYL in step C is read out in word line units in step E, and the data collation circuit DCR on the opposite side is read out.
, The corresponding complementary data line D of the memory array ARYR
It is compared with the test data held in R1 to D Rn. At this time, in the dynamic RAM memory array ARYL,
The word lines WL1 to WLm are sequentially set to a high level selection state,
Shared MOSFETs Q17 and Q18 are turned on. Therefore, the minute read signal of the n memory cells coupled to the selected word line of the memory array ARYL is amplified by the corresponding unit amplifier circuit USA of the sense amplifier SA,
At the complementary input / output nodes D1 to Dn , a high-level or low-level binary read signal is output.

On the other hand, in the data matching circuit DCR, the timing signal φdcr
Is at low level, and the exclusive OR circuit EO of each unit circuit is
Is set to the operating state. Therefore, each exclusive OR circuit EO
The output node n1, the sense amplifier SA of the corresponding complementary data lines D complementary output nodes D. 1 to read data established in D n and the memory array ARYR the corresponding unit circuits R1~
It is selectively set to a high level on condition that the original test data Cr held in D Rn does not match. as a result,
As shown in FIG. 4, the corresponding check bit Cc of the data collation circuit DCR is selectively extracted and rewritten to logic "0", that is, low level. not to mention,
If both corresponding data match, the data collation circuit DCR
Is kept at logic "1", that is, high level.

The comparison and collation operation in step E is repeated for m cycles, that is, for the number of word lines of the memory array ARYL. Therefore, the state of each check bit Cc of data matching circuit DCR is becomes to aggregate function test results of all the memory cells coupled to the corresponding complementary data lines D L1 through D Ln memory array ARYL.

Complementary data lines D R1 to D Rn of the memory array ARYR on the opposite side
The original test data Cr held in step (1) is cleared to the initial state, that is, the half precharge level by executing one refresh dummy cycle in step F, although not particularly limited.

The result of the above test mode of dynamic RAM is
In step G, the determination is made by sequentially reading the check bits of the data matching circuit DCR. At this time, a selection signal for designating the check bit word line WCR1 or WCR2 is sequentially supplied to the address input terminal of the dynamic RAM as a row address, and a unit circuit of the data matching circuit DCR is designated as a column address. Y address signals AY0 to AYi are sequentially supplied. Data collation circuit
Check bits Cc sequentially read from the DCR are taken into an external test device via a data output terminal Dout,
The test mode is used to determine the result. as a result,
When the read check bit Cc remains at logic "1", the m memory cells arranged at the corresponding column address of the memory array ARYL are normal and have been rewritten to logic "0". , A predetermined error process is performed. The above determination operation is repeatedly performed for the number of check bits, that is, n cycles.

As described above, the dynamic RAM of this embodiment is
Using a shared sense amplifier system, a pair of memory arrays
A sense amplifier SA is interposed between ARYL and ARYR. The dynamic RAM further has a test mode for performing a function test of the memory cells constituting the memory arrays AYL and ARYR in a data line direction,
Data collation circuits DCL and DCR are provided for this purpose. The sense amplifier SA includes n reference bits provided corresponding to each complementary data line of the memory arrays ARYL and ARYR, and the data matching circuits DCL and DCR provide n number of reference bits provided corresponding to each complementary data line. It includes a check bit and an exclusive OR circuit EO. In this embodiment, the reference bit and the check bit are the memory array IARY and the memory array IARY.
This is a dynamic memory cell similar to the memory cell constituting ARYR. In the test mode, (a) a logic “1” is written to a check bit of the data collation circuit DCR or DCL on the opposite side to reset the same, and a logic “1” or Write test data of “0” in a predetermined combination.

(B) The test data held in the reference beat is transferred to the memory cell under test of the memory array ARYL or ARYR for each word line, and the memory array on the opposite side is transferred.
Transfer to the corresponding complementary data line of ARYR or ARYL.

(C) The test data transferred to the memory cell under test is read out in word line units, and the original data held in the corresponding complementary data line of the memory array ARYR or ARYL on the opposite side by the data matching circuit DCR or DCL. Compare with data.

(D) The corresponding check bit is selectively rewritten to logic "0" according to the result of the comparison by the data comparison circuit DCR or DCL.

(E) After repeating the above operation for all the word lines, by sequentially reading out the check bits of the data matching circuit DCR or DCL, the n memory cells coupled to the corresponding complementary data lines of the memory array ARYL or ARYR Is determined to be normal. The procedure is as follows. As a result, in the dynamic RAM according to the present embodiment, since the reference bits and the check bits are constituted by ordinary dynamic memory cells, the functional test of the memory cells is consolidated in the data line direction while suppressing an increase in the layout required area. And run it. Therefore, the total number of cycles TC required to perform a functional test on all the memory cells of the memory arrays ARYL and ARYR is TC = 2 (2m + 3n + 2) where m is the number of word lines and n is the number of complementary data lines. ). As is well known, a so-called write / read test is performed in a normal dynamic RAM in which the function tests cannot be collectively executed, and the total number of cycles TC 'is TC' = 2 × 2 (m × n). Therefore, the dynamic RAM of this embodiment
The total number of cycles TC is the above normal dynamic RAM
Is reduced to (2m + 3n + 2) / 2 (m × n).
For example, when the storage capacity of the dynamic RAM is so-called 1 mega (1 million) bits and the number of word lines m and n is 1024, the reduction ratio is a small value such as 0.0024. As a result, the time required for a function test of a dynamic RAM or the like is significantly reduced, and cost reduction is achieved.

As shown in the present embodiment, by applying the present invention to a semiconductor memory device such as a dynamic RAM having a relatively large storage capacity, the following operation and effect can be obtained. That is, (1) a reference bit, a data collation circuit, and a check bit are provided for each data line, and a function test of a memory cell is performed. Write.

(B) This test data is written to the memory cell under test in word line units.

(C) The test data transferred to the memory cell under test is
The data is read out in word line units and compared with the original test data held in the reference bits by the corresponding data matching circuit.

(D) The corresponding check bit is selectively rewritten according to the result of the comparison by the data comparison circuit.

(E) After repeating the above items (b) to (d) for all word lines, check bits are sequentially read out,
Determine the normality of all memory cells coupled to the corresponding data line.

With such a procedure, it is possible to obtain an effect that functional tests of memory cells such as a dynamic RAM can be performed in the data line direction.

(2) In the above item (1), the reference bit and the check bit are dynamic memory cells similar to the memory cells constituting the memory array, and the original test data is replaced on the opposite side during the comparison and collation operation. By holding the data by the corresponding data line of the memory array, an effect that the increase in the required area of the dynamic RAM layout can be suppressed and the increase in the chip size can be suppressed can be obtained.

(3) According to the above items (1) and (2), it is possible to obtain an effect that a functional test of a memory cell such as a dynamic RAM having a relatively large column address space can be efficiently performed, and the cost can be reduced.

Although the invention made by the inventor has been specifically described based on the embodiments, the invention is not limited to the above-described embodiments, and various changes can be made without departing from the gist of the invention. Nor. For example, in FIG. 1, since the reset processing of the check bits of the data collation circuits DCL and DCR only writes the logic “1”,
The circuit may be configured so that it can be performed collectively in a cycle. In this case, the total number of cycles TC required for the functional test is
Furthermore, TC is reduced to 2 (2m + 2n + 3). Instead of the check bits, the data collation circuits DCL and DCR are arranged in series or in parallel, and each gate has an output node n1 of an exclusive OR circuit EO corresponding to the gate.
May be provided with a NOR gate circuit or a NAND gate circuit composed of a plurality of MOSFETs. In this case, since the test results of all the memory cells can be determined in one cycle,
The total number of siles TC is further reduced to TC = 2 (2m + n + 4). Sense amplifier SA and data matching circuit
When the number of circuit elements of DCL and DCR does not matter, the reference bit and the check bit may be in a normal register form. In FIG. 2, a dynamic RAM
May have a plurality of memory mats, or may have a multi-bit configuration. In FIG. 3, the check bit reset processing performed as step A can be performed at the same time as long as it is performed before the test bit read collation processing. Further, the refresh dummy cycle performed as step F may be performed at the end of the test mode. Further, various embodiments such as a specific circuit configuration of the memory array and its peripheral circuits shown in FIG. 1, a block configuration of the dynamic RAM shown in FIG. 2, and a combination of control signals and address signals are described. Can be taken.

In the above description, the dynamic RA, which is a field of application in which the invention made by the inventor
Although the description has been given of the case where the present invention is applied to M, the present invention is not limited to this. For example, the present invention can be applied to a multi-port RAM having a dynamic RAM as a basic configuration, a memory with a logic function, and the like. The present invention can be widely applied to at least a semiconductor memory device having a large number of memory cells arranged in a lattice and a digital integrated circuit device having such a semiconductor memory device.

〔The invention's effect〕

The effects obtained by the representative inventions among the inventions disclosed in the present application will be briefly described as follows. That is, a reference bit, a data collating circuit, and a check bit are provided for each data line, and a function test of the memory cell is performed. (A) The check bit is reset, and predetermined test data is written to all the reference bits.

(B) This test data is transferred to the memory cell under test in word line units.

(C) The test data transferred to the memory cell under test is read out in word line units, and is compared and collated with the original test data held in the reference bits by the corresponding data collation circuit.

(D) The corresponding check bit is selectively rewritten according to the result of the comparison by the data comparison circuit.

(E) After repeating the above items (b) to (d) for all word lines. The normality of all the memory cells coupled to the corresponding data line is determined by sequentially reading the check bits.

In order to retain the original test data during the comparison and collation operation, the reference bit and the check bit are configured by dynamic memory cells. Dynamic RAM that can perform functional tests of memory cells in the data line direction while suppressing an increase in the required layout area by using the data lines of the memory array
Etc. can be realized. As a result, it is possible to increase the efficiency of the function test of a memory cell such as a dynamic RAM having a relatively large column address space and promote the cost reduction.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an embodiment of a memory array of a dynamic RAM to which the present invention is applied and peripheral circuits thereof, and FIG. 2 is a dynamic memory including the memory array of FIG.
FIG. 3 is a block diagram showing an embodiment of the RAM, FIG. 3 is a processing flowchart showing an embodiment of the test mode of the dynamic RAM of FIG. 2, and FIG. 4 is an embodiment of the test mode of FIG. FIG. ARYL, ARYR …… Memory array, DCL, DCR …… Data collation circuit, EO …… Exclusive OR circuit, SA …… Sense amplifier, US
A: Unit amplification circuit, UPC: Unit precharge circuit, Cs
…… Capacitor for information storage, Qm …… MOSF for address selection
ET, Cc: Check bit capacitor, Qc: Check bit selection MOSFET, Cr: Reference bit capacitor, Qr: Reference bit selection MOSFET, Q1
~ Q4 ... P-channel MOSFET, Q11 ~ Q35 ... N-channel MOSFET. RAD: Row address decoder, CAD: Column address decoder, RAB: Row address buffer, AMX: Address multiplexer, RFC: Refresh address counter, CAB: Column address buffer, I / O: Data input / output circuit , TG ... timing generation circuit.

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int. Cl. ⁶ , DB name) G11C 29/00 G11C 11/401 H11L 21/8242 H11L 27/108 G01R 31/28

Claims (5)

(57) [Claims] A memory array including a plurality of memory cells provided at intersections of a plurality of word lines and a plurality of data lines;
A reference bit, a data collating circuit, a check bit, and a data holding means provided corresponding to the data line; and a function test of the plurality of memory cells includes: (a) setting the check bit to a predetermined initial state; Resetting and writing predetermined test data in the reference bits; (b) writing the test data held in the reference bits into the memory cells under test in word line units and transferring the test data to the data holding means; The test data held in the memory cell under test is read out in word line units and compared with the original test data held in the data holding means by a corresponding data matching circuit, and (d) the data matching circuit Is performed by selectively rewriting the corresponding check bit in accordance with the comparison result of That the semiconductor memory device. 2. The semiconductor device according to claim 1, wherein said reference bit and said check bit comprise a dynamic memory cell together with said memory cell, and said reference bit has a larger information storage capacity than said memory cell. Item 2. The semiconductor memory device according to item 1. 3. The semiconductor memory device employs a shared sense amplifier system, wherein the data holding means comprises:
3. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is realized by using a corresponding data line of the other memory array forming a pair with the memory array. 4. A plurality of first memory cells provided at intersections of a plurality of first word lines and a plurality of first data lines, a first check bit provided corresponding to the first data line, and a first check bit provided for the first data line. A first memory array including a data matching circuit; a plurality of second memory cells provided at intersections of a plurality of second word lines and a plurality of second data lines; and a plurality of second memory cells provided corresponding to the second data lines. A second memory array including a second check bit and a second data matching circuit; one end coupled to the first data line via a first switch, and the other end coupled to the second data line via a second switch And a reference bit and a sense amplifier provided corresponding to the third data line. 5. The function test of the plurality of first memory cells according to claim 4, wherein: (a) resetting the second check bit to a predetermined initial state; and storing predetermined test data in the reference bit. Writing, (b) writing the test data held in the reference bit to the first memory cell on a word line basis, transferring the test data to the second data line, and (c) holding the test data in the first memory cell (D) reading the test data to the first data line in word line units and comparing and comparing the test data with the original test data held in the corresponding second data line by the corresponding second data comparison circuit; A semiconductor memory device, which is performed by selectively rewriting a corresponding second check bit in accordance with a result of comparison by a data comparison circuit.