JP2942382B2 - Train detection receiver - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a train detection receiver for detecting a train by receiving a plurality of frequency signals transmitted from a train, and to prevent erroneous detection of a train due to noise mixed into a receiving antenna. It was done.

[0002]

2. Description of the Related Art FIG. 4 is a block diagram showing the configuration of a conventional train detecting receiver. In the figure, 1 is a receiving circuit,
Reference numerals 211 to 21n denote frequency classification circuits, reference numeral 3 denotes a judgment circuit, reference numeral 4 denotes a train, and reference numeral 5 denotes a rail.

The train 4 includes a transmitter 41 and a transmitting antenna 4
And 2. The transmitter 41 generates a transmission signal including a plurality of frequency signals f1 to fn having different frequencies. The transmission signal is usually composed of six or twelve frequency signals, and two frequency signals are always transmitted simultaneously in order to obtain a fail-safe property. ATC such as speed, train type, etc. is obtained by combining two frequency signals from six or twelve frequency signals.
The signal is configured. The transmission antenna 42 transmits the transmission signal to the train detection receiver.

When the train 4 passes, the receiving circuit 1
The transmitting signal transmitted by the transmitting antenna 42 is transmitted to the receiving antenna 1
1 and the received signal 12 is divided into frequency classifying circuits 211 to 2
1n. As the receiving antenna 11, a loop antenna or the like laid along the rail 5 is generally used.

Each of the frequency discriminating circuits 211 to 21n is usually constituted by a band pass filter circuit, and separates one frequency signal f1 to fn from the received signal 12 respectively.
The signals are logicalized by determining the levels of the frequency signals f1 to fn, and the logical signals 221 to 22n are supplied to the determination circuit 3.
If the levels of the frequency signals f1 to fn are equal to or higher than a predetermined level, the logic signals 221 to 22n of logic “1” are supplied to the determination circuit 3.

The judgment circuit 3 has a logical OR circuit 31 and a timer circuit 32. The logical OR circuit 31 calculates the logical sum of the logical signals 221 to 22n and supplies the logical signal 311 to the timer circuit 32. The timer circuit 32 starts accumulating a predetermined time T when the logic signal 311 is logic “1”, and outputs a logic signal 321 of logic “1” when supplied continuously for the predetermined time T. Train detection is performed when the logic signal 321 becomes logic "1".

FIG. 5 is a time chart showing a train detection method of the conventional train detection receiver. In FIG.
The same reference numerals as those shown above indicate identical components. The figure shows a case where the frequency signals f1 and f2 are received simultaneously at time t0. FIG. 5 will be described with reference to FIG.

The operation of each part at time t0 will be described. The frequency classification circuit 211 classifies the frequency signal f 1, determines the level of the frequency signal f 1, and outputs the logic signal 221 of logic “1” to the logic OR circuit 31.
To supply. Similarly, the frequency classification circuit 212 classifies the frequency signal f <b> 2, determines the level of the frequency signal f <b> 2, and supplies the logic signal 222 of logic “1” to the logic OR circuit 31. The frequency classification circuits 213 to 21n supply the logic signals 223 to 22n of logic “0” to the logic OR circuit 31 because the frequency signals f3 to fn do not exist. The logical OR circuit 31 outputs the logical signal 2
A logic signal 311 of a logic “1” is supplied to the timer circuit 32 by means of 21 and 222. The timer circuit 32 outputs the logic signal 31
The integration of the predetermined time T is started by 1 and the logic signal 321 of logic "0" is output.

Time (t0 + T) at which predetermined time T has elapsed
, The timer circuit 32 outputs the logic signal 32 of logic “1”.
Outputs 1. In the train detection, the logic signal 321 is logic "1"
It is performed when it becomes.

[0010]

However, in the above-mentioned conventional train detecting device, the frequency signals f1 to fn are low in frequency, and the logical OR circuit 31 has the frequency signal f1.
Since the logical sum of the logical signals 221 to 22n for which the levels of .about.fn have been determined is calculated, when an inductive load such as a motor is started or stopped, or when a train passes a rail joint. When the generated noise is received by the receiving antenna, as shown in FIG.
Noise does not exist in the frequency signals f1 to fn
There is a problem in that it is determined by the logical sum of the pseudo signals 221 to 22n converted to that of any of the frequency signals f1 to fn that the train is erroneously detected.

An object of the present invention is to provide a train detection receiver capable of solving the above-mentioned conventional problems and preventing erroneous detection of a train due to noise.

[0012]

In order to solve the above-mentioned problems, the present invention is a train detecting receiver having a receiving circuit, a plurality of signal sorting circuits, and a determining circuit, wherein the receiving circuit comprises: A circuit that receives a plurality of frequency signals having different frequencies transmitted from the train by a receiving antenna and supplies the received signals to the plurality of signal separation circuits, each of the signal separation circuits includes a frequency separation circuit and a signal width. Having a determination circuit, the frequency separation circuit separates one frequency signal from the received signal and supplies it to the signal width determination circuit,
A circuit that generates a detection signal when the signal width determination circuit detects the one frequency signal for a predetermined time or more, wherein the determination circuit calculates a logical sum of the detection signals supplied from each of the signal width determination circuits. It is characterized by taking.

[0013]

The frequency discriminating circuit discriminates one frequency signal from the received signal and supplies it to the signal width determining circuit. When the signal width determining circuit detects one frequency signal for a predetermined time or more, the detection signal is sent to the determining circuit. Since the signal is output, even if noise is mixed in the received signal, the detection signal due to the noise is not supplied to the determination circuit unless the noise is continuously mixed for a predetermined time or longer. Further, since the determination circuit is configured to calculate the logical sum of the detection signals supplied from each of the signal width determination circuits, the frequency signals f1 to f generated by the noise are obtained.
There is no direct OR of the n pseudo signals. For this reason, erroneous detection of a train due to noise can be prevented.

[0014]

FIG. 1 is a block diagram showing the configuration of a train detecting receiver according to the present invention. In the figure, the same reference numerals as those shown in FIG. 4 indicate identical components.
21 to 2n are signal classification circuits, and 231 to 23n are signal width determination circuits.

The signal classification circuit 21 includes a frequency classification circuit 21
1 and a signal width determination circuit 231. The frequency classification circuit 211 classifies the frequency signal f1 from the received signal 12, and supplies a logic signal 221 obtained by determining the level of the frequency signal f1 to the signal width determination circuit 231. If the level of the frequency signal f1 is equal to or higher than a predetermined value, the logic signal 221 of logic “1” is supplied to the signal width determination circuit 231. When the signal width determination circuit 231 detects the logic signal 221 of logic “1” continuously for a predetermined time T or more, the signal width determination circuit 231 supplies the determination circuit 3 with the logic signal 2 of logic “1” serving as a detection signal of the frequency signal f1.
41 is supplied. The predetermined time T is the time width t of the noise.
And the reception time of the frequency signals f1 to fn determined by the maximum speed of the train 4 and the size of the receiving antenna 11. In this embodiment, the frequency signals f1 to fn
Is about 15 to 20 msec, and the empirical time width t of the noise is several msec.
Set to ec. The same applies to the signal classification circuits 22 to 2n. In the present embodiment, in order to simplify the signal width determination circuit 231, the logic is performed before output from the frequency classification circuit 211. However, the logic may be performed before output from the signal width classification circuit 231. The determination circuit 3 has a logical OR circuit 31 and calculates the logical sum of the logic signals 241 to 24n supplied from the signal width determination circuits 231 to 23n, respectively.

FIG. 2 is a time chart showing a train detection method of the train detection receiver. In the figure, the same reference numerals as those in FIG. 1 indicate the same components. In the figure,
At time t0, the case where the normal frequency signals f1 and f2 are received simultaneously is shown. For simplicity of explanation,
It is assumed that noise does not mix into the received signal 12. Hereinafter, FIG. 2 will be described with reference to FIG.

The operation of each unit at time t0 will be described. The frequency classification circuit 211 classifies the frequency signal f1 and determines the level of the frequency signal f1 to determine the level of the logic signal 221.
Is supplied to the signal width determination circuit 231. Similarly, the frequency classification circuit 212 classifies the frequency signal f2, determines the level of the frequency signal f2, and supplies the logic signal 222 of logic “1” to the signal width determination circuit 232. Frequency classification circuit 21
Since the frequency signals f3 to fn do not exist in each of 3 to 21n, the logic signals 223 to 22n of logic "0" are supplied to the signal width determination circuits 233 to 23n. The signal width determination circuits 231 and 232 respectively output the logic signals 221 and 22
2, the integration of a predetermined time T is started, and the logic signals 241 and 242 of logic “0” are supplied to the logic OR circuit 31. The logic OR circuit 31 outputs a logic signal 311 of logic “0”.

The time when a predetermined time T has elapsed (t0 + T)
, Each of the signal width determination circuits 231 and 232 supplies the logic signals 241 and 242 of logic “1” to the logic OR circuit 31. The logic OR circuit 31 outputs a logic signal 311 of logic “1”. Train detection is performed when the logic signal 311 becomes logic "1".

FIG. 3 is a time chart showing the operation when noise is mixed in the train detecting receiver. In the drawing, the same reference numerals as those in FIG. 2 indicate the same components. In the figure, for the sake of simplicity of explanation, the normal frequency signals f1 to fn are ignored, and noise
As a result of the frequency analysis by 1 to 2n, the frequency signal f
This shows a case where the signal is converted into a pseudo signal of 1 to fn. The spontaneously generated noise is empirically about several milliseconds, and the pseudo signal of the frequency signals f1 to fn does not exceed several milliseconds. Therefore, noise is continuously generated at time intervals t,
This shows a case where pseudo signals of the frequency signals f1 to fn are sequentially generated. Hereinafter, FIG. 3 will be described with reference to FIG.

The noise generated at time t0 is the frequency signal f
1 pseudo signal. The frequency classification circuit 211
The pseudo signal of the frequency signal f1 is separated from the noise, the level is determined, and the logic signal 221 of logic “1” is supplied to the signal width determination circuit 231. The signal width determination circuit 231 starts integration of the time T, and outputs a logic signal of logic “0” to the logic OR circuit 3.
Feed to 1. Logic OR circuit 31 outputs a logic signal 311 of logic "0", and train detection is not performed.

The noise generated at time t 1 is the frequency signal f
2 pseudo signals. The frequency classification circuit 211 supplies a logic signal 221 of logic “0” to the signal width determination circuit 231. The signal width determination circuit 231 ends the integration of the time T. Therefore, even if the pseudo signal of the frequency signal f1 due to the noise is mixed, the detection signal 241 of the frequency signal f1 due to the noise is not supplied to the determination circuit 3 unless the mixing is continued for a predetermined time T or more. The frequency classification circuit 212 classifies the pseudo signal of the frequency signal f <b> 2 from the noise, determines the level, and supplies the logic signal 222 of logic “1” to the signal width determination circuit 232. The signal width determination circuit 232 starts to accumulate the time T, and outputs a logical “0” logical signal to the logical OR circuit 31.
To supply. The logic OR circuit 31 outputs a logic signal 311 of logic “0”, and no erroneous detection of the train is performed. Time t
The same operation is performed sequentially at 2 to tn.

As described above, the signal width determination circuits 21 to 2
n are supplied with the logic signals 241 to 24n to the determination circuit 3 when the frequency signals f1 to fn are continuously detected for a predetermined time T or more, respectively.
Even if noise is mixed in the reception signal 12, a predetermined time T
The detection signals 241 to 24n of the frequency signals f1 to fn due to noise are not supplied to the determination circuit 3 unless they are continuously mixed. Since the determination circuit 3 calculates the logical sum of the detection signals 241 to 24n supplied from the signal classification circuits 21 to 2n, respectively, the pseudo signal of the frequency signals f1 to fn generated by noise is directly obtained. There is no logical OR. For this reason, erroneous detection of a train due to noise can be prevented.

Although the embodiment has been described using a logic circuit for the sake of explanation, the same processing can be performed by software of a micro computer.

[0024]

As described above, according to the present invention, the frequency discriminating circuit discriminates one frequency signal from the received signal and supplies it to the signal width judging circuit, and the signal width judging circuit discriminates the one frequency signal to a predetermined value. A detection signal is output to the judgment circuit when it is detected for more than a time, and the judgment circuit ORs the detection signals supplied from each of the signal width judgment circuits to prevent false detection of trains due to noise. A train detection receiver that can be provided.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a train detection receiving device according to the present invention.

FIG. 2 is a time chart showing a train detection method of the train detection receiver according to the present invention.

FIG. 3 is a time chart showing an operation when noise is mixed in the train detection receiver according to the present invention.

FIG. 4 is a block diagram showing a configuration of a conventional train detection receiver.

FIG. 5 is a time chart showing a train detection method of a conventional train detection receiver.

FIG. 6 is a time chart showing an operation when noise is mixed in the conventional train detection receiver. Reference Signs List 1 reception circuit 11 reception antenna f1 to fn frequency signal 21 to 2n signal classification circuit 211 to 21n frequency classification circuit 231 to 23n signal width determination circuit 241 to 24n logic signal (detection signal) 3 determination circuit 31 logic OR circuit 4 train 41 transmission Vessel 42 transmission antenna 5 rail

Claims (1)

(57) [Claims] 1. A train detecting receiver comprising a receiving circuit, a plurality of signal sorting circuits, and a determining circuit, wherein the receiving circuit receives a plurality of frequency signals having different frequencies transmitted from the train by a receiving antenna. And a circuit for supplying a reception signal to the plurality of signal classification circuits, wherein each of the signal classification circuits has a frequency classification circuit and a signal width determination circuit, and the frequency classification circuit From each other to supply one frequency signal to the signal width determination circuit,
A circuit that generates a detection signal when the signal width determination circuit detects the one frequency signal for a predetermined time or more, wherein the determination circuit calculates a logical sum of the detection signals supplied from each of the signal width determination circuits. A train detection receiving device, characterized in that: