JP2941445B2 - Line sensor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a line sensor and, more particularly, to a line sensor suitable for high-speed signal reading.

[0002]

2. Description of the Related Art FIG. 3 is a block diagram of a conventional line sensor device. As shown in FIG. 3, the line sensor has a photodiode array 5 for converting the level of light received in a line into an electric signal. An electric signal from the photodiode row 5 is supplied to the first shift gate 3 by a first CC.
The data is transferred to the D shift register 1 and transferred to the second CCD shift register 2 by the second shift gate 4. First CCD shift register 1 and second CCD
The transfer signal from the shift register 2 is output from the output buffer 6. Power is supplied from the power supply terminal 0D, and the ground terminal SS is grounded. Shift pulse terminal S
From H, a shift clock is applied to the first shift gate 3 and the second shift gate 4. A clock pulse Φ ₁ for charge transfer is applied to the first CCD shift register 1 and the second CCD shift register 2 from the clock pulse input terminal Φ _1A . Clock pulse input terminal Φ
_{From 2A} , the first CCD shift register 1 and the second CC
A clock pulse Φ for charge transfer is supplied to the D shift register 2.
₂ is given. The clock pulse terminal Φ _1B supplies the first CCD shift register 1 with a clock pulse Φ ₁ for charge transfer in the final stage. From the clock pulse terminal Φ _2B , the second CCD shift register 2
A clock pulse Φ ₂ for charge transfer in the final stage is applied. A reset pulse is supplied to the output buffer 6 from the reset pulse input terminal RS for each unit output of the signal.

The following operation of the above configuration will be described in more detail with reference to the waveform diagram of FIG. 4A is a waveform diagram of the clock pulse Φ ₁ , FIG. 4B is a waveform diagram of the clock pulse Φ ₂ , and FIG. 4C is a reset pulse input terminal R.
FIG. 4D is a waveform diagram of the reset pulse from S, and FIG. 4D is a waveform diagram of the output signal from the signal output terminal OS.

When light strikes the photodiode array 5, electric charges are generated in each photodiode constituting the photodiode array 5 in accordance with the intensity of the light. When a shift pulse is applied to the shift pulse terminal SH in this state, the charges of the odd-numbered photodiodes in the photodiode row 5 are transferred in parallel to the first CCD shift register 1 through the first shift gate 3. The charges of the even-numbered photodiodes in the photodiode row 5 are transferred in parallel to the second CCD shift register 2 through the second shift gate 4. First CCD shift register 1 and the second CCD shift register 2 is supplied with the clock pulse [Phi ₁ from a clock pulse terminal [Phi _1A, is supplied with the clock pulses [Phi ₂ clock pulse terminal [Phi _2A, the signal The corresponding charge is serially transferred. On the other hand, the clock pulse Φ ₁ is supplied to the final output stage of the first CCD shift register 1 from the clock pulse terminal Φ _1B ,
The clock pulse Φ ₂ is supplied from the clock pulse terminal Φ _2B to the final output stage of the second CCD shift register 2, and the first CCD shift register
The charge from the shift register 1 and the charge from the second CCD shift register 2 are alternately supplied to the output buffer 6. The charge is converted into a voltage signal by the buffer 6 and is led out from the signal output terminal OS. Output buffer 6
Is provided with a reset pulse from a reset pulse input terminal RS every time a charge signal is converted into a voltage signal, and prepares for voltage conversion of sequentially input charge signals. As a result of the above operation, a voltage signal corresponding to the intensity of the light hitting the photodiode array 5 is sequentially extracted from the signal output terminal OS.

As a result of the above operation, the signal output terminal O
The effective output period of the output signal extracted from S is shown in FIG.
As shown in (a) to (d), clock pulses Φ ₁ , Φ
_This period is a period obtained by excluding the period in which the reset pulse is at the H level from the period at the L level of ₂ . That is, the output voltage signal is an intermittently valid signal. In order to convert the intermittent signal into a continuous signal, it is necessary to sample and hold the output signal from the signal output terminal OS for each unit of the output signal.

[0006]

The conventional line sensor device has been constructed as described above. Therefore, it is necessary to externally provide a circuit for sampling and holding the output signal from the signal output terminal OS. However, in general, a certain time is required to sample and hold a signal. However, in the conventional configuration, the output period of the output signal is determined by the period of the clock pulses Φ ₁ and Φ ₂ and the ratio of the signal valid period between them. For this reason, it is necessary to secure the time required for the sample hold. Therefore, there is a limit in shortening the period of the clock pulses Φ ₁ and Φ ₂ . Therefore, it is very difficult to drive the line sensor at high speed (that is, to increase the frequency of the clock pulses Φ ₁ and Φ ₂ ).

[0007] The present invention has been made in view of the above,
It is an object of the present invention to increase the rate of an effective signal output period obtained by a buffer for converting a signal from a CCD shift register into a voltage, thereby enabling high-speed clock pulses, that is, high-speed driving.

[0008]

According to the present invention, there is provided a line sensor comprising: a sensor in which light detecting elements are arranged in a row; and a first shift gate for taking out an odd-numbered output signal of the light detecting element of the sensor in parallel. A second shift gate for taking out in parallel an even-numbered output signal of the photodetector of the sensor; and serially transferring a signal from the first shift gate by a first clock pulse and a second clock pulse. A first transfer unit for performing serial transfer of a signal from the second shift gate using a first clock pulse and a second clock pulse, and an output signal of the first transfer unit. An output buffer for receiving intermittently the output signals of the two transfer means and outputting as an intermittent signal sequence while being reset by a reset pulse for each signal unit; A first-stage shift pulse in which a non-reset period of the reset pulse is added to the leading edge of the first clock pulse by processing the clock pulse, the second clock pulse, and the reset pulse. Clock pulse processing for providing a final-stage shift pulse in which a non-reset period of a reset pulse is added to the leading edge of the second clock pulse to the final stage of the second transfer unit, Means.

[0009]

The odd-numbered output signals of the photodetectors of the sensor having the photodetectors arranged in a row are taken out in parallel through the first shift gate. The first shift gate provides this to the first transfer means. At the same time, the even-numbered output signals of the light detecting elements of the sensor are taken out in parallel through the second shift gate. This second gate provides this to the second transfer means. The first transfer gate is serially transferred by a first clock pulse and a second clock pulse. The second transfer means,
By the first clock pulse and the second clock pulse,
Serially transferred. The final stage shift pulse in which the non-reset period of the reset pulse is added to the leading edge of the first clock pulse from the clock pulse processing means is applied to the final stage of the first transfer gate. At the same time, the clock pulse processing means sends the second
Of the reset pulse is added to the leading edge of the clock pulse of FIG. Thus, the output buffer alternately receives the output signal of the first transfer unit and the output signal of the second transfer unit,
The signal is output as an intermittent signal sequence while being reset for each signal unit by the reset pulse.

[0010]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of a line sensor according to one embodiment of the present invention. The configuration of FIG. 1 differs from the configuration of FIG. 3 in that the first CCD shift register 1 and the second
A changeover switch 7 is provided to switch the clock pulse applied to the last stage of the D shift register 2. This changeover switch 7 has a final-stage pulse changeover terminal SW
In such a manner that the switching is performed by the switching signal from the user. The changeover switch 7 reset pulse is inputted with a clock pulse terminal [Phi _1B and the clock pulse terminal [Phi _2B is connected. The changeover switch 7 adds clock pulses Φ ₁ and Φ ₂ from the clock pulse terminals Φ _1B and Φ _{2B in} response to a signal from the last-stage pulse switching terminal SW. Thereby, the first CCD shift register 1 and the second CCD shift register
The effective period of the clock pulse at the last stage of the CCD shift register 2 is set substantially long. Thereby, the output period of one unit of the signal is set long.

Next, the operation of the above configuration will be described in more detail with reference to the waveform diagram of FIG. 4A shows the waveform of the clock pulse Φ ₁ , FIG. 4B shows the waveform of the clock pulse Φ ₂ , and FIG. 4C shows the reset pulse input terminal R.
FIG. 4D is a waveform diagram of the reset pulse from S, and FIG. 4D is a waveform diagram of the output signal from the signal output terminal OS.

When light strikes the photodiode array 5, charges are generated in each of the photodiodes forming the photodiode array 5 in accordance with the intensity of the light. In this state, a shift pulse is applied to the shift pulse terminal SH. As a result, the charges of the odd-numbered photodiodes in the photodiode row 5 are transferred through the first shift gate 3 to the first C
The data is transferred to the CD shift register 1 in parallel. The charges of the even-numbered photodiodes in the photodiode row 5 are transferred in parallel to the second CCD shift register 2 through the second shift gate 4. The first CCD shift register 1 and the second CCD shift register 2 receive a clock pulse Φ ₁ from a clock pulse terminal Φ _1A.
Is supplied. These registers 1 and ₂ are supplied with a clock pulse Φ ₂ from a clock pulse terminal Φ _2A . These registers 1 and 2 serially transfer charges corresponding to the magnitude of the signal. On the other hand, the first CCD
The clock pulse Φ ₁ is supplied to the final output stage of the shift register 1 from the clock pulse terminal Φ _1B via the changeover switch 7. The clock pulse Φ ₂ is supplied to the final output stage of the second CCD shift register 2 from the clock pulse terminal Φ _2B via the changeover switch 7. The reset pulse acts to reset the output buffer 6 at the H level. When the reset pulse is added to the clock pulses Φ ₁ and Φ ₂ , L for the non-reset period
The level part is added as a valid part. Then, the first CCD shift register 1 is output through the output buffer 6.
And the charge from the second CCD shift register 2 are alternately supplied to the output buffer 6. The charges are converted into a voltage signal by the buffer 6, and the signal output terminal OS
Is derived to the outside. Each time the charge signal is converted to a voltage signal, a reset pulse input terminal R
A reset pulse is given from S. This allows
The buffer 6 prepares for voltage conversion of sequentially input charge signals. As a result of the above operation, a voltage signal corresponding to the intensity of the light hitting the photodiode array 5 is sequentially extracted from the signal output terminal OS.

As a result of the above operation, the signal output terminal O
The effective output period of the output signal extracted from S is shown in FIG.
(A) to (d) are obtained. That is, the output voltage signal is an intermittently effective signal having a signal output period longer by the period A than that of the related art. Then, the sample-and-hold circuit for converting the intermittent signal into a continuous signal samples and holds a signal having a long effective period ratio. In other words, even if the frequency of the clock pulses Φ ₁ and Φ ₂ is increased, a signal output period sufficient for sample and hold can be obtained.

Therefore, it is possible to drive the line sensor at a higher speed than in the conventional case.

In the above embodiment, the pulse applied to the last stage of the first CCD shift register 1 and the second CCD shift register 2 is switched by the changeover switch 7 between the clock pulses Φ ₁ , Φ ₂ and the reset pulse. The configuration in which the signal output period is lengthened by this is exemplified. But,
The same effect can be obtained by configuring a logic circuit instead of the changeover switch 7 and thereby switching the last stage pulse.

The circuit for extending the effective signal output period can be formed on a semiconductor substrate constituting a device. Therefore, there is an advantage that it is not necessary to increase the scale of the external circuit, and the wiring is built-in, so that it is hardly affected by external noise.

[0018]

As described above, according to the present invention, by effectively increasing the length of the last shift pulse of the CCD shift register for transferring the charge of the line sensor, one unit of signal can be obtained. Since the ratio of the signal valid period to the transfer period is increased, the signal transfer period can be increased, and high-speed driving can be performed.

[Brief description of the drawings]

FIG. 1 is a block diagram of a line sensor device according to one embodiment of the present invention.

FIG. 2 is a waveform chart for explaining the operation of FIG.

FIG. 3 is a block diagram of a conventional line sensor device.

FIG. 4 is a waveform chart for explaining the operation of FIG. 3;

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 first CCD shift register 2 second CCD shift register 3 first shift gate 4 second shift gate 5 photodiode array 6 output buffer 7 switch

Claims (1)

(57) [Claims] 1. A sensor in which photodetectors are arranged in a row, a first shift gate for taking out an odd-numbered output signal of the photodetectors of the sensor in parallel, and an even number of the photodetectors of the sensor. A second shift gate for extracting a second output signal in parallel; a first transfer unit for serially transferring a signal from the first shift gate by a first clock pulse and a second clock pulse; A second transfer means for serially transferring a signal from the shift gate by a first clock pulse and a second clock pulse, and alternately receiving an output signal of the first transfer means and an output signal of the second transfer means An output buffer that outputs an intermittent signal sequence while being reset for each unit of signal by a reset pulse, the first clock pulse, and the second clock pulse. And the reset pulse is processed to provide a final-stage shift pulse in which the non-reset period of the reset pulse is added to the leading edge of the first clock pulse to the final stage of the first transfer means. Clock pulse processing means for applying a final-stage shift pulse in which a non-reset period of a reset pulse is added to the leading edge of the second clock pulse to the final stage of the second transfer means. Line sensor.