JP2941048B2 - Method for manufacturing SOI substrate - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial applications]

This invention is SOI (Silicon on Insulator)
The present invention relates to a method for manufacturing a substrate.

[Prior art]

As the miniaturization of semiconductor devices progresses, the process becomes complicated in order to separate the elements from the manufacturing side, and various problems such as a short channel effect occur in the element characteristics. Since many of these problems can be solved by using an SOI substrate, development of an SOI substrate has been actively performed in recent years. For example, FIG. 4 shows SOI by a conventional bonding polishing method.
4 shows a procedure for manufacturing a substrate. First, as shown in FIG. 2A, a plurality of grooves A1, A2, A3 having a concave cross section and a depth D (about D-100 nm) are formed on the surface 1a of the silicon substrate 1 using a photoresist R as a mask. Thereby, each groove A
Regions (hereinafter, referred to as “element regions”) S1 and S2 in which the substrate surface 1a protrudes are formed between 1, A2 and A3. Next, as shown in FIG. 2B, after removing the photoresist R,
By the thermal oxidation, the grooves A1, A2,
A silicon oxide film 3 covering A3 and the element regions S1 and S2 is formed, and subsequently, a polycrystalline silicon film 4 having a thickness exceeding the depth D of each of the trenches A1, A2 and A3 is deposited. At this time, depressions A11, A12, and A13 are formed on the surface 4a of the polycrystalline silicon film 4, reflecting the shapes of the grooves A1, A2, and A3. Next, FIG.
As shown in FIG. 5, the surface 4a of the polycrystalline silicon film 4 is ground and polished to remove the dents A11, A12, and A13, and the flat surface 4f
To form Next, as shown in FIG. 3D, a silicon substrate 9 is brought into close contact with the flat surface 4f of the polycrystalline silicon film 4,
Heat to high temperature and bond at the atomic bonding level. next,
The silicon substrate 1 is ground and polished from the back surface 1b of the silicon substrate 1 to a position where the insulating film 3 in each of the grooves A1, A2, A3 is exposed, and as shown in FIG. , A3, the element regions S1 and S2 are exposed. Thus, the SOI substrate 100 is formed while leaving the element regions S1 and S2 while being surrounded by the insulating film 3. Note that the element regions S1, S2
Is a region in which a semiconductor element is to be formed. On the other hand, portions in the trenches A1, A2, A3 of the insulating film 3 become field regions F1, F2, F3 separating the element regions S1, S2.

[Problems to be solved by the invention]

By the way, a MOSFET (field effect transistor) formed by using the SOI substrate 100 formed by the above-described method has a configuration as shown in FIG. That is, each element region S
1, a source region 10s and a drain region 10d are formed in S2. Further, a gate electrode 11 is provided on a channel region 10c between the source region 10s and the drain region 10d via a gate oxide film 14, thereby forming MOSFETs TR1 and TR2. Then, an interlayer insulating film 12 is deposited, two openings (contact holes) 12W are formed in the interlayer insulating film 12 for each transistor, and a source electrode 13s and a drain electrode 13d are formed.
Are provided. As described above, in each of the MOSFETs TR1 and TR2, a number of contact holes 12W are provided in the interlayer insulating film 12 to perform electrode wiring. For this reason, there is a problem that when a multilayer wiring is formed thereon, a contact failure is likely to occur, and the yield and reliability are reduced. SUMMARY OF THE INVENTION It is an object of the present invention to provide a method for manufacturing an SOI substrate which can reduce the number of contact holes provided in an interlayer insulating film and therefore can improve the yield and reliability of an element formed in an element region.

[Means for Solving the Problems]

In order to achieve the above object, a method for manufacturing an SOI substrate according to the present invention is characterized in that a plurality of grooves having a concave cross section and a predetermined depth are formed on a surface of a first silicon substrate. Forming an element region in which a flat portion of the substrate surface protrudes; forming a first insulating film covering the groove and the protruding region on the surface of the first silicon substrate; A step of etching and removing a portion of the film covering portions to be the source and drain of the element region by a predetermined pattern, and depositing a conductive film on the surface side of the first silicon substrate; Forming an electrode wiring leading to the source and drain portions by etching the substrate with a predetermined pattern; and forming a depth of the groove and the first insulating film on the surface side of the first silicon substrate. Exceed the thickness of conductive film Depositing a second insulating film having a thickness of 3 mm, and applying an organic film on the surface of the second insulating film so that the front side thereof is flat, and forming the second insulating film on the surface of the second insulating film. A step of filling the depression formed by reflecting the shape of the groove and the pattern of the first insulating film and the conductive film, and the surface of the organic film under the condition that the etching rates of the organic film and the second insulating film become equal. Forming a flat surface on the front side of the first silicon substrate by performing etching from the side to the point where the dent of the second insulating film disappears; and forming a flat surface of the first silicon substrate. Heating and bonding a second silicon substrate to a side of the first silicon substrate; and bonding the first silicon substrate in each of the grooves from the back side of the first silicon substrate.
Shaving the first silicon substrate until the insulating film is exposed, and exposing the element region between the grooves in a state surrounded by the first insulating film. I have.

[Action]

According to the method for manufacturing an SOI substrate of the present invention, the electrode wiring is provided on the side of the second silicon substrate in each element region, the electrode wiring being connected to a source and a drain. Therefore, after a device is formed by providing a gate insulating film and a gate electrode on the exposed side of the device region, the number of contact holes to be provided in the interlayer insulating film is reduced. Therefore, the yield and reliability of the device formed in the device region are improved. A part of the electrode wiring is formed by providing an opening in the interlayer insulating film so that a signal can be output to the outside of the element.

【Example】

Hereinafter, a method for manufacturing an SOI substrate of the present invention will be described in detail with reference to examples. First, as shown in FIG.
A plurality of grooves A1, A2, A3 having a concave section and a depth D (about D to about 100 nm) are formed on the surface 1a of the silicon substrate 1 by RIE (reactive ion etching) using the resist R as a mask. As a result, element regions S1 and S2 are formed between the grooves A1, A2 and A3 so that the flat portions of the substrate surface 1a protrude. Next, as shown in FIG. 3B, after removing the resist R, each groove is formed on the surface 1a of the silicon substrate 1 by thermal oxidation.
A 400 nm thick silicon oxide film (first insulating film) 3 covering A1, A2, A3 and the element regions S1, S2 is formed. Next, as shown in FIG. 3C, a resist R2 having a predetermined pattern is provided on the surface of the silicon oxide film 3 by photolithography. Then, openings W1,..., W4 are formed by removing portions of the silicon oxide film 3 that cover the portions to be the sources and drains of the element regions S1, S2. Next, after removing the photoresist R2, as shown in FIG. 3D, a 400 nm-thick silicon oxide film 3 having openings W1,..., W4 is formed on the silicon oxide film 3 by CVD (chemical vapor deposition). A melting point metal (for example, W) film 5 is deposited. Subsequently, as shown in FIG. 4E, a photoresist R3 having a predetermined pattern is provided on the surface of the high melting point metal film 5 by a photolithography method. Then, the portion of the refractory metal film 5 that covers the center of the element regions S1 and S2 is removed by etching by RIE. At this time, portions of the refractory metal film 5 covering the openings W1,..., W4 are not etched and are left as they are. As a result, the sources of the element regions S1 and S2,
Electrode wirings 51, 52, and 53 connected to a portion to be a drain are formed. Next, the photoresist R3 is removed as shown in FIG. Subsequently, on the surface 1a side of the silicon substrate 1, a depth D of each of the grooves A1, A2, A3 is formed as a second insulating film by a CVD method.
100 nm, thickness of silicon oxide film 3 400 nm, refractory metal film 5
P with a thickness of about 1 μm exceeding the total size of 400 nm
An SG (phosphorus glass) film 6 is deposited. At this time, the PSG film 6
The surface 6a has a depression A21 reflecting the shape of each of the grooves A1, A2, A3 and the pattern of the silicon oxide film 3 and the refractory metal film 5.
.., A24 are formed. Further, a photoresist R4 made of an organic material is spin-coated on the surface 6a of the PSG film 6 so that the surface R4f is flat. Thereby, the depressions A21,..., A24 of the PSG film 6 are filled with the photoresist R4. Next, as shown in FIG. 3G, the RIE method is used to change the photoresist R4 from the surface R4f side under the condition that the etching rates of the photoresist R4 and the PSG film 6 become equal.
Etching is performed until the depressions A21,..., A24 of the SG film 6 disappear. Thus, a flat surface 6f is formed on the front side of the PSG film 6 (etch back method). Next, as shown in FIG. 2H, the flat surface 6f of the PSG film 6 is formed.
A polycrystalline silicon film 8 having a uniform thickness is deposited thereon by a CVD method so that the surface side becomes a flat surface 8f. Subsequently, the second silicon substrate 9 is brought into close contact with the flat surface 8f of the polycrystalline silicon film 8, subjected to a high-temperature heat treatment at about 1000 ° C., and bonded at an atomic bonding level. Next, each of the grooves A1, A2,
The silicon substrate 1 is ground and polished until the silicon oxide film 3 in A3 is exposed, and the element regions S1 and S2 are surrounded by the silicon oxide film 3 as shown in FIG. Exposure between A1, A2, A3. Since the silicon oxide film 3 has a higher hardness than the silicon substrate 1, it plays a role of stopping polishing when it is exposed. Thus, the SOI substrate 200 is formed leaving the element regions S1 and S2 while being surrounded by the silicon oxide film 3. Note that F1, F2, and F3 each indicate a field area.
Thus, the SOI substrate 200 can be formed by adding a few steps to the conventional bonding and polishing method. The complementary MOSFET formed using the SOI substrate 200 has a configuration as shown in FIG. That is, each element region S
1, a source region 10s and a drain region 10d are formed in S2. Further, a gate electrode 11 is provided on a channel region 10c between the source region 10s and the drain region 10d via a gate oxide film 14, thereby forming an n-channel MOSFET TR10 and a p-channel MOSFET TR20. Subsequently, the interlayer insulating film 1
2 is deposited, and a contact hole 12W is formed in the interlayer insulating film 12 for each transistor. Then, a wiring 15 connected to each source region 10s is provided. Thus, the electrode wirings 51, 52, 63 connected to the source region 10s and the drain region 10d are provided on the silicon substrate 9 side of the SOI substrate 200.
Is provided, the number of contact holes to be provided in the interlayer insulating film 12 can be reduced. Therefore, the MOSFETs TR10 and TR20 formed in the element regions S1 and S2
Yield and reliability can be improved. In this embodiment, the back bias electrode 5 is made of a refractory metal film. However, the present invention is not limited to this, and a film having conductivity such as a polycrystalline silicon film can be widely used. After forming a flat surface 6f on the surface side of the PSG film 6 (step), a polycrystalline silicon film 8 was deposited (step).
However, it is not limited to this. Depression A on surface 6a of PSG film 6
The polycrystalline silicon film 8 may be deposited while leaving A21,..., A24, and the pits formed on the surface of the polycrystalline silicon film 8 may be planarized by an etch-back method. Also,
After forming a flat surface 6f on the surface side of the PSG film 6 (process),
Instead of depositing the polycrystalline silicon film 8, the silicon substrate 9 may be directly attached to the flat surface 6f.

【The invention's effect】

As is clear from the above, according to the method for manufacturing an SOI substrate of the present invention, the SOI substrate having the electrode wiring on the side of the second silicon substrate in the element region can be obtained by adding only a few steps.
A substrate can be made. Therefore, the number of contact holes to be provided in the interlayer insulating film can be reduced, and the yield and reliability of the device formed in the device region can be improved.

[Brief description of the drawings]

FIG. 1 is a process chart for explaining a method of manufacturing an SOI substrate according to one embodiment of the present invention, and FIG. 2 is manufactured by the above-described method.
Sectional view showing state where MOSFET was fabricated on SOI substrate.
Figure shows MOSFET on SOI substrate manufactured by conventional manufacturing method
FIG. 4 is a cross-sectional view showing a state in which is fabricated, and FIG. 4 is a process chart for explaining a conventional method for manufacturing an SOI substrate. DESCRIPTION OF SYMBOLS 1 ... 1st silicon substrate, 3 ... silicon oxide film, 5 ... refractory metal film, 6 ... PSG film, 8 ... polycrystalline silicon film, 9 ...
Second silicon substrate, 12 ... interlayer insulating film, 12W ... contact hole, 15 ... wiring, 51, 52, 53 ... electrode wiring, 200 ... SOI substrate, A1, A2, A3 ... groove, F1, F2, F3 ... field Region, R, R2, R
3 ... photoresist, S1, S2 ... element area, W1, ..., W4 ... opening.

Claims (1)

(57) [Claims] 1. An element region in which a flat portion of the substrate surface protrudes between each groove by forming a plurality of grooves having a concave cross section and a predetermined depth on the surface of the first silicon substrate. Forming a first insulating film on the surface of the first silicon substrate, the first insulating film covering the trench and the protruding region; and forming a source and a drain of the element region in the first insulating film. Removing a portion covering the portion by etching with a predetermined pattern; and depositing a conductive film on the surface side of the first silicon substrate;
Etching the conductive film in a predetermined pattern to form an electrode wiring connected to the source / drain portions; and forming a depth of the groove and a first depth on the surface side of the first silicon substrate. The second layer having a thickness exceeding the thickness of the insulating film and the conductive film
Depositing an insulating film, and applying an organic film on the surface of the second insulating film so that the surface side becomes a flat surface, and forming the groove and the second shape on the surface of the second insulating film. A step of filling the depression formed by reflecting the pattern of the first insulating film and the conductive film; and a step of filling the second layer from the surface side of the organic film under the condition that the etching rates of the organic film and the second insulating film become equal. Etching until the above-mentioned dent of the insulating film disappears,
A step of forming a flat surface on the front side of the first silicon substrate, a step of heating and bonding a second silicon substrate to the front side of the flattened first silicon substrate, The first silicon substrate is shaved from the back surface side of the silicon substrate to a position where the first insulating film in each of the grooves is exposed, and the element region is surrounded by the first insulating film. Exposing between the grooves.