JP2939248B2 - Branch prediction method and processor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for decoding a branch instruction in advance, predicting a result of a branch, reading an instruction of a branch destination in advance based on the prediction, and achieving a prediction when an actual branch instruction is executed. The present invention relates to a branch prediction method and a processor for reducing performance degradation due to instruction reading delay due to a branch instruction.

[0002]

2. Description of the Related Art In recent years, with the development of computers, devices using processors have become widespread in various fields. The processor may include a branch prediction device in order to reduce a hazard caused by a branch instruction. 2. Description of the Related Art In a processor including a conventional branch prediction device, an instruction is decoded in advance before execution, and if the instruction is a branch instruction, a branch result is predicted, and an instruction at a branch destination is read in advance based on the execution result of the branch instruction.

[0003] Branch prediction methods include static branch prediction and dynamic branch prediction. Static branch prediction is to determine in advance whether a branch is taken or not taken by hardware. For example, it can be determined that all branches are always predicted not to be taken. In this case, if the ratio of non-establishment is large, the effect is increased, but if the ratio of establishment is large, the effect is opposite. In another example, there is a method of determining that the backward branch is predicted to be taken and the forward branch is predicted to be not taken. This method is based on BTFN (Backward branch T).
aken, Forward branch Not T
aken) method. Since the backward branch often forms a loop, it can be assumed that the branch is taken in most cases. Therefore, the backward branch can be predicted with high accuracy. However, in the case of the forward branch, the same effect as described above may not be obtained.

[0004] Dynamic branch prediction solves the problem of such static branch prediction. In dynamic branch prediction, the result of each branch instruction is left as a history and used for prediction of the next branch. FIG. 8 shows a conceptual diagram of dynamic branch prediction. As shown in FIG. 8, in order to perform dynamic branch prediction, a table in which one entry includes an absolute address of a branch instruction and branch result information (for example, “1” when a branch is taken and “0” when a branch is not taken). Are required as branch prediction information for performing branch prediction. When a branch instruction is executed, its address and result are recorded in any of the entries. Next, when a branch instruction having the same address is decoded in advance, a corresponding entry is searched using the address, and branch prediction is performed with reference to the recorded branch result information. If the branch prediction is taken, the instruction at the branch destination is read from the memory storing the instruction. If the branch prediction is not taken, the next instruction is read from the memory. Further, when the branch result matches the prediction result when the same branch instruction is executed, the instruction read from the memory in advance by the prediction is executed. At this time, the delay in reading the instruction at the branch destination from the memory is reduced because it is performed in advance. FIG. 8 conceptually shows addresses A to D and result information of branch instructions corresponding to the addresses A to D.

As described above, in the conventional dynamic branch prediction,
The prediction of the branch result can be given for each branch instruction, and the prediction is performed using the result of the previous (or earlier), so that the accuracy of the branch prediction can be increased. At this time, a table for holding the address of the branch instruction and the result information and a means for searching for a necessary entry are required.

[0006]

However, in the conventional dynamic branch prediction, since an address is held for each branch instruction, a large storage capacity is required for performing the branch prediction. Since it is necessary to search for instruction information at high speed, there is a problem that an address comparing device is required for each entry. Usually, in order to enhance the effect of branch prediction, it is necessary to cover many branch instructions. Therefore, the number of entries in the table is increased (usually 512 to 1024 entries).

A first object of the present invention is to reduce a storage capacity for holding branch prediction information and to simplify a circuit for performing information retrieval while minimizing a decrease in branch prediction accuracy. It is to provide a prediction method. A second object of the present invention is to minimize a decrease in branch prediction accuracy,
An object of the present invention is to provide a processor including a branch prediction device capable of reducing a storage capacity for holding branch prediction information and simplifying a circuit for performing information search.

[0008]

In order to solve this problem, a branch prediction method according to the present invention uses a branch instruction that is taken or not taken.
A first step of recording, as history information , a branch result corresponding to the relative position from the starting point, and the history based on the relative position of the preceding decoding instruction from the starting point at the time of preceding decoding before execution of the next branch instruction. A second step of predicting a branch result of the next branch instruction with reference to information.

In this case, the first step includes a starting position holding step for holding the position of the starting instruction, an execution decoding step for decoding the instruction for execution, and a reference to the instruction position held in the starting position holding step. An instruction position obtaining step of obtaining a relative position of an instruction decoded for execution as
If the decoded instruction is a branch instruction, a history recording step of recording the branch result of the branch instruction as history information corresponding to the relative position of the branch instruction.

The second step includes a preceding decoding step of precedingly decoding the instruction before execution of the next instruction, and a preceding step of obtaining a relative position of the previously decoded instruction based on the instruction position held in the starting position holding step. An instruction position acquisition step, a history reference step of referring to history information corresponding to the relative position of the previously decoded branch instruction when the preceding decoded instruction is a branch instruction, and a preceding step using the result obtained by referring to the history information. A prediction step of predicting the execution result of the decoded branch instruction.

The starting point holding step includes, for example, a step of holding an address of an instruction of a starting point to be executed. More specifically, the starting position holding step includes, for example, a loop detecting step of detecting a loop structure of the program, and a step of extracting and holding the address of the first instruction of the loop based on the loop structure of the program detected by the loop detecting step. Consists of The above-described loop detecting step includes a step of detecting a loop structure of a program by decoding a branch instruction that branches backward, for example.

The starting position holding step includes, for example, a block head address detecting step for detecting a head address of a program block, and a block head address holding step for holding an address detected in the block head address detecting step. In some cases. The above-mentioned instruction position obtaining step includes, for example, a step of counting the number of instructions decoded for execution to obtain the number of instructions, and in response to this, the preceding instruction position obtaining step counts the number of the previously decoded instructions and reduces the number of instructions. The steps of obtaining.

The instruction position obtaining step further includes, for example, a step of counting instructions which have been found to be branch instructions by decoding for execution to obtain the number of instructions, and correspondingly obtaining a preceding instruction position. In some cases, the step includes a step of counting instructions which are determined to be branch instructions by preceding decoding to obtain the number of instructions. Further, the instruction position obtaining step further includes, for example, a step of obtaining a difference between the address of the decoded instruction for execution and the address held by the starting position holding step. There may be a step of obtaining a difference between the address of the pre-decoded instruction and the address held in the starting position holding step.

[0014] According to the branch prediction method of the present invention, the branch instruction
The branching result indicating whether the
Correspondingly records as history information and executes the next branch instruction
Sometimes history information based on the relative position of the preceding decoding instruction from the starting point
Is used to predict the branch result of a branch instruction
Therefore, as branch prediction information necessary for performing branch prediction,
Only the start point information, relative position information, and history information.
The result of a branch instruction can be predicted.
Information amount in the case of the conventional example holding dress and history information
Compared to the information of the starting point and the relative position information and
Branching due to the small amount of information when
Reduce the memory capacity to hold prediction information
Can be.

Further, conventionally, the address is retained for each branch instruction, and each time a branch instruction appears, the corresponding branch instruction is searched. In order to compare the address of the branch instruction with all the retained addresses, However, according to the branch prediction method of the present invention, the relative position information (for example, the relative address value) has a smaller amount of information than the address information. Can be reduced, and the circuit scale of the search circuit can be reduced. It also leads to lower power consumption.

Further, the processor of the present invention provides a
A first means for recording, as history information , a branch result indicating whether a branch has been taken or not , corresponding to a relative position from the starting point; And second means for predicting the branch result of the next branch instruction by referring to the history information. In this case, the first means includes a starting position holding means for holding the position of the starting instruction, an execution decoding means for decoding the instruction for execution, and an execution position based on the instruction position held by the starting position holding means. Instruction position obtaining means for obtaining the relative position of the decoded instruction, and when the decoded instruction is a branch instruction,
History recording means for recording the branch result of the branch instruction as history information corresponding to the relative position of the branch instruction.

The second means includes a preceding decoding means for decoding the instruction before execution of the next instruction, and a preceding means for obtaining a relative position of the previously decoded instruction based on the instruction position held by the starting position holding means. Instruction position acquisition means, history reference means for referring to history information corresponding to the relative position of the previously decoded branch instruction when the predecoded instruction is a branch instruction, and precedent using the result obtained by referring to the history information; Branch prediction means for predicting the execution result of the decoded branch instruction.

The starting position holding means comprises, for example, means for holding an address of an instruction of a starting point to be executed. More specifically, the starting position holding means includes:
For example, it comprises a loop detecting means for detecting the loop structure of the program, and a loop head address holding means for extracting and holding the address of the head instruction of the loop based on the loop structure of the program detected by the loop detecting means. The above-mentioned loop detecting means comprises, for example, means for detecting a loop structure of a program by decoding a backward branch instruction.

The starting position holding means includes, for example, a block head address detecting means for detecting a head address of a program block, and a block head address holding means for holding an address detected by the block head address detecting means. In some cases. The above-mentioned instruction position obtaining means includes, for example, means for counting instructions decoded for execution to obtain the number of instructions. Means to obtain.

Further, the instruction position obtaining means includes means for obtaining the number of instructions by counting the number of instructions determined to be a branch instruction by decoding for execution, for example. In some cases, the means may be a means for counting instructions determined to be branch instructions by preceding decoding to obtain the number of instructions. Further, the instruction position obtaining means may further comprise a means for obtaining a difference between the address of the decoded instruction for execution and the address held by the starting position holding means, for example. There may be a case in which a means for obtaining a difference between the address of the instruction decoded in advance and the address held by the starting position holding means is provided.

[0021] According to the processor of the present invention, the branch instruction
Indicate success / failureMatch the branch result to the relative position from the starting point.
In response to history informationAsRecord and execute next branch instruction
History information based on the relative position of the preceding decoding instruction from the starting point.
Means for predicting the branch result of a branch instruction by referring to
Therefore, as branch prediction information necessary for performing branch prediction,
Only the start point information, relative position information, and history information.
The result of a branch instruction can be predicted.
Information amount in the case of the conventional example holding dress and history information
Compared to the information of the starting point and the relative position information and
Branching due to the small amount of information when
Reduce the memory capacity to hold prediction information
Can be.

Further, conventionally, a structure is provided in which the address is held for each branch instruction, and means for searching for the corresponding branch instruction each time the branch instruction appears is used. Although a search circuit having a plurality of comparators for comparison is required, according to the processor of the present invention, relative position information (for example, relative address value)
Since the information amount is smaller than the address information, the size of the comparator can be reduced, and the circuit size of the search circuit can be reduced. It also leads to lower power consumption.

[0023]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of a branch prediction method and a processor according to the present invention will be described below with reference to FIGS.
This will be described in detail with reference to FIG. FIG. 1 is a block diagram illustrating a hardware configuration of a processor according to an embodiment of the present invention. This processor is roughly divided into an instruction supply unit 100 and an instruction execution unit 200.

In the present embodiment, an example of information on the number of branch instructions as relative position information is shown. In the case of the number information of the branch instructions, the obtained information is a continuous value (a value that simply increases by one), so that it is not necessary to hold the information for searching, and is used as an index storing the history information as it is. be able to. The instruction supply unit 100 reads the instruction 101 from the instruction memory according to the program, and supplies the instruction 101 to the instruction execution unit 200 together with the instruction address 102. If the instruction supplied to the instruction execution unit 200 is a branch instruction, the instruction supply unit 100 executes the branch instruction with reference to the branch determination result 201 of the instruction execution unit 200. The instruction execution unit 200 has a function of a normal processor for executing the instruction supplied from the instruction supply unit 100.

FIG. 2 is a more detailed block diagram of the instruction supply unit 100 in FIG. Hereinafter, the configuration of each block shown in FIG. 2 will be described. The instruction memory 1 stores instructions, and can collectively read, for example, an instruction group 1A including four instructions. In this embodiment, it is assumed that the instruction group 1A can be read in one cycle. The instruction group 1A is supplied to the instruction buffer 6 and the multiplexer 8.

The prefetch counter 2 stores the output 4A of the multiplexer 4 as a read address of the instruction memory 1. The prefetch counter 2 is controlled by a control signal 55 of the control circuit 26. The output address 2A is stored in the instruction memory 1 and the incrementer 3. Given to. Incrementor 3
For updating the prefetch counter 2, the address 2A output from the prefetch counter 2 is input. In this example, the count value is updated by 4 and the output 3A is given to the multiplexer 5.

The multiplexers 4 and 5 select the value of the prefetch counter 2 in the next cycle, and are controlled by control signals 50 and 51 of the control circuit 26, respectively. The multiplexer 5 outputs the output 3A of the incrementer 3
And a branch destination address 14A as an output of the decoder 14 and a generation address 16A of the incrementer 16 as inputs, select one according to the control signal 51, and give its output 5A to the multiplexer 4. The multiplexer 4 receives the output 5A of the multiplexer 5 and the preceding branch destination address 10A which is the output of the preceding decoder 10, selects one according to the control signal 50, and supplies the output 4A to the prefetch counter 2.

The prefetch counter 2, the incrementer 3, and the multiplexers 4 and 5 function as means for generating an address when the instruction is read from the instruction memory 1 in order to decode the instruction in advance. The instruction buffer 6 stores the instruction group 1A read from the instruction memory 1, and is controlled by a control signal 60 of the control circuit 26.
The instruction group 6A output from the instruction buffer 6 is supplied to the multiplexer 8 and the preceding decoder 10.

The multiplexer 8 selects the instruction group 1A read from the instruction memory 1 and the instruction group 6A held and output in the instruction buffer 6, and selects one according to the control signal 52 of the control circuit 26. Then, the instruction group 8A which is the output is given to the multiplexer 9. The multiplexer 9 selects one instruction from an instruction group 8A composed of four instructions selected and output by the multiplexer 8.
According to the control signal 53 of the control circuit 26, any one of the instructions 9A is selected and supplied to the instruction register 13 and sent to the instruction execution unit 200 as an execution instruction 101.

The above-mentioned instruction buffer 6 and multiplexer 8
The multiplexer 9 functions as a unit for temporarily storing an instruction group for pre-decoding the instruction, and a unit for supplying the instruction to the instruction execution unit 200 and the instruction register 13 for executing the instruction. The predecoder 10 decodes the instruction group 6A held and output in the instruction buffer 6, determines a backward branch instruction or a forward branch instruction, and generates the preceding branch destination address 10A. It functions as a leading decoding means for leading decoding. The branch determination result 10B by the preceding decoder 10 is provided to the control circuit 26, and the preceding branch destination address 10A is supplied to the multiplexer 4
Given to.

The instruction register 13 receives an instruction 9A output from the multiplexer 9 and holds an instruction decoded to execute a branch instruction.
Is controlled by the control signal 57. The output 13A of the instruction register 13 is provided to the decoder 14. Decryptor 1
Numeral 4 is used to decode a branch instruction that branches forward or a branch instruction that branches backward. A signal 14B indicating that the instruction is a branch instruction is supplied to the control circuit 26, and at the same time, a branch destination address 14A is generated. , Multiplexers 5 and 18, loop address register 19 and comparator 20 to function as execution decoding means for decoding instructions for execution. Further, the decoder 14 functions as a loop detecting means for detecting a branch instruction and further detecting a backward branch based on the branch destination address, thereby detecting a loop structure of the program. Is the loop start address.

The program counter 15 receives the output 18A of the multiplexer 18 as an input and holds an address corresponding to the instruction held in the instruction register 13, and is controlled by a control signal 56 of the control circuit 26. The address 15A output from the program counter 15 is provided to an incrementer 16. Incrementer 16
Is for updating the program counter 15,
Address 15A output from program counter 15
And the value is updated one by one to generate the address of the next instruction. The generated address 16A is given to the multiplexers 5 and 18.

The multiplexer 18 includes the incrementer 1
6 and the branch destination address 14A output by the decoder 14 are input, and when the branch instruction is decoded by the decoder 14, the branch counter address 14A output by the decoder 14 is selected, whereby the program counter is selected. 15 is updated, and is controlled by the control signal 54 of the control circuit 26. In the case other than the branch instruction, the generation address 16A of the incrementer 16 is selected.

The loop address register 19 functions as a starting position holding means for holding the position of the starting instruction, for example, the address of the starting instruction, or as a loop starting address holding means for extracting and holding the loop starting address. Is controlled by a control signal 58 of the control circuit 26. The loop head address 19A output from the loop address register 19 is supplied to the comparator 20.

The comparator 20 compares the branch destination address of the decoded branch instruction with the loop start address stored so far, and functions as means for detecting the second or subsequent loop. A branch destination address 14A output from the detector 14 and a loop head address 19A output from the loop address register 19 are input. When they match, a match signal 20A is generated and supplied to the control circuit 26.

The history bit stream 21 is transmitted to the control circuit 2
6 is controlled by the control signal 59, and indicates whether a branch instruction existing after the loop start address is taken or not taken.
It has a function of holding a branch result as a 1-bit history. This history bit stream 21 includes an instruction execution unit 2
From 00, the branch determination result 201 is input as a history, and the held history 21A is input to the control circuit 26.
In the present embodiment, a configuration capable of holding a 4-bit history is illustrated. However, the configuration is not limited to 4-bit.
The same operation is performed for bits.

The read pointer 22 indicates a bit position when one bit is read from the history bit stream 21, and obtains a preceding instruction position for obtaining a relative position of the previously decoded instruction with reference to the instruction position held by the starting position holding means. Functions as a means. This preceding instruction position acquiring means is:
More specifically, the number of instructions is obtained by counting instructions determined to be branch instructions by preceding decoding. The output 22A of the read pointer 22 is the history bit stream 21
To the comparator 24. The reset and update of the read pointer 22 are controlled by control signals 61 and 62 of the control circuit 26, respectively.

The write pointer 23 indicates a bit position when one bit is written in the history bit stream 21. An instruction for obtaining a relative position of an instruction decoded for execution with reference to the instruction position held by the starting position holding means. Functions as a position acquisition unit. Specifically, the instruction position obtaining means is a means for obtaining the number of instructions by counting the number of instructions determined to be branch instructions by decoding for execution. The output 23A of the write pointer 23 is provided to the history bit stream 21 and the comparator 24. The reset and update of the write pointer 23 are controlled by control signals 63 and 64 of the control circuit 26, respectively.

The comparator 24 is for detecting that the value of the output 22A of the read pointer 22 matches the value of the output 23A of the write pointer 23. Used to indicate that it does not hold. Here, when the decoded instruction is a branch instruction using the history bit stream 21 and the write pointer 23, the history recording unit records the branch result of the branch instruction as history information corresponding to the relative position of the branch instruction. History reference means for functioning, wherein the history bit stream 21, read pointer 22, and comparator 24 refer to history information corresponding to the relative position of the previously decoded branch instruction when the previously decoded instruction is a branch instruction. Also, it functions as a branch prediction unit that predicts the execution result of the previously decoded branch instruction using the result obtained by referring to the history information. The output 24A of the comparator 24 is input to the control circuit 26.

The state register 25 stores the operation state of branch prediction. The state register 25 receives a control signal 65 of the control circuit 26 as an input and returns an output 25A to the control circuit 26. Take the value of “S0”,
The value of "S1" is taken during storage, and the value of "S2" is taken when branch prediction is performed using the stored history. The control circuit 26 controls the overall operation. As described above, the control circuit 26 determines options of the multiplexers 4, 5, 8, 9, and 18, and stores the instruction buffer 6, the prefetch counter 2, the program counter 15, and the instruction register. 13. The update of the loop address register 19 is controlled, the reading and writing of the history bit stream 21 are controlled, and the reset and update of the read pointer 22 and the write pointer 23 are controlled. Note that the branch determination result 201 is input to the control circuit 26 from the instruction execution unit 200.

The operation of the main components of FIG. 2 in the processor according to the embodiment of the present invention configured as described above will be described. The prefetch counter 2 holds an address at the time of reading an instruction from the instruction memory 1 prior to execution for pre-decoding. Prefetch counter 2
Is incremented by the incrementer 3 to generate the address of the next cycle, and is stored and updated in the prefetch counter 2 in the next cycle via the multiplexers 5 and 4.

The multiplexer 5 decodes the instruction to be executed held in the instruction register 13 by the decoder 14 and detects that the instruction is a branch instruction to be taken. Select The incrementer 16 outputs the address of the instruction next to the instruction to be executed stored in the instruction register 13. When the multiplexer 5 selects this, the branch prediction predicts that the branch is taken, and the prefetch counter 2 This is a path for correcting the prefetch counter 2 when the branch is not taken after the value is changed. Note that the incrementer 3 is a path selected when the instruction is not a branch instruction.

When it is predicted that the branch instruction is pre-decoded by the pre-decoder 10 and the branch is taken, the multiplexer 4 outputs the pre-branch destination address 1 output from the pre-decoder 10.
0A is selected, otherwise multiplexer 5
Output 5A is selected. When a valid instruction group is stored in the instruction buffer 6, the prefetch counter 2 is not updated.

The instruction buffer 6 holds the instruction group read from the instruction memory 1. The held instruction group is decoded by the preceding decoder 10 for each instruction, a branch instruction is detected, and used for predicting the result of the branch. The instruction group held in the instruction buffer 6 is sequentially supplied to the instruction register 13. The instruction buffer 6 reads and holds the next instruction group from the instruction memory 1 as soon as the stored instruction is exhausted. When it is detected that the instruction held in the instruction register 13 is a branch instruction, and the branch is determined as a result of the branch determination output from the instruction execution unit 200, the instruction group held in the instruction buffer 6 is invalidated. You. Similarly, the leading decoder 1
If the branch instruction is predicted to be taken at 0,
The instruction buffer 6 is invalidated.

Here, the validity and invalidity of the contents of the instruction buffer 6 will be described. The instruction buffer 6 prefetches and holds the instruction group, but there are cases where the prefetched instruction group is invalid as a result, for example, when a branch prediction is missed. It is valid when the prefetched instruction group is used in the future. The multiplexer 8 selects an instruction group including an instruction to be executed next from the respective outputs of the instruction memory 1 and the instruction buffer 6. When the instruction buffer 6 is invalid, it is not selected. The multiplexer 9 selects an instruction to be executed next from the instruction group selected by the multiplexer 8. The instruction group includes four instructions, and one of the instructions is selected using the lower two bits of the value of the next cycle stored in the program counter 15.

The instruction stored in the instruction register 13 is decoded by the decoder 14 and a branch instruction (For
signal indicating that the instruction is a “ward branch”, and a branch instruction (backward branch) for branching backward.
h) and a branch destination address are generated. The branch destination address is valid only when a forward branch or a backward branch is indicated.

The address of the instruction stored in the instruction register 13 is stored in the program counter 15. The value “1” is added by the incrementer 16, and becomes the address of the next instruction via the multiplexer 18. . The multiplexer 18 selects a branch destination address when the instruction decoded by the decoder 14 is a branch instruction and the branch determination result output from the instruction execution unit 200 indicates that the branch is taken, and selects the branch destination address in the next cycle. The address is stored in the program counter 15 and output to the instruction execution unit 200 at the same time as the address 102 of the execution instruction. The instruction execution unit 200 uses the address of the execution instruction to execute an instruction that requires an instruction address, such as a subroutine call instruction.

The control circuit 26 includes a signal indicating that the instruction is a backward branch instruction or a forward branch instruction, a branch determination result output from the instruction execution unit 200, a detection result of a previously decoded branch instruction, an operation state of the status register 25, and a history. From the branch history output from the bit stream 21, various control signals and the operation state of the operation register 25 in the next cycle are generated, but control is also performed as a control circuit of an instruction supply unit of a normal processor.

The operation state of the status register 25 is "S0" before the loop head address is detected. S1 ". When the operation state is "S1", the backward branch instruction is detected again, and the branch destination address and the loop address register 19 are detected.
Are matched (that is, when the same loop is detected), "S2" is reached.

When the status register 25 is "S0", the contents of the loop address register 19 are invalid. If the backward branch instruction is detected by the decoder 14 when the operation state is "S0", the branch destination address 14A is stored in the next cycle. This is the start address of the loop, that is, the starting position. When the status register 25 is "S1" or "S2", the backward branch instruction is detected and the branch destination address 14A is detected.
If the contents of the loop address register 19 match the contents of the loop address register 19, the loop address register 19 does not change. If the branch destination address does not match the contents of the loop address register 19 in any operation state, a new branch destination address is stored in the loop address register 19, and the state register 25 becomes "S1". This is when another loop is detected. When the backward branch is detected and the branch is not taken, the status register becomes “S0”,
The loop address register 19 is invalidated.

The write pointer 23 is incremented after the branch result obtained from the instruction execution unit 200 is stored in the bit position indicated by the write pointer 23, and the read pointer 22 is read from the read pointer 22 of the history bit stream 21 for branch prediction. It is incremented after the branch result stored at the indicated bit position is referred to. However, when the comparator 24 detects that the value of the read pointer 22 is equal to or larger than the value of the write pointer 23, the read pointer 22 is not incremented. When the operation state of the status register 25 is "S"
When the value changes from "0" to "S1", it is reset to 0. The read pointer 22 is stored in the loop address register 19.
Is reset to "0" when it is detected that the branch address generated by the decoder 14 is equal to the branch address.

When the decoder 14 detects a forward branch instruction when the status register 25 is "S1", the branch bit output from the instruction execution unit 200 is output to the bit position indicated by the value of the write pointer 23. Write the result. Thereafter, the write pointer 23 is incremented. By repeating this, the result of the forward branch instruction is sequentially written from bit position 0 (leftmost bit) of the history bit stream 21. Status register 2
When 5 is "S2", when the preceding decoder 10 detects that the next instruction to be executed is a forward branch instruction, the preceding decoder 10 refers to the branch result at the bit position indicated by the value of the read pointer 22, and performs branch prediction. Used for For example, if the previous branch has been taken, it can be predicted that the current branch will be taken, or if the previous branch has not been taken, it can be predicted that this branch will not be taken again. However,
If the comparator 24 detects that the value of the read pointer 22 is equal to or larger than the value of the write pointer 23, no prediction is performed. This is because a valid history is not stored in a bit position having a value larger than the value of the write pointer 23.

FIG. 5 conceptually shows the loop start address and the result information of the first, second, third, and fourth branch instructions from the top of the loop, similarly to FIG. Each part operates as described above. Hereinafter, the flow of the entire operation will be described using a time chart shown in FIG. 3 and a program example shown in FIG.

FIG. 4 shows a program stored in the instruction memory 1. FIG. 3 is a time chart when the program of FIG. 4 is sequentially executed from address 0, and shows the value of each signal in each of the cycles C0 to C19. In FIG. 4, "beq TA" is a conditional branch instruction, and TA
Is a branch destination address. “Inst0”, “inst
"2", "inst4", and "inst20" are instructions other than branch instructions and are executed by the instruction execution unit 200. The program in FIG. In this example, the branch instruction at address 1 is a branch not taken at a forward branch, the branch instruction at address 3 is a branch taken at a front branch, and the branch instruction at address 21 is a branch taken at a backward branch.

Here, in the present embodiment, the branch prediction of the backward branch is performed by the static branch prediction, and it is predicted that the branch is always taken. It is stated that the branch prediction of the present invention operates only on the forward branch instruction. The operation will be described with reference to FIG. For simplicity of description, it is assumed that cycle C0 in FIG. 3 is the last cycle of the first processing of the loop processing of the program in FIG. 4, and cycle C1 is the first cycle of the second processing. That is, in the cycle C0, the branch instruction is executed at the end of the loop, and at the same time, the leading address of the loop obtained by the preceding decoding is stored in the prefetch counter 2.

Cycle C0: The instruction register 13 stores the last instruction of the loop, ie, the instruction "beq0" at address 21, and the decoder 14 generates a signal indicating a backward branch instruction and a branch destination address. The prefetch counter 2 is at address 0, which is a branch destination, and reads an instruction group corresponding to address 0 from the instruction memory 1. This instruction group includes instructions at addresses 0 to 3.
Hereinafter, the description is abbreviated as in instruction groups 0 to 3.

Cycle C1: The state register 25 is set to "S1" because the backward branch instruction detection of the decoder 14 and the branch determination result of the instruction execution unit 200 indicate that the branch is taken. As a result, the branch address is stored in the loop address register 19, and the write pointer 23 is reset to "0". The instruction groups 0 to 3 read from the instruction memory 1 are stored in the instruction buffer 6, and the instruction corresponding to the address 0 (hereinafter, abbreviated as the instruction 0).
“Inst0” is stored in the instruction register 13 and sent to the instruction execution unit 200 at the same time. After the value of the prefetch counter 2 is added with “4” by the incrementer 3, the value is stored in the prefetch counter 2 via the multiplexers 5 and 4. The preceding decoder 10 decodes the instruction 1 to be executed next to the instruction being executed, that is, the instruction at address 1 in advance, and determines whether the instruction is a branch instruction. Here, it is determined that the instruction is a forward branch instruction.
Is "S1", no branch prediction is performed. This is the same operation as predicting that a branch is not taken. In this case, the information decoded earlier is ignored.

Cycle C2: Instruction 1 in instruction register 13
That is, “beq 10” is stored, and the decoder 14 determines a branch instruction. Since instruction 1 is a branch instruction to address 10, that is, a forward branch instruction,
4 outputs the branch destination address 10. The instruction 1 is also transferred to the instruction execution unit 200, and the instruction execution unit 200 outputs a branch determination result. In this case, the instruction execution unit 200 outputs a branch not taken.

Cycle C3: The status register 25 sets "S
1 ”, the branch determination result output from the instruction execution unit 200 is the write pointer 23 of the history bit stream 21.
Is written to the bit position indicated by. Here, since the write pointer 23 is “0”, “0” indicating that the branch is not taken is written in the position of bit 0, that is, the leftmost position. x represents an indefinite value. Thereafter, the value of the write pointer 23 is incremented to "1".

The instruction register 13 stores the instruction 2, ie,
“Inst2” is stored and transferred to the instruction execution unit 200. The preceding decoder 10 decodes the next instruction in advance and determines whether or not the instruction is a branch instruction. Here, it is determined that the instruction is a forward branch instruction.
Since it is 1 ", branch prediction is not performed. This is the same operation as predicting that a branch is not taken. In this case, information decoded in advance is ignored.

Cycle C4: Instruction 3 in instruction register 13
That is, “beq 20” is stored, and the decoder 14 determines the branch instruction. Since instruction 3 is a branch instruction to address 20, that is, a forward branch instruction,
4 outputs the branch destination address 20. The instruction 3 is also transferred to the instruction execution unit 200, and the instruction execution unit 200 outputs a branch determination result. In this case, the instruction execution unit 200 outputs a branch taken.

Cycle C5: The status register 25 sets "S
Since it is "1", the branch determination result is written into the bit position indicated by the write pointer 23 of the history bit stream 21. Here, the value of the write pointer 23 is "1".
Therefore, "1" indicating that the branch is taken is written at the position of bit 1, that is, the second position from the left. Thereafter, the value of the write pointer 23 is incremented to “2”.

Although the branch is taken in cycle C4, no instruction has been executed in this cycle since the reading of the instruction at the branch destination from the instruction memory 1 has not been completed. The prefetch counter 2 stores the branch destination address 20 selected by the multiplexer 5 and is used for reading an instruction from the instruction memory 1. Cycle C5 is a penalty cycle caused by the branch taken by the forward branch instruction at address 3. If the branch is not taken by the forward branch instruction, no penalty occurs because the prefetched subsequent instruction is valid, but if the branch is taken, the subsequent instruction is invalid,
The instruction cannot be executed until a valid instruction is read from the instruction memory 1 using the branch destination address. This penalty cycle degrades the performance of the processor.

Cycle C6: The instruction 20 stores the instruction 20 in the instruction register 13. The leading decoder 10 decodes the instruction 21 and finds that it is a backward branch instruction. In the case of a backward branch instruction, it is predicted that the branch will be fixedly performed by hardware. Therefore, the preceding decoder 10 outputs the address 0, which is the branch destination address, and sends it to the prefetch counter 2 via the multiplexer 4.

Cycle C7: The address 0 is stored in the prefetch counter 2 and the instruction at the address 21 is stored in the instruction register 13 and executed. Decryptor 14
, The branch destination address and the value of the loop address register 19 are compared with each other by the comparator 20.
Are compared. As a result of the comparison, if they match, it is determined that the same loop as the previous time is executed. In that case, the status register 25 is set to “S2” and the read pointer 22 is set to “0”. The branch execution is output from the instruction execution unit 200 as a branch determination result, and the branch is executed.

Cycle C8: The branch destination address 0 obtained in cycle C7 is stored in the program counter 15. On the other hand, the instruction register 13 stores the instruction 0 read from the instruction memory 1 in cycle C7. Here, the penalty cycle of the branch instruction does not occur because of the branch prediction of the backward branch instruction.

Since the status register 25 is "S2",
The pre-decoder 10 pre-decodes the next instruction, instruction 1. As a result of the preceding decoding, it is found that the instruction is "beq 10", that is, a forward branch instruction. Therefore, the value of the bit position of the value of the read pointer 22 of the history bit stream 21 is referred to. In the case of, it is predicted that the branch is taken. In this case, since the value of the read pointer 22 is “0”, bit 0, that is, the leftmost bit is referred to. Since the value of the leftmost bit is “0”, it is predicted that the branch is not taken. When the branch prediction is not taken, the same operation as when there is no branch instruction is performed. The read pointer 22 is incremented to "1".

Cycle C 9: Instruction 1, that is, “beq 10” is stored in the instruction register 13,
Is used to determine the branch instruction. Since the instruction 1 is a branch instruction to the address 10, that is, a forward branch instruction, the decoder 14 outputs the branch destination address 10. The instruction 1 is also transferred to the instruction execution unit 200, and the instruction execution unit 200 outputs a branch determination result. In this case, the failure is output.

Cycle C 10: The instruction 2, ie, “inst 2”, is stored in the instruction register 13 and transferred to the instruction execution unit 200. The pre-decoder 10 pre-decodes the instruction 3 and determines whether it is a branch instruction. Here, it is determined that the instruction is a forward branch instruction, that is, “beq 20”, and since the status register 25 is “S2”, branch prediction is performed. That is, the value of the bit position of the value of the read pointer 22 of the history bit stream 21 is referred to. In this case, since the value of the read pointer 22 is “1”, bit 1, that is, the second bit from the left is referred to. Since the value referred to is "1", it is predicted that the branch is taken. Thus, the prefetch counter 2 stores the branch destination address output by the preceding decoder 10, that is, the address 20. The read pointer 22 is incremented to “2”.

Cycle C11: The instruction register 13 stores the instruction 3, ie, “beq 20”,
At step 4, the branch destination address 20 of the branch instruction is output. The instruction 1 is also sent to the instruction execution unit 200, and the instruction execution unit 200 outputs a branch determination result. In this case, a branch taken is output.

Cycle C12: In this cycle, a penalty should occur because the branch is taken by the forward branch instruction of cycle C11. However, no penalty occurs because the branch prediction of the present invention is performed in cycle C11. The address 20 is stored in the program counter 15, and the instruction at the address 20 is stored in the instruction register 13. The instruction groups 20 to 23 at the address 20 are predicted to be taken in the cycle C10, and are read from the instruction memory 1 in advance in the cycle C11. The instruction buffer 6 stores instruction groups 20 to 23, and the preceding decoder 10
Can be decoded in advance, and the decoding indicates that it is a backward branch instruction. In the case of a backward branch, the branch is always predicted to be taken. Therefore, the prefetch counter 2 stores the branch destination address output from the preceding decoder 10, that is, the address 0.

Cycle C13: Prefetch counter 2
And the instruction register 13
The instruction at the address 21 is stored and executed. Decryptor 1
4, when it is detected that the instruction is a backward branch instruction, the branch destination address and the value of the loop address register 19 are compared with each other by the comparator 20.
And confirm that the same loop is executed by matching the two. In this case, the status register 25 is set to “S2”, and the read pointer 22 is set to “0”. The branch execution is output from the instruction execution unit 200 as a branch determination result, and the branch is executed.

After the cycle C14, the cycles C8 to C13 are repeated until the loop ends. In the above, the state register 25 state of "S1", in other words the cycle C1 to C7, met-branch instruction FuNaru
A first step of recording the branching result indicating standing as history information corresponding to the relative position from the starting point is executed. Further, when the state of the state register 25 is "S2", that is, in each cycle C8 and thereafter, the history information is referred to based on the relative position of the preceding decoded instruction from the starting point at the time of preceding decoding before execution of the next branch instruction. Thus, the second step of predicting the branch result of the next branch instruction is executed. The first means executes the first step, and the second means executes the second step.
Means.

Although the operation in the case where the branch prediction is successful has been described above, the prediction may actually be incorrect.
The operation when the branch prediction is incorrect will be described below. (1) In the case where the branch prediction is not taken and the branch is taken When the branch prediction is not taken, the operation is the same as the case where the preceding decoder 10 does not detect the branch instruction. Does not perform read operation. Thereafter, when the instruction execution unit 200 determines that the branch has been taken, the instruction memory 1 is read therefrom.
In that case, a one-cycle penalty will occur. (2) When the branch prediction is taken and the branch is not taken When the branch prediction is taken, the branch destination address output by the preceding decoder 10 is stored in the prefetch counter 2,
An instruction is read from the instruction memory 1 in advance. Thereafter, when the instruction execution unit 200 determines that the branch is not taken, the next address (output of the incrementer 16) of the current instruction (branch instruction) stored in the program counter 15 passes through the multiplexers 5 and 4 to the prefetch counter. 2 and the instruction following the branch instruction is read from the instruction memory 1. In that case, a one-cycle penalty will occur.

If the branch is not taken (end of the loop) after the detection of the backward branch, the status register 25 is set to "S0". Further, when the backward branch instruction is executed, the branch destination address and the loop address register 19 are stored in the comparator 20.
Are compared, and if they do not match, the status register 25 is set to “S1”. This is an operation when a different loop is detected during a loop. For such a case, a set of a plurality of loop address registers 19, a history bit stream 59, a read pointer 22, a write pointer 23, a comparator 20, and a comparator 24 is provided, and a loop address register 19 corresponding to a branch destination address is provided. When the branch prediction corresponding to each loop is performed by using the history bit stream 59, the read pointer 22, the write pointer 23, the comparator 20, and the comparator 24 of the same set, the prediction accuracy rate in the present invention is increased. Can be.

As described above, according to the embodiment of the present invention, a branch result indicating whether a branch instruction has been taken or not has been recorded as history information corresponding to the number of executed branch instructions from the loop top address. At the time of execution of a branch instruction, the branch result is predicted by referring to the history information based on the number of previously decoded branch instructions from the starting point. The branch result of a plurality of branch instructions can be predicted only by the loop start address and the history bit stream. Since the amount of information for holding the bit stream is small, the memory capacity for holding the branch prediction information can be made smaller than before. Also, the address is held for each branch instruction as in the past,
Since there is no need to search for a corresponding branch instruction each time a branch instruction appears, a search circuit is not required, and the circuit scale can be reduced. It also leads to lower power consumption.

For example, in a conventional processor that performs branch prediction, a 32-bit address and a 1-bit history bit form one entry as 512 entries or 10
24 storage elements are required. In the case of 512 entries, (32 + 1) × 512, that is, a storage element on the order of 33 times 512 is required. On the other hand, in the present invention, an address corresponding to each history bit is not required, so that one bit per entry is sufficient. However, a storage element for holding the starting address and a storage element for realizing the read pointer and the write pointer are required. When the address is 32 bits and the read pointer and the write pointer handle 512 history bits, each requires 9 bits. Therefore, in the case of 512 entries, (0 + 1) × 512 + (32 + 9 + 9), that is, a storage element of at most twice the order of 512 is sufficient.

In the search circuit, a conventional processor for performing branch prediction searches a 512-bit 32-bit address for an address that matches the address of a previously decoded branch instruction at high speed. Although 512 comparators are required, in the present invention, the comparator 20 (32
Since only the bit comparator) and the comparator 24 (9-bit comparator) are required, the circuit scale can be significantly reduced.

In the embodiment of the present invention, the branch result holds the first branch result of the loop and is used for branch prediction of the remaining loops, but the history is updated with the result of the branch in each loop. Alternatively, the prediction may be performed based on the result of the previous branch. Although the history information of the branch result is represented by one bit, the history information is composed of two bits or more, and the history information is such that the branch prediction is performed using the results of two or more past branches of the same branch instruction. May be better. That is, a plurality of pieces of history information may be used, and branch prediction may be performed based on the plurality of pieces of history information. In this case, for example, if the past two times are taken, the branch is predicted to be taken this time, and if the past two times are taken and the branch is not taken, it is considered that the taking and the taking are alternately repeated. This time, it may be predicted that the branch is taken.

Further, when the branch prediction is deviated, the subsequent branch prediction may not be performed, and in the case of deviated, the accuracy can be improved by having another history bit stream. In the embodiment of the present invention, the number of forward branch instructions is counted, and the number of branch instructions is used as an index.
The same effect can be obtained with any number of instructions.

As shown in the conceptual diagram of FIG. 6, the same effect can be obtained by holding the address difference from the loop start address and searching for the address difference. In other words, when the difference between addresses is held, for example, in a 32-bit address program, if the configuration size of the loop is regarded as a maximum of 255, the number of bits for holding the difference (relative address value) may be 8 bits, and This is because only one-fourth of the case where a typical address is held is required. In this case, the instruction position obtaining means comprises means for obtaining a difference between the address of the decoded instruction for execution and the address held by the starting position holding means, and the preceding instruction position obtaining means accordingly A means for obtaining a difference between the address of the decoded instruction and the address held by the starting position holding means.

Further, not only one path but also a plurality of paths as histories can improve accuracy.
(History bit stream of tree structure) After prediction, the execution result can be fed back to further improve accuracy. Here, a history bit stream having a tree structure will be described. The bit stream referred to here indicates a flow resulting from the branch. For example, in a 4-bit stream, ○ indicates that the branch is taken and X indicates that the branch is not taken. When prediction is performed on this stream, the branch is taken first and the branch is not taken next. At this time, it is assumed that the first branch is not taken. Then,
The history of subsequent branches is much less reliable. Because the branch was not taken, the instruction flow changed,
The branch instructions that apply may also be different. Therefore, we have a bit stream as follows. (1) shows the same flow as above. (2) is (1)
2 shows an alternative stream when the prediction of the first branch instruction is incorrect. Hereinafter, (3) and (4) show alternative streams when prediction is further deviated, respectively. This structure is a tree structure.

Although the number of branch instructions is counted and the number of branch instructions is used as an index, the same effect can be obtained by using the number of bytes from the loop start address. Further, in the above embodiment, the number of branch instructions is counted. However, the number of all instructions to be executed is counted, and the value is used as an index, and the branch instruction is located at a position corresponding to the branch instruction. May be stored. In this case, the instruction position obtaining means comprises means for counting the number of instructions decoded for execution to obtain the number of instructions. In response to this, the preceding instruction position obtaining means counts the number of instructions decoded before and counts the number of instructions. Means to obtain.

In the above embodiment, the starting point is the start address of the loop. However, the present invention is not limited to the loop. For example, the program may be divided into program blocks having a size of 64 bytes, and the start address of the program block may be used as the starting position. in this case,
The starting position holding means comprises a block head address detecting means for detecting a head address of a program block, and a block head address holding means for holding an address detected by the block head address detecting means.

A branch prediction method performed by the branch prediction device in the processor described above will be described with reference to the flowchart of FIG. This branch prediction method includes a first step of recording, as history information , a branch result indicating whether a branch instruction has been taken or not , corresponding to a relative position from the starting point, A second step of predicting the branch result of the next branch instruction by referring to the history information based on the relative position of the preceding decoding instruction. The first step is executed when the state of the state register 25 is “S1” in the time chart of FIG. 3, that is, in cycles C1 to C7. The second step is executed when the state of the state register 25 is “S2” in FIG.

In this case, the above-mentioned first step corresponds to FIG.
As shown in the figure, a start position holding step ST1 for holding the position of the start instruction, an execution decoding step ST2 for decoding the instruction for execution, and an execution position based on the instruction position held in the start position holding step. An instruction position obtaining step ST3 for obtaining a relative position of the decoded instruction; and a history recording step of recording the branch result of the branch instruction as history information corresponding to the relative position of the branch instruction when the decoded instruction is a branch instruction. ST4. The starting position holding step ST1 is executed by the starting position holding means, the execution decoding step ST2 is executed by the execution decoding means, and the instruction position obtaining step ST3 is executed by the instruction position obtaining means. Yes, history recording step ST
4 is executed by the history recording means.

As shown in the figure, the second step is a preceding decoding step ST5 for precedingly decoding the instruction before the next execution of the instruction, and a preceding decoding step based on the instruction position held in the starting position holding step. A preceding instruction position obtaining step ST6 for obtaining a relative position of the decoded instruction; a history reference step ST7 for referring to history information corresponding to the relative position of the previously decoded branch instruction when the previously decoded instruction is a branch instruction; A prediction step ST8 for predicting the execution result of the previously decoded branch instruction using the result obtained by referring to the history information. The preceding decoding step ST5 is executed by the preceding decoding means, and the preceding instruction position acquiring step S5 is performed.
T6 is executed by the preceding instruction position obtaining means, the history reference step ST7 is executed by the history reference means, and the prediction step ST8 is executed by the branch prediction means.

Further, the starting position holding step ST1 described above.
Consists of, for example, a step of holding an address of an instruction of a starting point to be executed. More specifically, the starting position holding step ST1 extracts and holds the address of the first instruction of the loop based on, for example, a loop detection step for detecting the loop structure of the program and the loop structure of the program detected by the loop detection step. It consists of steps. The above-described loop detecting step includes a step of detecting a loop structure of a program by decoding a branch instruction that branches backward, for example.

The starting position holding step ST1 includes, for example, a block head address detecting step for detecting the head address of the program block and a block head address holding step for holding the address detected in the block head address detecting step. In some cases. The instruction position obtaining step ST3 includes, for example, counting the number of instructions decoded for execution to obtain the number of instructions.
No. 6 comprises a step of counting instructions decoded earlier to obtain the number of instructions.

The instruction position obtaining step ST3 further comprises a step of counting the number of instructions which are determined to be branch instructions by decoding for execution to obtain the number of instructions. Acquisition step ST6
However, there may be a case where the number of instructions is obtained by counting instructions determined to be branch instructions by preceding decoding.
Further, the instruction position obtaining step ST3 further comprises a step of obtaining a difference between the address of the decoded instruction for execution and the address held by the starting position holding step, for example. S
In some cases, T6 includes a step of obtaining a difference between the address of the previously decoded instruction and the address held in the starting position holding step.

The history recording step ST4 may be a step of recording a plurality of histories. According to the above-described branch prediction method, history information is recorded corresponding to the relative position from the start point , indicating whether the branch instruction is taken or not, and the next branch instruction is executed at the next execution of the branch instruction. Since the branch result of the branch instruction is predicted by referring to the history information based on the relative position of the preceding decoding instruction, the starting point information, the relative position information, and the history are used as the branch prediction information necessary for performing the branch prediction. The branch result of a plurality of branch instructions can be predicted using only the information, and the starting point information and the relative position information for each branch instruction are compared with the information amount of the conventional example in which the absolute address and the history information are retained for each branch instruction Further, since the amount of information when holding the history information is small, the memory capacity for holding the branch prediction information can be reduced as compared with the related art.

Conventionally, an address is held for each branch instruction, and a search is made for a corresponding branch instruction every time a branch instruction appears. In order to compare the address of a branch instruction with all the held addresses, However, according to the branch prediction method of the present invention, the relative position information (for example, relative address value) has a smaller amount of information than the address information. Can be reduced, and the circuit scale of the search circuit can be reduced. It also leads to lower power consumption.

[0093]

According to the branch prediction method of the present invention, a branch result indicating whether a branch instruction has been taken or not is recorded as history information corresponding to a relative position from the starting point, and the branch result is recorded from the starting point at the next execution of the branch instruction. The prediction result of the branch instruction is predicted by referring to the history information based on the relative position of the preceding decoding instruction of the starting instruction, so that the information of the starting point and the relative position information are used as the branch prediction information necessary for performing the branch prediction. The branch result of a plurality of branch instructions can be predicted using only the history information. Since the amount of information when storing information and history information is small, the memory capacity for storing branch prediction information can be reduced as compared with the related art.

Conventionally, the address is held for each branch instruction, and each time a branch instruction appears, the corresponding branch instruction is searched. In order to compare the address of the branch instruction with all the held addresses, However, according to the branch prediction method of the present invention, the relative position information (for example, relative address value) has a smaller amount of information than the address information. Can be reduced, and the circuit scale of the search circuit can be reduced. It also leads to lower power consumption.

According to the processor of the present invention, the branch instruction
The branch result indicating whether the branch was taken or not is recorded as history information corresponding to the relative position from the start point, and the next branch instruction is executed by referring to the history information based on the relative position of the preceding decoding instruction from the start point when the next branch instruction is executed. Means for predicting a branch result of a plurality of branch instructions, the branch result of a plurality of branch instructions can be predicted using only the information of the starting point, the relative position information, and the history information as the branch prediction information necessary for performing the branch prediction. Compared to the information amount in the conventional example in which the absolute address and the history information are stored for each instruction, the information amount in the case of holding the relative position information and the history information for each of the starting point information and the branch instruction is small, so that the branching is performed. The memory capacity for holding the prediction information can be made smaller than before.

Conventionally, a configuration is provided in which the address is held for each branch instruction, and means for searching for the corresponding branch instruction each time the branch instruction appears is used. Although a search circuit having a plurality of comparators for comparison is required, according to the processor of the present invention, relative position information (for example, relative address value)
Since the information amount is smaller than the address information, the size of the comparator can be reduced, and the circuit size of the search circuit can be reduced. It also leads to lower power consumption.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a processor according to an embodiment of the present invention.

FIG. 2 is a block diagram illustrating a configuration of an instruction supply unit of the processor according to the embodiment of the present invention.

FIG. 3 is a time chart illustrating an operation of an instruction supply unit of the processor according to the embodiment of the present invention.

FIG. 4 is a schematic diagram showing an example of a program for explaining the operation of the embodiment of the present invention.

FIG. 5 is a conceptual diagram of dynamic branch prediction according to the present invention.

FIG. 6 is a conceptual diagram of dynamic branch prediction according to the present invention.

FIG. 7 is a flowchart showing a branch prediction method according to the embodiment of the present invention.

FIG. 8 is a conceptual diagram of conventional dynamic branch prediction.

[Explanation of symbols]

 REFERENCE SIGNS LIST 100 instruction supply unit 101 instruction 102 address 200 instruction execution unit 201 branch determination result 1 instruction memory 1A instruction group 2 prefetch counter 3 incrementer 4 multiplexer 5 multiplexer 6 instruction buffer 8 multiplexer 9 multiplexer 10 predecoder 13 instruction register 14 decipherer 15 Program counter 16 incrementer 18 multiplexer 19 loop address register 20 comparator 21 history bit stream 22 read pointer 23 write pointer 24 comparator 25 status register 26 control circuit

Continuation of the front page (56) References JP-A-5-143334 (JP, A) JP-A-1-142294 (JP, A) JP-A-6-89173 (JP, A) JP-A-3-147133 (JP) , A) JP-A-8-234980 (JP, A) Tetsuya Hara, 3 others "Instruction supply mechanism of super scalar processor" Shinkaze "based on SIMP (single instruction flow / multiple instruction pipeline) method" IPSJ Research Report, Vol. 90, No. 7 (90-ARC-80), 80-7, January 25, 1990, pp. 49-56 (58) (Int.Cl. ⁶ , DB name) G06F 9/38

Claims (12)

(57) [Claims] A first step of recording as a history information a branch result indicating whether a branch instruction has been taken or not, corresponding to a relative position from the starting point; A second step of predicting a branch result of the next branch instruction by referring to the history information based on a relative position of the preceding decoding instruction , wherein the first step holds a position of an instruction at a starting point. Ki
A point holding step and the actual decoding of the instruction for execution.
Row deciphering step and the starting position holding step
Of instructions decoded for execution based on the instruction position
Instruction position acquisition step to obtain pair position and decoded instruction
If the instruction is a branch instruction, the result of the branch instruction is executed.
Recorded as history information corresponding to the relative position of the branch instruction.
And a history recording step of recording the instruction.
A preceding decoding step for line decoding, and the starting position holding step.
Instructions decoded earlier based on the instruction position held in the map
Preceding instruction position obtaining step for obtaining the relative position of
If the read instruction is a branch instruction,
Refer to the history information corresponding to the relative position of the
A history reference step, and a result obtained by referring to the history information.
To predict the execution result of the previously decoded branch instruction
A prediction step, wherein the starting position holding step is a loop structure of the program.
Detecting a loop, and detecting the loop.
Loop based on the loop structure of the program detected by
Extracting and holding the address of the first instruction of the loop
A branch prediction method characterized by comprising : 2. The loop detecting step branches backward.
Loop by decoding the branch instruction
Claims comprising the step of detecting a structure.
Item 2. The branch prediction method according to Item 1. 3. A branch result indicating whether a branch instruction is taken or not taken.
Is recorded as history information corresponding to the relative position from the starting point.
First step and preceding solution before execution of next branch instruction
When reading, based on the relative position of the preceding decoding instruction from the starting point,
Predicts the branch result of the next branch instruction with reference to history information
A second step of holding the position of the instruction at the starting point.
A point holding step and the actual decoding of the instruction for execution.
Row deciphering step and the starting position holding step
Of instructions decoded for execution based on the instruction position
Instruction position acquisition step to obtain pair position and decoded instruction
If the instruction is a branch instruction, the result of the branch instruction is executed.
Recorded as history information corresponding to the relative position of the branch instruction.
And a history recording step of recording the instruction.
A preceding decoding step for line decoding, and the starting position holding step.
Instructions decoded earlier based on the instruction position held in the map
Preceding instruction position obtaining step for obtaining the relative position of
If the read instruction is a branch instruction,
Refer to the history information corresponding to the relative position of the
A history reference step, and a result obtained by referring to the history information.
To predict the execution result of the previously decoded branch instruction
A starting step , wherein the starting position holding step includes
Block start address detection step for detecting the start address
In the block start address detection step.
Block start address holding stage that holds the
And a branch prediction method. 4. A branch result indicating whether a branch instruction is taken or not taken.
Is recorded as history information corresponding to the relative position from the starting point.
First step and preceding solution before execution of next branch instruction
When reading, based on the relative position of the preceding decoding instruction from the starting point,
Predicts the branch result of the next branch instruction with reference to history information
A second step of holding the position of the instruction at the starting point.
A point holding step and the actual decoding of the instruction for execution.
Row deciphering step and the starting position holding step
Of instructions decoded for execution based on the instruction position
Instruction position acquisition step to obtain pair position and decoded instruction
If the instruction is a branch instruction, the result of the branch instruction is executed.
Recorded as history information corresponding to the relative position of the branch instruction.
And a history recording step of recording the instruction.
A preceding decoding step for line decoding, and the starting position holding step.
Instructions decoded earlier based on the instruction position held in the map
Preceding instruction position obtaining step for obtaining the relative position of
If the read instruction is a branch instruction,
To refer to the history information corresponding to the relative position of the branch instruction
A history reference step, and a result obtained by referring to the history information.
To predict the execution result of the previously decoded branch instruction
A prediction step, wherein the instruction position obtaining step decodes the instruction for execution.
Counting the number of instructions to obtain the number of instructions.
The instruction position acquisition step counts instructions decoded earlier and issues instructions.
Branch prediction characterized by the step of obtaining an instruction number
Method. 5. A branch result indicating whether a branch instruction is taken or not taken.
Is recorded as history information corresponding to the relative position from the starting point.
First step and preceding solution before execution of next branch instruction
When reading, based on the relative position of the preceding decoding instruction from the starting point,
Predicts the branch result of the next branch instruction with reference to history information
A second step of holding the position of the instruction at the starting point.
A point holding step and the actual decoding of the instruction for execution.
Row deciphering step and the starting position holding step
Of instructions decoded for execution based on the instruction position
Instruction position acquisition step to obtain pair position and decoded instruction
If the instruction is a branch instruction, the result of the branch instruction is executed.
Recorded as history information corresponding to the relative position of the branch instruction.
And a history recording step of recording the instruction.
A preceding decoding step for line decoding, and the starting position holding step.
Instructions decoded earlier based on the instruction position held in the map
Preceding instruction position obtaining step for obtaining the relative position of
If the read instruction is a branch instruction,
Refer to the history information corresponding to the relative position of the
A history reference step, and a result obtained by referring to the history information.
To predict the execution result of the previously decoded branch instruction
A prediction step, wherein the instruction position acquisition step is performed by decoding for execution.
Count instructions found to be branch instructions and count
Obtaining the preceding instruction position.
Is an instruction that was found to be a branch instruction by preceding decoding
Counting the number of instructions to obtain the number of instructions.
Branch prediction method. 6. A branch result indicating whether a branch instruction is taken or not taken.
Is recorded as history information corresponding to the relative position from the starting point.
First step and preceding solution before execution of next branch instruction
When reading, based on the relative position of the preceding decoding instruction from the starting point,
Predicts the branch result of the next branch instruction with reference to history information
A second step of holding the position of the instruction at the starting point.
A point holding step and the actual decoding of the instruction for execution.
Row deciphering step and the starting position holding step
Of instructions decoded for execution based on the instruction position
Instruction position acquisition step to obtain pair position and decoded instruction
If the instruction is a branch instruction, the result of the branch instruction is executed.
Recorded as history information corresponding to the relative position of the branch instruction.
And a history recording step of recording the instruction.
A preceding decoding step for line decoding, and the starting position holding step.
Instructions decoded earlier based on the instruction position held in the map
Preceding instruction position obtaining step for obtaining the relative position of
If the read instruction is a branch instruction,
Refer to the history information corresponding to the relative position of the
A history reference step, and a result obtained by referring to the history information.
To predict the execution result of the previously decoded branch instruction
A predicting step, wherein the instruction position obtaining step includes the step of obtaining a decoded instruction for execution.
Command address and the starting position holding step.
Obtaining a difference from the specified address.
The line instruction position acquisition step determines the address of the previously decoded instruction.
Address and the address held in the starting position holding step.
A step of obtaining a difference from the
Forecasting method. 7. A branch result indicating whether a branch instruction is taken or not taken.
Is recorded as history information corresponding to the relative position from the starting point.
First means, and preceding decoding before execution of the next branch instruction
The history information based on the relative position of the preceding decoding instruction from the origin.
The branch result of the next branch instruction with reference to the report
Second means, wherein the first means retains the position of the starting instruction.
Holding means and an execution interpreter for decoding instructions for execution
And the command position held by the starting position holding means.
Instruction to get relative position of instruction decoded for execution as
When the position acquisition means and the decoded instruction are branch instructions
The branch result of the branch instruction as history information;
History recording means for recording corresponding to the relative position of the instruction;
Made, the second means, the prior solution of the instruction before execution of the next instruction
Reading means for reading and holding by the starting position holding means.
And the instruction position relative location of the instruction that preceded decrypt the basis of
Preceding instruction position acquisition means to obtain and precedently decoded instruction branch
If it is an instruction, the relative value of the previously decoded branch instruction
History reference means for referring to the history information corresponding to a position
And the preceding decoding using a result obtained by referring to the history information.
Branch prediction means for predicting the execution result of a branch instruction
The starting position holding means detects the loop structure of the program.
Loop detecting means for detecting the
First instruction of loop based on the loop structure of the issued program
Loop start address holding
And a processor. 8. The loop detecting means branches backward.
Program loop structure by decoding branch instructions
8. The apparatus according to claim 7, further comprising means for detecting
Processor. 9. A branch result indicating whether a branch instruction is taken or not taken.
Is recorded as history information corresponding to the relative position from the starting point.
First means, and preceding decoding before execution of the next branch instruction
The history information based on the relative position of the preceding decoding instruction from the origin.
The branch result of the next branch instruction with reference to the report
Second means, wherein the first means retains the position of the starting instruction.
Holding means and an execution interpreter for decoding instructions for execution
And the command position held by the starting position holding means.
Instruction to get relative position of instruction decoded for execution as
When the position acquisition means and the decoded instruction are branch instructions
The branch result of the branch instruction as history information;
History recording means for recording corresponding to the relative position of the instruction;
Made, the second means, the prior solution of the instruction before execution of the next instruction
Reading means for reading and holding by the starting position holding means.
The relative position of the previously decoded instruction is
Preceding instruction position acquisition means to obtain and precedently decoded instruction branch
If it is an instruction, the relative value of the previously decoded branch instruction
History reference means for referring to the history information corresponding to a position
And the preceding decoding using a result obtained by referring to the history information.
Branch prediction means for predicting the execution result of a branch instruction
And the starting position holding means detects the start address of the program block.
A block start address detecting means for detecting a dress;
Detected address in the serial block start address detection means
And block start address holding means for holding
And a processor. 10. A branch connection indicating whether a branch instruction is taken or not taken.
Record the result as history information corresponding to the relative position from the starting point
First means for performing the above, and preceding decoding before execution of the next branch instruction
Sometimes the history is based on the relative position of the preceding decoding instruction from the starting point.
Predicting the branch result of the next branch instruction with reference to the information
Second means, wherein the first means retains the position of the instruction at the starting point.
Holding means and an execution interpreter for decoding instructions for execution
And the command position held by the starting position holding means.
Instruction to get relative position of instruction decoded for execution as
When the position acquisition means and the decoded instruction are branch instructions
The branch result of the branch instruction as history information;
History recording means for recording corresponding to the relative position of the instruction;
Made, the second means, the prior solution of the instruction before execution of the next instruction
Reading means for reading and holding by the starting position holding means.
The relative position of the previously decoded instruction is
Preceding instruction position acquisition means to obtain and precedently decoded instruction branch
If it is an instruction, the relative value of the previously decoded branch instruction
History reference means for referring to the history information corresponding to a position
And the preceding decoding using a result obtained by referring to the history information.
Branch prediction means for predicting the execution result of a branch instruction
The instruction position obtaining means counts the instructions decoded for execution.
Means for obtaining the number of instructions by counting
Means for obtaining the number of instructions by counting the previously decoded instructions.
A processor comprising stages. 11. A branch connection indicating whether a branch instruction is taken or not taken.
Record the result as history information corresponding to the relative position from the starting point
First means for performing the above, and preceding decoding before execution of the next branch instruction
Sometimes the history is based on the relative position of the preceding decoding instruction from the starting point.
Predicting the branch result of the next branch instruction with reference to the information
Second means, wherein the first means retains the position of the instruction at the starting point.
Holding means and an execution interpreter for decoding instructions for execution
And the command position held by the starting position holding means.
Instruction to get relative position of instruction decoded for execution as
When the position acquisition means and the decoded instruction are branch instructions
The branch result of the branch instruction as history information ;
History recording means for recording corresponding to the relative position of the instruction;
Made, the second means, the prior solution of the instruction before execution of the next instruction
Reading means for reading and holding by the starting position holding means.
The relative position of the previously decoded instruction is
Preceding instruction position acquisition means to obtain and precedently decoded instruction branch
If it is an instruction, the relative value of the previously decoded branch instruction
History reference means for referring to the history information corresponding to a position
And the preceding decoding using a result obtained by referring to the history information.
Branch prediction means for predicting the execution result of a branch instruction
The instruction position obtaining means branches by decoding for execution.
Count instructions found to be instructions to get the number of instructions
Means for acquiring the preceding instruction position,
Instructions that are determined to be branch instructions by
A processor comprising means for obtaining an instruction number. 12. A branch connection indicating whether a branch instruction is taken or not taken.
Record the result as history information corresponding to the relative position from the starting point
First means for performing the above, and preceding decoding before execution of the next branch instruction
Sometimes the history is based on the relative position of the preceding decoding instruction from the starting point.
Predicting the branch result of the next branch instruction with reference to the information
Second means, wherein the first means retains the position of the instruction at the starting point.
Holding means and an execution interpreter for decoding instructions for execution
And the command position held by the starting position holding means.
Instruction to get relative position of instruction decoded for execution as
When the position acquisition means and the decoded instruction are branch instructions
The branch result of the branch instruction as history information;
History recording means for recording corresponding to the relative position of the instruction;
Made, the second means, the prior solution of the instruction before execution of the next instruction
Reading means for reading and holding by the starting position holding means.
The relative position of the previously decoded instruction is
Preceding instruction position acquisition means to obtain and precedently decoded instruction branch
If it is an instruction, the relative value of the previously decoded branch instruction
History reference means for referring to the history information corresponding to a position
And the preceding decoding using a result obtained by referring to the history information.
Branch prediction means for predicting the execution result of a branch instruction
The instruction position obtaining means is configured to decode the decoded instruction for execution.
Ad held by the address and the origin position location holding means
Means for obtaining a difference from the
The obtaining means calculates the address of the instruction decoded earlier and the starting position.
Means for obtaining a difference from the address held by the holding means
A processor comprising: