JP2937318B2 - Amorphous silicon thin film transistor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] An amorphous silicon thin film transistor having an active layer having a structure in which an impurity-doped layer and a non-doped layer are stacked adjacent to each other is provided. Aiming to be able to control the threshold voltage of the TFT, one of two opposing main surfaces of the operating semiconductor layer is provided with a gate electrode via a gate insulating film, and the other is provided with a source electrode and a drain electrode In the thin film transistor, at least a portion of the active semiconductor layer corresponding to the gate electrode is in contact with the gate insulating film, is thinner than the thickness of the space charge region and has a non-doped layer having a thickness of 20 to 1000 mm, and has a predetermined threshold voltage. And a doped layer doped with an impurity of a group III or V material, and amorphous silicon Configured to be from.

[Industrial applications]

The present invention relates to an amorphous silicon thin film transistor including an active layer having a structure in which a layer doped with an impurity and a non-doped layer are stacked adjacent to each other.

[Conventional technology]

Amorphous silicon (a-Si) thin film transistors (TFTs), which are developed and frequently used as switching elements for driving liquid crystals, control the threshold voltage to a desired value.
And the OFF current needs to be reduced.

For this purpose, MOs made using single crystal Si
As in the case of the SFET, it is necessary to dope impurities into the channel portion of the semiconductor layer. That is, by doping the semiconductor layer with an impurity, the amount of charges fixed to the space charge region is controlled, and the threshold value is set to a desired value.

[Problems to be solved by the invention]

In the case of single-crystal Si, the fixed charge amount increases almost in proportion to the doping amount, but in the case of a-Si, a larger amount of doping must be performed to obtain the same fixed charge amount. Therefore, the mobility is greatly reduced, and the characteristics as a switching element are deteriorated.

An object of the present invention is to make it possible to control the threshold voltage of a TFT by doping impurities without lowering the mobility.

[Means for solving the problem]

An amorphous silicon transistor according to the present invention is a thin film transistor in which a gate electrode is provided on one of two opposing main surfaces of an operation semiconductor layer via a gate insulating film, and a source electrode and a drain electrode are provided on the other. At least a portion corresponding to the gate electrode is in contact with the gate insulating film, is thinner than the thickness of the space charge region and has a non-doped layer having a thickness of 20 ° to 1000 °, and a group III or V group so as to have a predetermined threshold voltage. The doped layer doped with the impurity of the material is constituted by an amorphous silicon layer stacked adjacently.

(Operation)

The mobility of the TFT depends on the interface characteristics between the insulating film and the semiconductor layer, and the threshold voltage shifts depending on the doping amount in the active semiconductor layer.

The shift of the threshold voltage due to doping is caused by the fourth
This is because in the energy band diagram of FIG. 3A, the acceptor or the donor in the space charge region 10 on the semiconductor side is ionized and becomes fixed charge.

Therefore, at least the channel forming region in the interface between the gate insulating film 2 and the operation semiconductor layer 3 is formed using a non-doped a-Si layer having good interface characteristics, and the remaining space charge region 10 is doped. If the a-Si layer 4 is used, the threshold voltage can be controlled without lowering the mobility of the TFT.

FIG. 4B is an energy band diagram of a TFT when such a non-doped layer and a doped layer are stacked. Figure 10
Is a space charge region, and the interface with the gate insulating film 2 is formed by using a non-doped a-Si layer 3 to prevent a decrease in mobility, and the doped a-Si layer 4 is connected to the space charge region.
The threshold value is controlled by forming the threshold value within 10.

The hatched area in the figure is the doped a-Si layer 4, and if the a-Si layer 4 is in the space charge region 10 as shown in this figure, the threshold control can be performed.

Since the thickness of the space charge region 10 of the TFT is approximately 1000 mm, it is necessary that the doped a-Si layer 4 exists within approximately 1000 mm from the interface of the gate insulating film 2 in order to contribute to the threshold control. It is. Therefore, the thickness of the doped a-Si layer 3 needs to be 1000 ° or less at the maximum.

On the other hand, if the formed thin film is too thin, it is difficult to form a uniform film, and about 20 ° is the practical lower limit.

As described above, according to the configuration of the present invention, since the interface between the gate insulating film 2 and the active semiconductor layer is the non-doped a-Si layer 3, the mobility is not reduced, and the doped a-Si layer 4 is the gate insulating film. Since it is not in contact with the film 2, the mobility is not affected. Therefore, the doping concentration of the doped a-Si layer 4 can be arbitrarily selected, and the threshold voltage can be selected as desired.

〔Example〕

FIG. 1 is a sectional view of a main part showing a configuration of an a-Si thin film transistor according to one embodiment of the present invention.

In the figure, reference numeral 1 denotes, for example, titanium (T
i) a gate electrode, 2 is a gate insulating film, for example, a silicon nitride (SiN) film having a thickness of about 3000 mm;
4 is a non-doped a-Si layer with a thickness of 4 and 4 is a doped a-Si layer, and is a p-type a-layer with a thickness of about 450 ° doped with boron (B).
The -Si layers 5 and 5 'are made of an aluminum (Al) layer having a thickness of about 1000 DEG and are a source electrode and a drain electrode which are in ohmic contact with the doped a-Si layer 4.

Plasma chemical vapor deposition (P-CVD) or reactive sputtering is used to form the SiN film 2, the non-doped a-Si layer 3 and the doped a-Si layer 4, and the doping of the acceptor is performed by forming the a-Si layer. by occasionally adding B ₂ H _6,
It is well known that the Al layers 5, 5 'can be formed by a vacuum deposition method.

The voltage-current characteristics of the a-Si thin film transistor of the present embodiment configured as described above will be described with reference to FIG.

A diagram showing the dependence the figure with respect to the gate voltage I _G of the drain current I _D, curve I characteristics when all the active semiconductor layer undoped, characteristics when II is where the entire active semiconductor layer and the doped layer, III is the characteristic of the present embodiment.

When the entire operation semiconductor layer is doped with impurities, that is, in the conventional configuration, although the threshold value can be controlled as shown in the curve II, the mobility decreases at the same time, resulting in a gentle slope characteristic. I will.

In the present embodiment shown by the curve III, since the mobility does not decrease, the threshold voltage can be controlled without deteriorating the current characteristics.

FIG. 3 (a) shows a change in the threshold voltage with respect to the doping amount, and FIG. 3 (b) shows the mobility with respect to the doping amount.
Curves II in (a) and (b) are the characteristics of a conventional TFT in which impurities are doped in the entire operation semiconductor layer, and curve III is the characteristics of the TFT according to the present embodiment.

As can be seen from the above two figures, the threshold voltage can be controlled by the doping amount in the conventional method, but the mobility is drastically reduced. Has no effect. This is because, as described above, the interface with the gate insulating film 2 is a non-doped layer, and a doped layer is laminated on this non-doped layer.

In the above embodiment, an electron accumulation type TFT doped with group III boron (B) has been described. However, the present invention is directed to a hole accumulation type TFT doped with group V material. Of course, it can also be applied to

It is needless to say that the dopant can be arbitrarily selected.

In this embodiment, an example in which the non-doped a-Si layer 3 and the doped a-Si layer 4 are formed over the entire surface of the gate insulating film 2 has been described. May be provided in the region where is formed.

In this embodiment, an example in which an inverted staggered TFT is formed has been described. However, the present invention can be applied to a staggered TFT.

In the present invention, the thickness of the non-doped layer 3 is set to about 20 to 1000
However, as described above, this is due to the following reason.

Since the thickness of the space charge region of the TFT is about 1000 mm,
In order for the doped layer 4 to contribute to control of the threshold voltage _Vth , the doped layer 4 must be present within about 1000 ° from the gate insulating film interface. Therefore, when the thickness of the non-doped layer exceeds 1000 °, threshold control becomes impossible. Therefore, the non-doped layer 3 has a maximum thickness of 1000 °. On the other hand, in order to form a thin film uniformly, it is about 20 mm
The degree is the limit, and if it is less than this, it is difficult to form a uniform film, which is a practical limitation on the lower limit of the film thickness.

〔The invention's effect〕

As is apparent from the above description, according to the present invention, the threshold voltage can be shifted without lowering the mobility.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a main part showing the structure of one embodiment of the present invention, FIG. 2 is a current-voltage characteristic diagram of the above embodiment, and FIGS. 3 (a) and 3 (b) show the influence of the doping amount. FIG. 4A and FIG. 4B are energy band diagrams of the TFT. In the figure, 1 is a gate electrode, 2 is a gate insulating film (SiN
Film), 3 is a non-doped a-Si layer, 4 is a doped a-Si layer,
5 is a source and drain electrode, and 10 is a space charge region.

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Tetsuro Endo 1015 Uedanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture Inside Fujitsu Limited (72) Inventor Michiya Oura 1015 Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture Fujitsu Limited (56) References JP-A-61-145869 (JP, A) JP-A-58-86776 (JP, A) JP-A-59-172774 (JP, A) JP-A-61-170069 (JP, A) JP-A-62-282462 (JP, A) JP-A-63-1074 (JP, A) JP-A-63-102263 (JP, A)

Claims (1)

(57) [Claims] 1. A thin film transistor having a gate electrode disposed on one of two opposing main surfaces of an operation semiconductor layer via a gate insulating film and a source electrode and a drain electrode disposed on the other, wherein at least the A portion corresponding to the gate electrode is in contact with the gate insulating film, a non-doped layer having a thickness smaller than the thickness of the space charge region and having a thickness of 20 to 1000 mm, and an impurity of a group III or V material so as to have a predetermined threshold voltage. An amorphous silicon thin film transistor, characterized in that a doped layer doped with is formed of an amorphous silicon layer stacked adjacently.