JP2926775B2 - Semiconductor memory - Google Patents

Description

The present invention relates to a semiconductor memory having a so-called LDD (Lightly Doped Drain) structure in which a low concentration impurity region and a high concentration impurity region are formed.

[Summary of the Invention]

According to the present invention, in a semiconductor memory having at least a memory cell and a peripheral circuit, a high-concentration impurity region connected to a bit line of a switching MOS transistor in the memory cell is made the same as the high-concentration impurity region. By forming a shallow portion in the conductive type low-concentration impurity region, the bit line capacitance can be reduced, the input signal level can be improved, and the reading speed can be increased.

[Conventional technology]

In recent years, due to demands for higher density and higher performance of LSIs, the channel length of switching MOS transistors has been gradually reduced. However, the power supply voltage is TT
5V is used as before because of compatibility with L. As a result, the electric field strength of the channel is increased, and the traveling energy obtained by the carriers is also considerably high, resulting in a problem that the performance of the MOS transistor is deteriorated.

To solve this problem, the use of the LDD structure is currently the main focus. The LDD structure controls the impurity profile in the vicinity of the drain to reduce the electric field intensity, and is extremely effective in controlling generation of carriers having high energy, that is, hot carriers.

Next, the configuration of a conventional switching MOS transistor having an LDD structure will be described with reference to the manufacturing process diagram of FIG. 2. First, as shown in FIG. 2A, a P-type semiconductor substrate or a P-type well is formed. After a gate insulating film (22) is formed on the region (21) by thermal oxidation or the like, for example, a polycrystalline silicon layer is patterned on the gate insulating film (22) to form a gate electrode (23).

Next, as shown in FIG. 2B, an N-type impurity is ion-implanted using the gate electrode (23) as a mask to form a low concentration impurity region (24) on the surface of the substrate or the well region (21).

Next, as shown in FIG. 2C, an insulating film made of, for example, SiO ₂ is formed on the entire surface, and then, for example, RIE is performed on the entire surface.
Anisotropic etching such as (reactive ion etching) is performed to form a sidewall (25) on the gate electrode (23).

Next, as shown in FIG. 2D, high-concentration source / drain regions (26) are formed by ion-implanting N-type impurities using the gate electrode (23) and the sidewalls (25) as a mask. An MOB transistor according to a conventional example is obtained.

[Problems to be solved by the invention]

However, in a conventional switching MOS transistor having an LDD structure, a high concentration N ⁺ region (source / drain region) is used for a basic or well region (21).
(26) is in contact with this high-concentration impurity region (26)
When the switching MOS transistor is used to form, for example, a DRAM (dynamic RAM), the bit line capacitance increases and the input signal level decreases. In addition, there is a disadvantage that the reading speed is reduced.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and an object of the present invention is to reduce the bit line capacity, improve the input signal level, and increase the read speed. Is to provide.

[Means for solving the problem]

A semiconductor memory according to the present invention is a semiconductor memory including at least a memory cell (A) and a peripheral circuit (B).
The high-concentration impurity region (17b) connected to the bit line (16) of the MOS transistor is
And shallowly formed in a low-concentration impurity region (5b) of the same conductivity type.

[Action]

According to the configuration of the present invention described above, the high concentration impurity region (17b) connected to the bit line (16) is changed to the low concentration impurity region (5
b) Since the bit line contact (C) is formed to be shallower, the junction with the substrate or well region (1) at the bit line contact (C) is performed through the low concentration impurity region (5b) having a low impurity concentration. Therefore, the junction capacitance C _D of the bit line contact portion (C) is a high-concentration impurity regions (17b) and the substrate or well region (1) is greatly reduced than the conventional case had been joined, it accompanied no bit line capacitance C _B is also made as reduced. As a result, an improvement in the input signal level and an increase in the reading speed can be realized.

〔Example〕

Hereinafter, an embodiment of the present invention will be described with reference to FIG.

FIG. 1 is a process diagram showing the configuration of a semiconductor memory according to the present embodiment, particularly a semiconductor memory having an LDD structure and employing a DRAM as a memory cell, in the order of manufacturing steps. The steps will be described below in order.

First, as shown in FIG. 1A, selective oxidation is performed on a P-type semiconductor substrate or a P-type well region (1) to form a field insulating layer (2).
For example, a polycrystalline silicon layer is patterned via a gate insulating film (3) on an element formation region surrounded by, that is, on an element formation region of the memory cell portion (A) and the peripheral circuit portion (B), and each of the gate electrodes ( 4) is formed.

Next, as shown in FIG. 1B, an N-type impurity such as phosphorus (P) or arsenic (As) is ion-implanted using each gate electrode (4) as a mask, and the memory cell portion (A) and the peripheral circuit are implanted. Low concentration impurity regions (5a) to (5e) are formed on the surface of the portion (B). The impurity concentration at this time is 10 ¹⁸ to 10 ^{19 in} this example.
cm ^-3 . Thereafter, heat treatment is performed to activate the low-concentration impurity regions (5a) to (5e).

Next, as shown in FIG. 1C, an insulating film made of, for example, SiO _{2 is} formed on the entire surface including the gate electrode (4) by, for example, a CVD method or the like. Etching is performed to form a sidewall (6) on the gate electrode (4).

Next, as shown in FIG. 1D, after forming a resist film (7) only in the memory cell portion (A), the peripheral circuit portion (B)
Then, high-concentration impurity regions, that is, source and drain regions (8a) and (8b) are formed in the peripheral circuit portion (B) by ion-implanting N-type impurities, for example, arsenic (As). The impurity concentration at this time is set to 10 ²⁰ to 10 ²¹ cm ^-3 in this example.
The implantation energy and the like for ion implantation were set so that the depths of the drain regions (8a) and (8b) were almost the same as the depths of the low concentration impurity regions (5b) and (5e).

Next, as shown in FIG. 1E, the resist film (7) formed on the memory cell portion (A) is removed, and after that, an interlayer insulating film (9) made of, for example, SiO ₂ is formed on the entire surface. ,
Window (10a) leading to low-concentration impurity regions (5b) and (5c)
And (10c) are opened.

Next, as shown in FIG. 1F, for example, a polycrystalline silicon layer is formed on the entire surface and then patterned to form a capacitor lower electrode (11) in the memory cell portion (A). N-type impurities such as arsenic (As)
Is ion-implanted. Alternatively, the capacitor lower electrode (11) may be formed of a polycrystalline silicon layer doped with N-type impurities in advance.

Next, as shown in FIG. 1G, after a dielectric film (12) made of, for example, Si ₃ N ₄ is formed on the capacitor lower electrode (11), for example, a polycrystalline film is formed on the dielectric film (12). A capacitor upper electrode (13) made of a silicon layer is formed, and then an interlayer insulating film (14) made of, for example, SiO ₂ is formed on the entire surface, and then the low-concentration impurity region (5b) of the memory cell portion (A) and the peripheral circuit are formed. Open windows (15a) and (15b) leading to the source and drain regions of section (B), for example, region (8a).

Next, as shown in FIG. 1H, for example, a polycrystalline silicon layer or a so-called polycide layer composed of a polycrystalline silicon layer and a refractory metal silicide layer is formed on the entire surface and then patterned to form a bit line (16). I do. Thereafter, an N-type impurity such as arsenic (As) is ion-implanted into the bit line (16) to form a high-concentration impurity region (17b) in the bit line contact portion (C). At this time, the implantation energy of the ion implantation is changed to the low concentration impurity region (5a) shown in FIG. 1B.
To (5e), the depth of the high-concentration impurity region (17b) is limited to the source / drain region (8a) or (8) of the peripheral circuit portion (B).
The depth becomes shallower by the thickness of the bit line (16) than the depth of b).
Thereafter, heat treatment is performed to activate the high-concentration impurity regions (17b). At this time, N-type impurities in the capacitor lower electrode (11) are simultaneously thermally diffused to form shallow high-concentration impurity regions (17a) and (17c), thereby obtaining the semiconductor memory having the LDD structure according to the present example. The high-concentration impurity region (17b) has an impurity concentration of about 10 ²⁰ cm ^{−3 in} this example. Further, in this example, arsenic (As) having a lower diffusion rate than phosphorus (P) was used as the N-type impurity, so that during the subsequent heat treatment, the high-concentration impurity region (17b) is thermally diffused. It will be very shallow.

As described above, according to the present example, the high-concentration impurity region (17b) of the bit line contact portion (C) is connected to the peripheral circuit portion (B).
Is formed shallower than the source and drain regions (8a) and (8b), so that the depth of the high-concentration impurity region (17b) is smaller than that of the low-concentration impurity regions (5a) to (5c). Low-concentration impurity region (17b) to low-concentration impurity region (5b)
, The PN junction of the bit line contact portion (C) is formed by the P-type substrate or well region (1) and the low-concentration impurity region (5b). It can be reduced to about 1/2 compared to that. Meanwhile, important parameters governing the performance of the DRAM, the ratio of the bit line capacitance C _B and the memory cell capacitor C _S, i.e.
C _B / C is _S value, the bit line capacitance C value memory cell capacitance C of the _B
The performance is higher as the value is smaller than _S, so that the input signal level can be improved and the reading speed for the read signal from the cell can be increased. Bit line capacitance C _B has the following formula relationship.

C _B = C _D + C _WL + C _PL + C _BL where C _D is the junction capacitance of the bit line contact (C), C _WL is the capacitance between the bit line (16) and the gate electrode (4), and C _PL is the field capacitance between the bit line (16) substrate via an insulating layer (2) (or well) (1), C _BL indicates the capacitance between the bit line (16).

And in this example, the junction capacitance C _D Hakare reduction of, accompanied no bit line capacitance of the bit line contact portion of the parameters that determine the as described above the bit line capacitance C _B (C)
It is possible to reduce the C _B. Therefore, the input signal level can be improved and the read speed for the read signal from the cell can be increased, so that a high-performance semiconductor memory can be obtained.

Since the high-concentration impurity regions (17a) to (17c) are formed shallow in the memory cell portion (A), the source and drain regions in the memory cell portion (A) are substantially low-concentration impurity regions. Although (5a) to (5c) almost occupy, the resistance increases, but it is at most about 1 kΩ, which is negligible compared to 10 kΩ in the channel region at the time of operation. The reduction in the driving capability of the word line (gate electrode) due to the increase in the resistance of the semiconductor device is at a level that causes almost no problem.

In the above embodiment, arsenic (As) is ion-implanted when forming the high-concentration impurity region (17b), but phosphorus (P) may be ion-implanted. In this case, a relatively deep high concentration impurity regions than in the arsenic (As), junction capacitance C _D is reduced as in the case of arsenic (As).

In the above embodiment, the high-concentration impurity region (17b) of the bit line contact portion (C) is formed by ion implantation of an N-type impurity. Alternatively, a salicide structure may be applied. That is, in FIG. 1E, the interlayer insulating film (9)
After the peripheral circuit portion (B) is masked prior to the formation of, a metal, for example, titanium (Ti) is deposited on the low concentration impurity regions (5a) to (5c) and the gate electrode (4).
By heat treatment, only the surface of the gate electrode (4) and the surfaces of the low-concentration impurity regions (5a) to (5c) are silicided in a self-aligned manner to form a salicide layer. In this case, in the post-process,
No impurity ions are implanted into the capacitor lower electrode (11) and the bit line (16), and the bit line (16) is contacted via the salicide layer. This salicide structure is similar to the window (15a) in FIG.
After the opening, a metal, for example, titanium (Ti) may be deposited only on the surface of the bit line contact portion (C).

〔The invention's effect〕

In the semiconductor memory according to the present invention, the high-concentration impurity region connected to the bit line of the switching MOS transistor in the memory cell is formed shallowly in the low-concentration impurity region of the same conductivity type as the bit line. The capacity can be reduced, the input signal level can be improved, and the reading speed can be increased.

[Brief description of the drawings]

FIG. 1 is a process diagram showing the configuration of a semiconductor memory according to the present embodiment according to a manufacturing process, and FIG. 2 is a process diagram showing a MOS transistor according to a conventional example according to a manufacturing process. (A) is a memory cell portion, (B) is a peripheral circuit portion, (C) is a bit line contact portion, (1) is a semiconductor substrate or well region, (2) is a field insulating layer, (4) is a gate electrode, (5a) to (5e) are low concentration impurity regions, (6) is a sidewall, (8a) and (8b) are source and drain regions, (9) and (14) are interlayer insulating films, and (11) is a capacitor. A lower electrode, (12) is a dielectric film, (13) is a capacitor upper electrode, and (16) is a bit line.

Claims (1)

(57) [Claims] 1. A semiconductor memory comprising at least a memory cell and a peripheral circuit, wherein the high-concentration impurity region connected to a bit line of a switching MOS transistor in the memory cell comprises a high-concentration impurity region. A semiconductor memory formed shallowly in a low-concentration impurity region of the same conductivity type as that of the semiconductor memory.