JP2925162B2 - Data multiplexer - Google Patents

Description

The present invention relates to a data multiplexing device for multiplexing a plurality of input data, and more particularly to a clock supply means for a multi-stage multiplexing circuit. The present invention relates to an improved data multiplexing device.

(Prior Art) Conventionally, a data multiplexing device that multiplexes input data is
It is widely used not only in communications but also in fields such as digital arithmetic processing. In the multiplexing of data, the transmission rate of the multiplexed data increases as the amount of information increases. Therefore, when a plurality of multiplexing circuits are used, the multiplexing circuit in the subsequent stage (higher order group) is used in the preceding stage. (Low order group)
The timing of taking in the output data of the multiplexing circuit becomes important.

FIG. 6 is a block diagram showing a schematic configuration of a conventional data multiplexing device. An n: 1 multiplexing circuit 62 is connected to the subsequent stage of the m: n multiplexing circuit 61, and has a two-stage configuration. A timing signal for fetching data is generated based on a clock signal of the subsequent stage. Here, the load signal frequency at the time when the input data is read by the subsequent (higher-order group) multiplexing circuit 62 is f _ck / n
Therefore, this signal is generated in the subsequent multiplexing circuit 62 and fed back to the low-order group multiplexing circuit 61, and a timing adjuster for the input data and the load signal is provided, so that the high-order group multiplexing is performed. The timing at which the circuit 62 takes in data is adjusted.

The multiplexing circuits 61 and 62 are shift register type multiplexers (MUX). For example, assuming a 2: 1 MUX, a D flip-flop (DFF) 71, as shown in FIG.
72, selectors 73 and 74, a frequency divider 75 and the like. Data D ₁ is supplied to the DFF71 through the selector 73, the output of the DFF71 is supplied to the DFF72 through the selector 74, the output of the DFF72 is the output of the MUX. The clock signal is supplied to DFFs 71 and 72, and is also frequency-divided by a frequency divider 75 to 1/2.
Supplied to 3,74. The selectors 73 and 74 switch data to be selected each time a clock is input. Therefore, when the data rate of the input data is 5 Gbps, the clock frequency f
_{When ck is set} to 10 GHz, the data D ₁ and D ₂ are read at a load frequency of f _ck / 2 = 5 GHz and multiplexed to become 10 Gbps output data.

However, this type of apparatus has the following problems. In other words, it is necessary to match the timing at which the output data from the low-order group multiplexing circuit is captured by the high-order group multiplexing circuit. For this purpose, a load signal at the time of data input is created based on the high-order group clock frequency, and the input data It must be realized by providing a timing adjuster. In this case, as the speed becomes higher, the timing adjuster itself becomes more important, and the circuit design becomes more difficult.

(Problems to be Solved by the Invention) As described above, conventionally, when a multiplexing circuit is configured in a plurality of stages and a load signal for capturing input data is generated based on a clock frequency of a higher-order group, output data from a lower-order group and load Timing adjustment with a signal is required, and this timing adjustment is extremely difficult.

The present invention has been made in view of the above circumstances, and its purpose is to eliminate the need for timing adjustment between the output data from the low-order group and the load signal in the high-order group, and from the low-order group to the high-order group. To provide a data multiplexing device that facilitates data transfer.

[Structure of the Invention] (Means for Solving the Problems) The most important point of the multiplexing circuit is the timing at which the input data is fetched, and once the data is fetched, multiplexing the data is not so important. is not a problem. Conventionally, a load signal for capturing input data has been generated based on a clock signal of a high-order group, so that a time lag between output data of a low-order group, that is, input data to a high-order group and a load signal has occurred. . Therefore, if a signal synchronized with the output data of the low-order group is used as it is as the load signal of the high-order group, no time lag occurs.

The present invention pays attention to such a point, and in a data multiplexing device that multiplexes data using a plurality of multiplexing circuits, operates a subsequent multiplexing circuit with reference to a clock of the preceding multiplexing circuit. It is like that.

More specifically, the present invention relates to a data multiplexing apparatus for multiplexing data using a multi-stage multiplexing circuit, wherein different input data are selected at rising and falling edges of a clock using a selector, and Using a selector-type multiplexing circuit in which the data rate and the clock frequency match, the frequency f _ck of the clock input to the preceding m: n multiplexing circuit is multiplied by m / n between adjacent multiplexing circuits. A frequency multiplier to be supplied to the subsequent multiplexing circuit is inserted.

(Operation) According to the present invention, since the load signal at the time of data input to the high-order group is generated based on the clock of the low-order group, the timing adjustment between the output data from the low-order group and the load signal can be performed. This is unnecessary, and data transfer from the low-order group to the high-order group can be facilitated. At this time, the condition is that the input data rate and the clock frequency match.

(Examples) Hereinafter, details of the present invention will be described with reference to the illustrated examples.

FIG. 1 is a block diagram showing a basic configuration of a multiplexer according to a first embodiment of the present invention. In the figure, reference numeral 10 denotes an m: n multiplexing circuit as a low-order group side, and an output signal of the multiplexing circuit 10 is supplied to an n: 1 multiplexing circuit 20 on the high-order group side. The clock (frequency f _ck ) is supplied to the multiplexing circuit 10, and a clock whose frequency is multiplied by m / n in the multiplexing circuit 10 is supplied to the multiplexing circuit 20. In other words, the multiplexing circuit in the subsequent stage is operated at a clock frequency _fck · m / n that is m / n times the clock frequency _fck on the low order group side.

FIG. 2 is a block diagram showing FIG. 1 more specifically. Here, an 8: 1 multiplexer (hereinafter abbreviated as MUX) will be described as an example.

The 8: 1 MUX itself is a tree-like configuration of a 2: 1 MUX. That is, the input data is MUX31 _{1 to} 31 of the first stage.
₄ are supplied, the output data of these MUX 31 ₁ to 31 ₄ is supplied to the MUX 31 _5, 31 ₆ of the second stage, the output data of the MUX 31 _5, 31 ₆ is supplied to the MUX 31 ₇ of the third stage You. And MU
X31 ₇ from the input data 8: multiplexed data is output to the 1.

Clock f _ck is input to the MUX 31 ₁ to 31 ₄ of the first stage,
This clock f _ck is an exclusive OR (XOR) gate 32
The ₁ and a delay circuit (DL) 33 ₁ is multiplied twice the clock 2f _ck is input to the MUX 31 _5, 31 ₆ of the second stage. further,
This clock 2f _ck is multiplied twice by XOR gates 32 ₂ and DL33 _2, clock 4f _ck is input to the MUX 31 ₇ of the third stage. Here, the first and second stage of MUX 31 ₁ to 31 ₆ corresponds to the multiplexing circuit 10 of the low-order, third-stage MUX 31 ₇ is equivalent to the multiplexing circuit 20 of the high-order group.

FIG. 3 is a block diagram showing a specific circuit configuration of the 2: 1 MUX. This circuit is basically a master-slave type D flip-flop (hereinafter abbreviated as MS-DFF) 41,
This is a selector system including a three-stage D flip-flop (hereinafter abbreviated as TS-DFF) 42, a selector 43, and the like. One of the input data is supplied to the MS-DFF41, and the other is supplied to the TS-DFF42. Then, the output data of each of the DFFs 41 and 42 is supplied to the selector 43 and selectively output. The clock signal f _ck is MS-DFF41, TS-DFF
42 and the selector 43 respectively. In the figure, reference numerals 44, 45, 46 and 47 denote buffer amplifiers, respectively.

Here, as shown in FIG. 4, the data Da input to the MS-DFF 41 is delayed by about 1/2 clock, and the data Db input to the TS-DFF 42 is delayed by about 1 clock. Da ′ and Db ′ are data obtained by delaying Da and Db, respectively. The selector 43 switches data Da 'and Db' to be taken in at the rise and fall of the clock _fck . Therefore, selector 4
From 3, data Da and Db are multiplexed and output.

In the configuration shown in FIG. 2, the first-stage MUXs 31 _{1 to} 31 ₄
When the input data rate is 1 Gbps, a clock of f _ck = 1 GHz is input. At that time, data is taken in the first-stage MUXs 31 _{1 to} 31 ₄ without timing adjustment, and the multiplexed data is sent to the second-stage MUXs 31 ₅ and 31 ₆ . Second stage
MUX 31 _5, 31 in _6, the frequency f _ck of the clock is input is doubled by XOR gates 32 ₁ and DL33 _1. Therefore, 2Gb
A clock of 2 GHz is input for an input data rate of ps, and data is taken in without timing adjustment as in the first stage. The third stage is realized in a similar manner.

Thus, according to the present embodiment, the clock input to the preceding MUX is doubled and supplied to the subsequent MUX, and the load signal (clock) supplied to the subsequent MUX is supplied to the preceding MUX.
There is no time lag because it is synchronized with the output data. Therefore, without providing a timing adjuster or the like,
Data transfer from the low-order group to the high-order group can be easily performed.

FIG. 5 is a block diagram showing a schematic configuration of a reference example of the present invention. This reference example differs from the above-described embodiment in that a multiplexing device is realized by combining circuits having different sampling rates for the same frequency. Here, the low-order group is an 8: 2 MUX, and the high-order group is 2:
The MUX 50 of the lower order group is a circuit having the same sampling rate as the clock, and the MUX 20 of the higher order group is a circuit having a sampling rate twice the clock. Specifically, the lower order group side is a combination of the shift register type MUX shown in FIG. 7, and the higher order side MUX is the selector type MUX shown in FIG.

In this case, the input data rate of the lower order group and the clock frequency f _ck are different, but the input data rate of the higher order group and f _ck can be the same. Further, the lower order group needs a timing adjuster for adjusting the timing of the input data rate and the load signal as in the conventional case, but the higher order group does not need it.

With such a configuration, multiplexing can be performed by supplying the same clock to adjacent multiplexing circuits. Furthermore, the input data rate and f _ck low order group is different, it is possible to equalize the input data rate and f _ck of high-order group. In data multiplexing, it is particularly difficult to match the timing on the higher-order group side, so it is effective to make the input data rate and _{fck the} same on the higher-order group side as in this embodiment.

The present invention is not limited to the above-described embodiment, and can be implemented with various modifications without departing from the spirit of the invention. For example, the multiplexing ratio (m: n) of the low-order group and high-order group multiplexing circuits is not limited to the embodiment, and can be appropriately changed according to the specifications. Further, a part of the connection of the adjacent multiplexing circuit in the first embodiment may include the connection of the multiplexing circuit as in the reference example.

[Effects of the Invention] As described above in detail, according to the present invention, the load signal at the time of data input to the high-order group is generated based on the clock frequency of the low-order group, so that the output from the low-order group is generated. There is no need to adjust the timing between the data and the load signal, and a multiplexing device that facilitates data transfer from the low-order group to the high-order group can be realized.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a schematic configuration of a multiplexer according to a first embodiment of the present invention, FIG. 2 is a block diagram showing FIG. 1 more specifically, and FIG. 3 is a first embodiment. 2: 1 in
FIG. 4 is a block diagram showing a specific circuit configuration of the MUX, FIG. 4 is a timing chart for explaining the operation of the MUX of FIG. 3, FIG. 5 is a block diagram showing a schematic configuration of a reference example of the present invention, and FIG. FIG. 1 is a block diagram showing an example of a conventional multiplexer, and FIG. 7 is a block diagram showing an example of the configuration of the multiplexer shown in FIG. 10, 20 multiplexing circuit (selector method) 31 _{1 to} 31 ₄ … first stage 2: 1 MUX 31 _{5 to} 31 ₆ … second stage 2: 1 MUX 31 ₇ … Third stage 2: 1 MUX 32 ₁ , 32 ₂ XOR gates 33 ₁ , 33 ₂ Delay circuit 41 MS-DFF 42 TS-DFF 43 Selector 50 Multiplex circuit (Shift register method)

Claims (2)

(57) [Claims] In a data multiplexing apparatus for multiplexing data using a plurality of multiplexing circuits, a frequency f of a clock input to a preceding m: n multiplexing circuit is provided between adjacent multiplexing circuits. A data multiplexer comprising a frequency multiplier which multiplies ck by m / n and supplies it to a subsequent multiplexing circuit. 2. The multiplexing circuit according to claim 1, wherein said multiplexing circuit uses a selector to select different input data at rising and falling edges of a clock using a selector, wherein an input data rate and a clock frequency match. The data multiplexing device according to claim 1, wherein