JP2924874B2 - Network congestion suppression device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a network congestion suppressing apparatus, and more particularly, to a network congestion suppressing apparatus for detecting a broken packet generated during processing at a transmitting node before sending the packet to the network and discarding it. The present invention relates to a congestion suppressing device.

[0002]

2. Description of the Related Art Conventionally, an asynchronous communication mode (Asynchro
nous Transfer Mode) AAL (ATM Adaptation Laye)
r) The transmission side node in / TYPE 5 is provided with an ATM switch as a distributing means for distributing an ATM cell arriving at every moment according to its destination. When the frequency at which ATM cells are sent increases and exceeds a predetermined frequency, the ATM switch causes a so-called congestion and causes a plurality of ATs arriving almost simultaneously.
It is known that one of the M cells is ignored.

As described above, when an arriving ATM cell is ignored and lost by a congested ATM switch, a packet including the ATM cell as one element is broken and becomes meaningless information. Therefore, the ATM cell forming the broken packet which is this meaningless information, ie, the AT cell
It must be discarded early so that other ATM cells not ignored by the M-switch do not occupy network resources forever. Examples of such discarding methods include an EPD (Early Packet Discard) method in which all ATM cells forming a broken packet are discarded in a transmitting node, an ATM cell immediately before an ATM cell immediately before being lost is transmitted to a network. A PPD (Partial Packet Discard) method for discarding cells in a transmission node is known.

In any of the above-described EPD and PPD systems, when discarding an ATM cell, a packet identification bit inserted into a trailer of each ATM cell is detected, and according to the value of the packet identification bit. It is determined whether or not the ATM cell is the last cell located at the end of the packet. Then, the ATM cell immediately after the identified last cell is regarded as the first cell of the next packet, and all the ATM cells arriving before the next cell is identified are regarded as ATM cells forming the same packet. And perform disposal processing. As described above, the broken packet generated in AAL / TYPE 5 in the asynchronous communication mode is
It can be found on the TM layer and discarded in packet units.

[0005]

In a packet processed by AAL / TYPE 5, only the last cell at the end of the ATM cells generated from this packet is given a role as a trailer. That is, in order to detect a packet transmission error or to know the number of ATM cells forming a packet, it is essential to analyze this last cell to distinguish the preceding and succeeding packets.

Therefore, the above-mentioned EPD method and PPD
When a method of discarding broken packets generated in AAL / TYPE5 such as a system is applied in packet units, if the ATM cell ignored and lost by the congested ATM switch is the last cell, the successive packets are distinguished. Instead, the packet is discarded as one packet. As a result, only the last cell is lost,
Along with the broken first packet having the last cell as an element, the second packet transmitted normally following the first packet is also regarded as abnormal and discarded by the transmitting node, and two packets are transmitted at a time. The problem of losing is caused. Then, in this case, a retransmission request made from an upper layer is performed for two packets at a time, and as a result, network resources are occupied extra for communication accompanying the retransmission request, and congestion is further increased. The problem that it became easy occurred.

On the other hand, if the discard control of the broken packet such as the EPD method or the PPD method is not performed, the first and second packets, which cannot be distinguished due to the loss of the last cell, pass through the network as they are. Transmitted to the receiving node. In this case, the receiving cell analyzes the last cell of the second packet transmitted after the first packet in which the last cell has been lost, and determines from the first cell of the first packet to the last cell of the second packet. Are considered to form one packet, and transmission errors and A
A check is made of the number of TM cells. Thus, there has been a problem that the first and second packets are discarded at the receiving node as one abnormal packet, and two packets are lost at a time. Also in this case, a retransmission request made from an upper layer is performed for two packets at a time, and as a result, network resources are occupied extra for communication accompanying the retransmission request, and congestion is further increased. The problem that it became easy occurred.

Accordingly, an object of the present invention is to provide a network congestion suppressing apparatus capable of distinguishing between preceding and succeeding packets even if the lost cell is the last cell and reliably discarding only cells forming an abnormal packet. Is to provide.

[0009]

According to the first aspect of the present invention, (a) when a plurality of cells forming a packet are obtained from a packet which is a logical data unit, another packet before and after the packet is obtained. And (b) a plurality of intermediate units each integrating the identification information output by the identification information output unit and a plurality of cells generated from a corresponding packet. Intermediate cell generating means for generating cells, and (c) distributing means for distributing the intermediate cells generated by the intermediate cell generating means according to their destinations except when congested,
(D) identification information extraction means for extracting identification information from the intermediate cells allocated by the allocation means; and (e) packet information of a series of cells having the same identification information extracted by the identification information extraction means. Cell discarding transmission processing means for performing a process of discarding a series of intermediate cells in which some of the cells forming part are missing and transmitting a series of other intermediate cells to the network, and a transmitting side of the network congestion suppression device. Prepare the node.

That is, according to the first aspect of the invention, the identification information output means outputs identification information determined differently from other preceding and succeeding packets, and the intermediate cell generation means generates the identification information from the identification information and the corresponding packet. A plurality of intermediate cells in which the plurality of cells thus obtained are integrated are generated. Therefore, a series of cells having the same identification information extracted by the identification information extracting means from the sorted intermediate cells can be regarded as forming the same packet. In other words, by performing a process of discarding a part of the series of cells that have been lost and transmitting a complete and non-deleted cell to the network, the boundary cells are lost due to congestion of the distribution unit. Even when the packet is dropped, the preceding and succeeding packets can be distinguished, and only the cells forming the abnormal packet can be reliably discarded.

According to the second aspect of the present invention, (a) a plurality of cells forming a packet which is a logical data unit are monitored, and a boundary cell for distinguishing successive different packets from each other is defined as a boundary cell. (B) When a large number of cells forming a plurality of packets are provided, each time the boundary cell detection means detects a boundary cell, the detection of the boundary cell is performed. Identification information output means for outputting identification information determined differently before and after; and (c) intermediate cell generation means for generating an intermediate cell integrating the identification information output by the identification information output means and the corresponding cell. , (D) except when congested,
(E) identification information extraction means for extracting identification information from the intermediate cells allocated by the distribution cell, and (f) identification information extraction. Among a series of cells having the same identification information extracted by the means, a series of intermediate cells in which a part of a plurality of cells forming a packet are missing are discarded, and a series of other intermediate cells are transmitted to a network. And a cell discarding / transmission processing means for performing the processing to be performed are provided in the transmission side node of the network congestion suppression device.

In other words, in the invention according to claim 2, the intermediate cell generating means differs before and after the detection output from the identification information output means every time the boundary cell detecting means detects a boundary cell for distinguishing a packet. Generate an intermediate cell integrating the identification information and the corresponding cell. Therefore, a series of cells having the same identification information extracted by the identification information extracting means from the sorted intermediate cells can be regarded as forming the same packet. That is,
By performing a process of discarding a part of the series of cells that are missing and transmitting a complete and non-missing cell to the network, the boundary cells are lost due to congestion of the distribution unit and the like. Even at this time, the preceding and succeeding packets can be distinguished, and only cells forming abnormal packets can be reliably discarded.

According to a third aspect of the present invention, in the first or second aspect of the present invention, (a) the identification information output by the identification information output means includes a predetermined first value and a predetermined first value. It is characterized by being one of the values of 2.

That is, according to the third aspect of the present invention,
Since the identification information to be integrated with the corresponding cell is only one of the first value and the second value, the information transmission amount is not greatly increased at the time of implementation.

According to the invention of claim 4, (a) either one of a predetermined first value and a second value is always output as identification information, and an instruction to switch the value of the identification information is given. Identification information output means for alternately switching the value of the identification information to be output in accordance with the indicated switching instruction signal, and (b) outputting the identification information to a plurality of cells forming a packet obtained from a packet which is a logical data unit Means for generating a plurality of intermediate cells each integrating the identification information output by the means, and outputting the switching instruction signal when a packet is newly given; Except
Distribution means for distributing the intermediate cells generated by the intermediate cell generation means for each destination; (d) identification information extraction means for extracting identification information from the intermediate cells distributed by the distribution means; and (e) identification information extraction Among a series of cells having the same identification information extracted by the means, a series of intermediate cells in which a part of a plurality of cells forming a packet are missing are discarded, and a series of other intermediate cells are transmitted to a network. And a cell discarding / transmission processing means for performing the processing to be performed are provided in the transmission side node of the network congestion suppression device.

That is, in the invention according to claim 4, the identification information output means always outputs one of the first value and the second value as the identification information according to the switching instruction signal, and the intermediate cell generation means outputs , Generating a plurality of intermediate cells in which the identification information is integrated with the plurality of cells forming the cell, and outputs a switching instruction signal when a packet is newly given. Therefore, a series of cells having the same identification information extracted by the identification information extracting means from the sorted intermediate cells can be regarded as forming the same packet. That is, of these series of cells,
By discarding partially missing packets and sending the complete and non-missing packets to the network, even if border cells are lost due to congestion of the sorting means, it is possible to distinguish packets before and after. However, only cells forming abnormal packets can be reliably discarded.

According to a fifth aspect of the present invention, in the first to fourth aspects of the present invention, (a) the cell discarding and sending processing means (b) temporarily stores the intermediate cells assigned by the assigning means. Cell buffer for temporarily storing
And a cell buffer control unit for transmitting a series of intermediate cells in which a plurality of cells forming the same packet are all stored among the intermediate cells stored in the cell buffer in accordance with the storage order. And

That is, according to the fifth aspect of the present invention,
When a plurality of intermediate cells forming the same packet are all accumulated in the cell buffer as a result of the distribution performed by the distribution means, the cell buffer control unit transmits the series of intermediate cells to the network according to the storage order. Send out. Therefore, only normal packets in which all cells are stored in the cell buffer can be transmitted to the network.

According to a sixth aspect of the present invention, in the fifth aspect of the invention, (a) the cell discard transmission processing means has an accumulation amount detection unit for detecting the accumulation amount of the intermediate cell in the cell buffer. (B) The cell buffer control unit, when the storage amount of the intermediate cells detected by the storage amount detection unit exceeds a predetermined congestion threshold amount, stores the intermediate cells stored in the cell buffer. It is characterized in that, among the cells, a series of intermediate cells in which some of the cells forming the same packet are not stored are all discarded.

That is, in the sixth aspect of the invention,
When the storage amount of the intermediate cells in the cell buffer exceeds a predetermined congestion threshold amount, a series of intermediate cells that have not been stored in the entire series of intermediate cells forming the same packet are discarded. Therefore, by setting the value of the congestion threshold amount to a value smaller than the capacity of the cell buffer in advance, it is possible to suppress the occurrence of congestion due to the capacity of the cell buffer.

[0021]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below with reference to embodiments.

FIG. 1 shows the overall configuration of a network congestion suppressing apparatus according to an embodiment of the present invention.

The input terminal 11 receives an ATM cell forming a packet which is a logical data unit. The destination identifier detection circuit 12 analyzes the ATM cell and analyzes a VPI (Virtual Path) representing the destination.
Identifier) and VCI (Virtual Channel Identifi)
er), and outputs a high-level destination identifier selection signal when the detected values of VPI and VCI are predetermined values, and outputs a low-level destination identifier selection signal otherwise. I have to do it.

The last cell detection circuit 13 further includes the AT
The M cell is analyzed to detect whether or not the ATM cell is the last cell located at the end of a packet which is a boundary cell for distinguishing successive different packets having the same VPI and VCI from each other. And, as a result of the detection,
When the ATM cell is the last cell and the destination identifier selection signal output from the destination identifier detection circuit 12 is at the high level, the high-level final cell detection signal is output. A final cell detection signal is output.

The packet identification bit output circuit 14 always outputs a high or low level packet identification bit signal. When the last cell detection circuit 13 detects the last cell and outputs a high-level last cell detection signal, it starts monitoring the falling of the last cell detection signal, When a fall to the low-level final cell detection signal occurs, the level of the packet identification bit signal is inverted to obtain different identification information before and after the detection of the final cell.

The intermediate cell generation circuit 15 multiplexes the packet identification bit signal output from the packet identification bit output circuit 14 and the corresponding ATM cell to generate an intermediate cell. The ATM switch 16 does not
The intermediate cell generated by the intermediate cell generation circuit 15 is
And according to the VCI.

The intermediate cell check circuit 17 extracts a packet identification bit signal from the intermediate cells distributed by the ATM switch 16, and forms a packet from a series of cells having the same extracted packet identification bit signal. A series of intermediate cells in which some of the plurality of cells are missing are discarded, and a series of other intermediate cells are sent from the output terminal 18 to the network.

FIG. 2 shows a detailed configuration of the intermediate cell check circuit 17 of the network congestion suppressing apparatus according to the present embodiment.

The packet identification bit extraction circuit 21 uses the AT
A packet identification bit signal is extracted from the intermediate cells sorted by the M switch 16 and is sent to a destination identifier extraction circuit 22.
Analyzes the intermediate cell to extract VPI and VCI. The cell buffer 23 temporarily stores the sorted intermediate cells. The cell buffer control unit 24 transmits a series of intermediate cells in which a plurality of cells forming the same packet are all stored among the intermediate cells stored in the cell buffer 23 in accordance with the storage order. Has become. The storage amount detector 25 detects the storage amount of the intermediate cell in the cell buffer 23 and notifies the cell buffer controller 24 of the detected amount.

(Explanation of Operation) Next, the operation of the network congestion suppressing apparatus of the present embodiment will be described with reference to FIGS.

(Circuit Operation Before ATM Switch 16) FIGS. 3 and 4 are diagrams for explaining the circuit operation performed before the ATM switch 16 of the network congestion suppressing apparatus of the present embodiment. FIG. 3 shows data or signals belonging to the first half of a series of time series in circuit operation, and FIG. 4 shows data or signals belonging to the latter half of a series of time series in circuit operation. 3A and FIG. 4A, FIG. 3A shows an ATM cell group input from the input terminal 11, FIG. 3B shows a destination identifier selection signal output from the destination identifier detection circuit 12, and FIG. Output the last cell detection signal
(D) shows the packet identification bit signal output from the packet identification bit output circuit 14, and (e) shows the intermediate cell generation circuit 1.
5 to the ATM switch 16 are:
Each is shown in chronological order. It should be noted that the destination identifier detection circuit 12 according to the present embodiment uses VPI = “VP1” and VCI =
It is assumed that a high-level destination identifier selection signal is output when it is “VC1”, and the circuits provided downstream of the destination identifier detection circuit 12 are such that the destination identifier detection circuit 12 is high. Only when the level destination identifier selection signal is output, the given ATM
The cell is to be processed.

(First packet: packet identification bit =
0) When the ATM cell 300 shown in FIG. 3 is input from the input terminal 11, the destination identifier detection circuit 12 analyzes this and detects VPI and VCI. Here VPI =
Since “VP1” and VCI = “VC1” are detected, the destination identifier detection circuit 12 outputs a high-level destination identifier selection signal 301. The last cell detection circuit 13 analyzes the ATM cell 300, but outputs a low-level last cell detection signal 302 because it is not the last cell.
The packet identification bit output circuit 14 outputs a low-level packet identification bit signal 303, but since the last cell detection circuit 13 outputs a low-level final cell detection signal 302, the low-level packet identification bit The output of the bit signal 303 is maintained. Therefore, the intermediate cell generation circuit 15 outputs the low-level packet identification bit signal 303 output from the packet identification bit output circuit 14.
That is, the packet identification bit “0” and the corresponding ATM
The intermediate cell 304 is generated by multiplexing with the cell 300.
Then, the intermediate cell 304 is input to the ATM switch 16.

The ATM cell 3 shown in FIG.
When 05 is input, the destination identifier detection circuit 12 analyzes this to detect VPI and VCI. Where V
Since PI = “VP1” and VCI = “VC1” are detected, the destination identifier detection circuit 12 outputs a high-level destination identifier selection signal 301. Last cell detection circuit 1
Numeral 3 analyzes the ATM cell 305 and outputs a high-level final cell detection signal 306 because it is the last cell located at the end of the original packet. The packet identification bit output circuit 14 outputs a low-level packet identification bit signal 30.
3, the last cell detection circuit 13 outputs the high-level last cell detection signal 306. Therefore, while maintaining the low-level packet identification bit signal 303, the last cell detection signal 306 is output. Start monitoring for falling. Therefore, the intermediate cell generation circuit 15 multiplexes the low-level packet identification bit signal 303 output from the packet identification bit output circuit 14, that is, the packet identification bit “0”, and the corresponding ATM cell 305 to form the intermediate cell 307. Generate. Then, this intermediate cell 307
Is input to the ATM switch 16 following the previous intermediate cell 304.

(Second packet: packet identification bit =
1) When the ATM cell 308 shown in FIG. 3 is input from the input terminal 11, the destination identifier detection circuit 12 analyzes this and detects VPI and VCI. Here VPI =
Since “VP1” and VCI = “VC1” are detected, the destination identifier detection circuit 12 outputs a high-level destination identifier selection signal 301. The final cell detection circuit 13 analyzes the ATM cell 308 and outputs a low-level final cell detection signal 309 because it is not the last cell. The packet identification bit output circuit 14 changes the low level packet identification bit signal 303 to high when the last cell detection circuit 13 causes a fall from the high level final cell detection signal 306 to the low level final cell detection signal 309. The level is inverted to the packet identification bit signal 310. Therefore, the intermediate cell generation circuit 15 multiplexes the high-level packet identification bit signal 310 output from the packet identification bit output circuit 14, that is, the packet identification bit “1”, with the corresponding ATM cell 308 to form the intermediate cell 311. Generate And, this intermediate cell 31
1 is the ATM switch 16 following the previous intermediate cell 307.
Is input to

The ATM cell 3 shown in FIG.
When 12 is input, the destination identifier detection circuit 12 analyzes this and detects VPI and VCI. Where V
Since PI = “VP2” and VCI = “VC1” are detected, the destination identifier detection circuit 12 outputs a low-level destination identifier selection signal 313. By this low-level destination identifier selection signal 313, the ATM cell 312 is excluded from the processing of each subsequent circuit. The following ATM cell 31
4, VPI = “VP1” and VCI = “V
Since it is C2 ", it is similarly excluded from the processing of the subsequent circuits.

A series of ATMs shown in FIG.
When the cell 315 is input, the destination identifier detection circuit 12
Analyzes these to detect VPI and VCI.
Here, VPI = “VP1” and VCI = “VC1”
Is detected, the destination identifier detection circuit 12 outputs the high-level destination identifier selection signal 316 again. The last cell detection circuit 13 analyzes the ATM cell 316 and determines that the cell is not the last cell.
Is output. The packet identification bit output circuit 14 outputs a high-level packet identification bit signal 310, but since the last cell detection circuit 13 outputs a low-level final cell detection signal 309, the high-level packet identification bit signal 310 is output. The output of the bit signal 310 is maintained. Therefore, the intermediate cell generation circuit 15 multiplexes the high-level packet identification bit signal 310 output from the packet identification bit output circuit 14, that is, the packet identification bit "1", with the corresponding series of ATM cells 315 to form a series of An intermediate cell 317 is generated. Then, these series of intermediate cells 317 are input to the ATM switch 16 following the previous intermediate cell 311.

The ATM cell 3 shown in FIG.
When 18 is input, the destination identifier detection circuit 12 analyzes this to detect VPI and VCI. Where V
Since PI = “VP1” and VCI = “VC1” are detected, the destination identifier detection circuit 12 outputs a high-level destination identifier selection signal 316. Last cell detection circuit 1
Numeral 3 analyzes the ATM cell 318 and outputs a high-level final cell detection signal 319 because it is the last cell located at the end of the original packet. The packet identification bit output circuit 14 outputs a high-level packet identification bit signal 31.
0 is output, but since the last cell detection circuit 13 outputs the high level last cell detection signal 319, the output of the last cell detection signal 319 is maintained while maintaining the output of the high level packet identification bit signal 310. Start monitoring for falling. Therefore, the intermediate cell generation circuit 15 multiplexes the high-level packet identification bit signal 310 output from the packet identification bit output circuit 14, that is, the packet identification bit “1”, with the corresponding ATM cell 318 to form the intermediate cell 320. Generate. And this intermediate cell 320
Is input to the ATM switch 16 following the above series of intermediate cells 317.

The ATM cell 3 shown in FIG.
When 21 is input, the destination identifier detection circuit 12 analyzes this to detect VPI and VCI. Where V
Since PI = “VP1” and VCI = “VC2” are detected, the destination identifier detection circuit 12 outputs a low-level destination identifier selection signal 322. Due to the low-level destination identifier selection signal 322, the ATM cell 321 is excluded from the processing target of each subsequent circuit. At this time, the last cell detection circuit 13 analyzes the ATM cell 321 and outputs a low-level last cell detection signal 323 because it is not the last cell. The packet identification bit output circuit 14 outputs the high-level last cell detection signal 3 by the last cell detection circuit 13.
When a fall from 19 to the low-level last cell detection signal 323 occurs, the high-level packet identification bit signal 310 is changed to the low-level packet identification bit signal 3.
Invert to 24. The following ATM cell 325 shown in FIG. 4 also has VPI = “VP2” and VCI = “VC
Since it is 1 ", it is similarly excluded from the processing of the subsequent circuits.

(Third packet: packet identification bit =
0) When the ATM cell 326 shown in FIG. 4 is input from the input terminal 11, the destination identifier detection circuit 12 analyzes this and detects VPI and VCI. Here VPI =
Since “VP1” and VCI = “VC1” are detected, the destination identifier detection circuit 12 outputs a high-level destination identifier selection signal 327. The final cell detection circuit 13 analyzes the ATM cell 326 and outputs a low-level final cell detection signal 323 because it is not the last cell. The packet identification bit output circuit 14 outputs a low-level packet identification bit signal 324, but since the last cell detection circuit 13 outputs a low-level final cell detection signal 323, the low-level packet identification bit The output of the bit signal 324 is maintained. Therefore, the intermediate cell generation circuit 15 outputs the low-level packet identification bit signal 324 output from the packet identification bit output circuit 14, that is, the packet identification bit “0”, to the corresponding ATM cell 3.
26 to generate an intermediate cell 328. Then, the intermediate cell 328 is input to the ATM switch 16 following the previous intermediate cell 320.

The ATM cell 3 shown in FIG.
When 29 is input, the destination identifier detection circuit 12 analyzes this and detects VPI and VCI. Where V
Since PI = “VP2” and VCI = “VC1” are detected, the destination identifier detection circuit 12 outputs a low-level destination identifier selection signal 330. Due to the low-level destination identifier selection signal 330, the ATM cell 329 is excluded from the processing of each subsequent circuit.

A series of ATMs shown in FIG.
When the cell 331 is input, the destination identifier detection circuit 12
Analyzes these to detect VPI and VCI.
Here, VPI = “VP1” and VCI = “VC1”
Is detected, the destination identifier detection circuit 12 outputs the high-level destination identifier selection signal 332 again. The last cell detection circuit 13 analyzes the ATM cell 331 and determines that the cell is not the last cell.
Is output. The packet identification bit output circuit 14 outputs a low-level packet identification bit signal 324, but since the last cell detection circuit 13 outputs a low-level final cell detection signal 323, the low-level packet identification bit The output of the bit signal 324 is maintained. Therefore, the intermediate cell generation circuit 15 multiplexes the low-level packet identification bit signal 324 output from the packet identification bit output circuit 14, that is, the packet identification bit “0”, with a corresponding series of ATM cells 331 to form a series of An intermediate cell 333 is generated. Then, a series of these intermediate cells 333 are input to the ATM switch 16 following the previous intermediate cell 328.

The ATM cell 3 shown in FIG.
When 34 is input, the destination identifier detection circuit 12 analyzes this to detect VPI and VCI. Where V
Since PI = “VP2” and VCI = “VC1” are detected, the destination identifier detection circuit 12 outputs a low-level destination identifier selection signal 335. Due to the low-level destination identifier selection signal 335, the ATM cell 334 is excluded from processing by the subsequent circuits. The following ATM cell 33
6, VPI = “VP1” and VCI = “V
Since it is C2 ", it is similarly excluded from the processing of the subsequent circuits.

The ATM cell 3 shown in FIG.
When 37 is input, the destination identifier detection circuit 12 analyzes this to detect VPI and VCI. Where V
Since PI = “VP1” and VCI = “VC1” are detected, the destination identifier detection circuit 12 outputs the high-level destination identifier selection signal 338 again. The final cell detection circuit 13 analyzes the ATM cell 337 and outputs a low-level final cell detection signal 323 because it is not the last cell. Although the packet identification bit output circuit 14 outputs the low-level packet identification bit signal 324, the last cell detection circuit 13 outputs the low-level last cell detection signal 32.
3, the output of the low-level packet identification bit signal 324 is maintained as it is. Therefore, the intermediate cell generation circuit 15 outputs the packet identification bit output circuit 14
Low-level packet identification bit signal 3 output from
24, ie, the packet identification bit “0” and the corresponding A
The intermediate cell 339 is generated by multiplexing with the TM cell 337. Then, the intermediate cell 339 is input to the ATM switch 16 following the series of intermediate cells 333.

The ATM cell 3 shown in FIG.
When 40 is input, the destination identifier detection circuit 12 analyzes this to detect VPI and VCI. Where V
Since PI = “VP1” and VCI = “VC1” are detected, the destination identifier detection circuit 12 outputs a high-level destination identifier selection signal 338. Last cell detection circuit 1
Numeral 3 analyzes the ATM cell 340 and outputs a high-level final cell detection signal 341 because it is the last cell located at the end of the original packet. The packet identification bit output circuit 14 outputs a low-level packet identification bit signal 32.
4 is output, but since the last cell detection circuit 13 outputs the high-level final cell detection signal 341, the output of the low-level packet identification bit signal 324 is maintained while the last cell detection signal 341 is output. Start monitoring for falling. Therefore, the intermediate cell generation circuit 15 multiplexes the low-level packet identification bit signal 324 output from the packet identification bit output circuit 14, that is, the packet identification bit “0”, and the corresponding ATM cell 340 to form the intermediate cell 342. Generate. And, this intermediate cell 342
Is input to the ATM switch 16 following the intermediate cell 339.

(Fourth packet: packet identification bit =
1) When the ATM cell 343 shown in FIG. 4 is input from the input terminal 11, the destination identifier detection circuit 12 analyzes this and detects VPI and VCI. Here VPI =
Since “VP1” and VCI = “VC1” are detected, the destination identifier detection circuit 12 outputs a high-level destination identifier selection signal 338. The final cell detection circuit 13 analyzes the ATM cell 343 and outputs a low-level final cell detection signal 344 because it is not the last cell. The packet identification bit output circuit 14 sets the low-level packet identification bit signal 324 to high when the last cell detection circuit 13 causes a fall from the high-level final cell detection signal 341 to the low-level final cell detection signal 344. Invert to the level packet identification bit signal 345. Therefore, the intermediate cell generation circuit 15 multiplexes the high-level packet identification bit signal 345 output from the packet identification bit output circuit 14, that is, the packet identification bit “1”, with the corresponding ATM cell 343 to form the intermediate cell 346. Generate. Then, this intermediate cell 346
Is input to the ATM switch 16 following the intermediate cell 342.

The ATM cell 3 shown in FIG.
When 47 is input, the destination identifier detection circuit 12 analyzes this to detect VPI and VCI. Where V
Since PI = “VP1” and VCI = “VC2” are detected, the destination identifier detection circuit 12 outputs a low-level destination identifier selection signal 348. By this low-level destination identifier selection signal 348, the ATM cell 347 is excluded from the processing of each subsequent circuit.

The ATM cell 3 shown in FIG.
When 49 is input, the destination identifier detection circuit 12 analyzes this and detects VPI and VCI. Where V
Since PI = “VP1” and VCI = “VC1” are detected, the destination identifier detection circuit 12 outputs the high-level destination identifier selection signal 350 again. The final cell detection circuit 13 analyzes the ATM cell 349 and outputs a low-level final cell detection signal 344 because it is not the last cell. Although the packet identification bit output circuit 14 outputs the high-level packet identification bit signal 345, the last cell detection circuit 13 outputs the low-level last cell detection signal 34.
4, the output of the high-level packet identification bit signal 345 is maintained as it is. Therefore, the intermediate cell generation circuit 15 outputs the packet identification bit output circuit 14
High-level packet identification bit signal 3 output from
45, ie, the packet identification bit “1” and the corresponding A
The intermediate cell 351 is generated by multiplexing with the TM cell 349. The intermediate cell 351 is the same as the intermediate cell 34.
Subsequent to 3, it is input to the ATM switch 16.

(Summary of Circuit Operation Prior to ATM Switch 16) The destination identifier detection circuit 12, the last cell detection circuit 13, the packet identification bit output circuit 14, and the intermediate cell generation circuit 15 in the network congestion suppression device of the present embodiment described above. 3 (e) and FIG.
A plurality of intermediate cells shown in (e) are obtained and input to the ATM switch 16 in time series. These intermediate cells are:
A series of intermediate cells 352 up to the last cell 307 where the packet identification bit signal “0” is multiplexed, and a series of intermediate cells from the top cell 311 to the last cell 320 where the packet identification bit signal “1” is multiplexed 353, a series of intermediate cell groups 354 from the first cell 328 multiplexed with the packet identification bit signal "0" to the last cell 342, and the first cell 346 multiplexed with the packet identification bit signal "1".
It can be classified into the following series of intermediate cell groups 355.

(Circuit Operation After the ATM Switch 16) FIGS. 5 and 6 are diagrams for explaining the circuit operation performed after the ATM switch 16 of the network congestion suppressing apparatus of this embodiment. FIG. 5 shows data or signals belonging to the first half of a series of time series in circuit operation, and FIG. 6 shows data or signals belonging to the latter half of a series of time series in circuit operation. 5A and 6A, (a) shows an intermediate cell group output from the ATM switch 16 and input to the intermediate cell check circuit 17, and (b) shows a packet identification bit extraction signal output from the packet identification bit extraction circuit 21. To
(C) shows the accumulation amount of the intermediate cells output from the accumulation amount detection unit 25 in the cell buffer 23, (d) shows the EPD control signal output from the cell buffer control unit 24, and (e) shows the cell buffer control unit 24. Shows the cell write address stored and output to the cell buffer 23, (f) shows the packet start address stored and used by the cell buffer control unit 24,
(G) shows, in chronological order, the intermediate cell groups in the intermediate cell check circuit 17 and waiting for transmission stored in the cell buffer 23. Note that FIG. 5A and FIG.
The plurality of intermediate cells input in chronological order from the ATM switch 16 shown in (a) are shown in FIGS. 3 (e) and 4 (e).
2 corresponds to a plurality of intermediate cells input in time series to the ATM switch 16 shown in FIG.

(Set of packet start address) The cell buffer control unit 24 controls the intermediate cell shown in FIG. 5 corresponding to the cell located at the head of the packet including the ATM cell 300 shown in FIG. 391, the intermediate cell 391 is stored in the cell buffer 23.
Of the cell write address 392 at the time of writing to
1 "is held as the packet start address 405 of this packet. All intermediate cells newly input from the ATM switch 16 are in accordance with the cell write address and the packet start address held by the cell buffer control unit 24. , Cell buffer 2 in packet units
3 or discarded by overwriting in packet units.

(First packet: discarded due to last cell loss) The ATM switch 16 to the intermediate cell 400 shown in FIG.
Is input, the packet identification bit extraction circuit 21
By analyzing this, the multiplexed packet identification bit “0” is extracted, and a low-level packet identification bit extraction signal 401 corresponding to the packet identification bit “0” is output. The destination identifier extraction circuit 22 includes an intermediate cell 400
Is analyzed to extract VPI and VCI, and VPI = “V
P1 "and a destination identifier extraction signal indicating that VCI =" VC1 ". The storage amount detection unit 25 stores the intermediate cell input before the intermediate cell 400 in the cell buffer 23 at that time. The amount is detected, and an accumulation amount detection signal shown in FIG.

The cell buffer control unit 24 compares the storage amount of the intermediate cell corresponding to the storage amount detection signal in the cell buffer 23 with a predetermined congestion threshold amount 402. Then, at this time, the accumulated amount of the intermediate cell is equal to the congestion threshold amount 4
02, and outputs a low-level EPD control signal 403 indicating that EPD control is not performed. The cell buffer control unit 24 determines whether or not the packet identification bit extraction signal 401 output from the packet identification bit extraction circuit 21 is equal to the packet identification bit extraction signal output according to the intermediate cell input immediately before. judge. In this determination, the packet identification bit extraction signal 40
1 is equal to the immediately preceding packet identification bit extraction signal. In this case, the cell buffer control unit 24 increments from the immediately preceding value as the cell write address 404 necessary for writing the input intermediate cell 400 into the cell buffer 23. The value “813” obtained as a result is held. And
The cell buffer control unit 24 controls the low-level EP described above.
The cell write address 404 is output together with the D control signal 403.

The cell buffer 23 has a low-level EPD control signal 403 output from the cell buffer controller 24.
And cell write address 404, AT
The intermediate cell 400 input from the M switch 16 is stored in the address “813”. However, as described later, the intermediate cell 400 is discarded by overwriting.

The intermediate cell 406 which should be continuously input to the above-described intermediate cell 400 is the ATM switch 16
Nothing is stored in the cell buffer 23 because it was lost due to congestion and the like and was not input.

(Second packet: stored in cell buffer)
When the intermediate cell 407 shown in FIG. 5 is input from the ATM switch 16, the packet identification bit extraction circuit 21 analyzes this and multiplexes the packet identification bit "1".
, And outputs a high-level packet identification bit extraction signal 408 corresponding to the packet identification bit “1”. The destination identifier extraction circuit 22 analyzes the intermediate cell 407 to extract VPI and VCI, and VPI = “VP1”
And outputs a destination identifier extraction signal indicating that VCI = "VC1". The storage amount detection unit 25 detects the storage amount of the intermediate cell input before the intermediate cell 407 in the cell buffer 23 at that time, and
An accumulation amount detection signal shown in (c) is output.

The cell buffer control unit 24 compares the storage amount of the intermediate cell corresponding to the storage amount detection signal in the cell buffer 23 with a predetermined congestion threshold amount 402. Then, at this time, the accumulated amount of the intermediate cell is equal to the congestion threshold amount 4
02, the output of the low-level EPD control signal 403 indicating that EPD control is not performed is maintained. The cell buffer control unit 24 determines whether the packet identification bit extraction signal 408 output from the packet identification bit extraction circuit 21 is equal to the packet identification bit extraction signal 401 output according to the intermediate cell input immediately before. Is determined. In this determination, the high-level packet identification bit extraction signal 408 and the low-level packet identification bit extraction signal 401 are not equal. In this case, the cell buffer control unit 24 further determines that the intermediate cell 400 input immediately before is It is determined whether or not it is generated corresponding to the last cell. In this determination, since the intermediate cell 400 is not generated corresponding to the last cell, the cell buffer control unit 24 sets the cell write address 409 necessary for writing the input intermediate cell 407 to the cell buffer 23. , "811" which is the value of the packet head address 405 stored earlier is stored. Then, the cell buffer control unit 24 outputs the cell write address 409 together with the low-level EPD control signal 403 described above. The cell buffer control unit 24
Is "811" as the packet start address 410 corresponding to the write address of the original ATM cell corresponding to the intermediate cell 407, that is, the cell located at the head of the packet having the ATM cell 308 shown in FIG. Hold.

The cell buffer 23 has a low-level EPD control signal 403 output from the cell buffer controller 24.
And cell write address 409, AT
The intermediate cell 407 input from the M switch 16 is stored at the address “811”. Therefore, the packet having the intermediate cell 400 stored earlier as an element is the intermediate cell 4
The cells after 07 are discarded by overwriting.

When the series of intermediate cells 411 shown in FIG. 5 is input from the ATM switch 16, the packet identification bit extraction circuit 21 analyzes these and extracts the multiplexed packet identification bit "1". A high-level packet identification bit extraction signal 408 corresponding to the packet identification bit “1” is output. The destination identifier extraction circuit 22
A series of intermediate cells 411 are analyzed to extract VPI and VCI, and VPI = “VP1” and VCI = “VC1”
Is output. The storage amount detection unit 25 detects the storage amount of the intermediate cells input before the intermediate cells 411 in the cell buffer 23 at that time, and outputs a storage amount detection signal shown in FIG.

The cell buffer control unit 24 compares the accumulation amount of the intermediate cell corresponding to the accumulation amount detection signal in the cell buffer 23 with a predetermined congestion threshold amount 402. Then, at this time, the accumulated amount of the intermediate cell is equal to the congestion threshold amount 4
02, the output of the low-level EPD control signal 403 indicating that EPD control is not performed is maintained. The cell buffer control unit 24 determines whether the packet identification bit extraction signal 408 output from the packet identification bit extraction circuit 21 is equal to the packet identification bit extraction signal 408 output according to the intermediate cell 407 input immediately before. Is determined. In the present determination, the cell buffer control unit 24 naturally increments from the immediately preceding value as a series of cell write addresses 412 necessary for writing the input series of intermediate cells 411 into the cell buffer 23. "812" obtained by
“813”, “814”, “815”, “816”,
“817” and “818” are stored in time series. Then, the cell buffer control unit 24 outputs a series of these cell write addresses 412 together with the low-level EPD control signal 403 described above. The cell buffer control unit 24 writes the write address of the original ATM cell corresponding to the series of intermediate cells 411, that is, the cell located at the head of the packet including the series of ATM cells 315 and 318 shown in FIG. "811" is continuously held as the packet start address 410 corresponding to.

The cell buffer 23 has a low-level EPD control signal 403 output from the cell buffer controller 24.
And a series of intermediate cells 411 input from the ATM switch 16 in accordance with the series of cell write addresses 412 and addresses “812”, “813”, “81”.
4 "," 815 "," 816 "," 817 "," 81 "
8 ".

(Third packet: discarded when congestion threshold is exceeded) From ATM switch 16 to intermediate cell 413 shown in FIG.
Is input, the packet identification bit extraction circuit 21
By analyzing this, the multiplexed packet identification bit “0” is extracted, and a low-level packet identification bit extraction signal 414 corresponding to the packet identification bit “0” is output. The destination identifier extracting circuit 22 is provided with the intermediate cell 413
Is analyzed to extract VPI and VCI, and VPI = “V
P1 ”and a destination identifier extraction signal indicating that VCI =“ VC1. ”The storage amount detection unit 25 stores the intermediate cell input before the intermediate cell 413 in the cell buffer 23 at that time. The amount is detected, and an accumulation amount detection signal shown in FIG.

The cell buffer control unit 24 compares the storage amount of the intermediate cell corresponding to the storage amount detection signal in the cell buffer 23 with a predetermined congestion threshold amount 402. Then, at this time, the accumulated amount of the intermediate cell is equal to the congestion threshold amount 4
02, the output of the low-level EPD control signal 403 indicating that EPD control is not performed is maintained. In addition, the cell buffer control unit 24 controls the series of intermediate cells 411 to which the packet identification bit extraction signal 414 output from the packet identification bit extraction circuit 21 is input immediately before.
Packet identification bit extraction signal 408 output according to
It is determined whether it is equal to or not. In the present determination, it is naturally not equal, and in this case, the cell buffer control unit 24
Further, it is determined whether or not the last intermediate cell of the series of intermediate cells 411 input immediately before is generated corresponding to the last cell. In this judgment, the corresponding intermediate cell was generated corresponding to the last cell,
The cell buffer control unit 24 receives the input intermediate cell 413
Is stored as a cell write address 415 necessary for writing the data into the cell buffer 23. Then, the cell buffer control unit 24 outputs the cell write address 415 together with the low-level EPD control signal 403 described above. The cell buffer control unit 24 determines the original ATM cell corresponding to the intermediate cell 413, that is, the packet start address corresponding to the write address of the cell located at the head of the packet including the ATM cell 326 shown in FIG. As the address 416, a value “819” equal to the cell write address 415 at this time is held.

The cell buffer 23 has a low level EPD control signal 403 output from the cell buffer controller 24.
And cell write address 415, AT
The intermediate cell 413 input from the M switch 16 is stored at the address “819”. However, as described later, the intermediate cell 413 is discarded by overwriting.

When a series of intermediate cells 417 shown in FIG. 6 is input from the ATM switch 16, the packet identification bit extraction circuit 21 analyzes these and extracts the multiplexed packet identification bit "0". A low-level packet identification bit extraction signal 414 corresponding to the packet identification bit “0” is output. The destination identifier extraction circuit 22
A series of intermediate cells 417 are analyzed to extract VPI and VCI, and VPI = “VP1” and VCI = “VC1”
Is output. The accumulation amount detection unit 25 detects the accumulation amount of the intermediate cells input before the intermediate cells 417 in the cell buffer 23 at that time, and outputs an accumulation amount detection signal shown in FIG.

The cell buffer control unit 24 compares the storage amount of the intermediate cell corresponding to the storage amount detection signal in the cell buffer 23 with a predetermined congestion threshold amount 402. Then, at this time, the accumulated amount of the intermediate cell is equal to the congestion threshold amount 4
02, the output of the low-level EPD control signal 403 indicating that EPD control is not performed is maintained. The cell buffer control unit 24 determines whether the packet identification bit extraction signal 414 output from the packet identification bit extraction circuit 21 is equal to the packet identification bit extraction signal 414 output in response to the intermediate cell 413 input immediately before. Is determined. In this determination, the cell buffer control unit 24 naturally increments from the immediately preceding value as a series of cell write addresses 418 necessary for writing the input series of intermediate cells 417 into the cell buffer 23. "820" obtained by
“821” and “822” are stored in time series. Then, the cell buffer control unit 24 outputs a series of these cell write addresses 418 together with the low-level EPD control signal 403 described above. The cell buffer control unit 24 determines the original ATM cell corresponding to the series of intermediate cells 417, that is, the cell located at the head of the packet having a part of the series of ATM cells 331 shown in FIG. "819" is continuously held as the packet start address 416 corresponding to the write address of.

The cell buffer 23 has a low-level EPD control signal 403 output from the cell buffer controller 24.
And a series of intermediate cells 417 inputted from the ATM switch 16 in accordance with the series of cell write addresses 418 and the addresses "820", "821", "822".
Accumulate in each. However, as described later, these intermediate cells 418 will be discarded by overwriting.

(Detection of Congestion Threshold Exceed) ATM Switch 1
When the intermediate cell 419 shown in FIG. 6 is input from FIG. 6, the packet identification bit extraction circuit 21 analyzes this and extracts the multiplexed packet identification bit “0”, and this packet identification bit “0”. Is output as a low-level packet identification bit extraction signal 414 corresponding to. The destination identifier extracting circuit 22 analyzes the intermediate cell 419 to extract VPI and VCI, and VPI = “VP1” and VCI =
It outputs a destination identifier extraction signal indicating "VC1". The accumulation amount detection unit 25 detects the accumulation amount of the intermediate cell input before the intermediate cell 419 in the cell buffer 23 at that time, and outputs an accumulation amount detection signal shown in FIG.

The cell buffer control unit 24 compares the storage amount of the intermediate cell corresponding to the storage amount detection signal in the cell buffer 23 with a predetermined congestion threshold amount 402. At this time, as indicated by reference numeral 420 in FIG. 5, since the accumulated amount of the intermediate cells exceeds the congestion threshold amount 402, a high-level EPD indicating that the EPD control is to be performed is performed.
The control signal 421 is output. Then, the cell buffer control unit 24 outputs the high-level EPD control signal 421, but stops outputting the cell write address. Note that the packet head address 416 is held as it is.

The cell buffer 23 has a high level EPD control signal 421 output from the cell buffer controller 24.
, The intermediate cell 419 input from the ATM switch 16 is discarded without being stored. As described above, the process of discarding the input intermediate cell without storing it is performed by the intermediate cell 4
The packet identification bits multiplexed in the new intermediate cell subsequent to 19 are inverted and the packet identification bit extraction circuit 21
Until the packet identification bit extraction signal output from the above becomes a high level, a series of input intermediate cells 422 are similarly performed.

(Fourth packet: stored in cell buffer)
When the intermediate cell 423 shown in FIG. 6 is input from the ATM switch 16, the packet identification bit extraction circuit 21 analyzes this and multiplexes the packet identification bit “1”.
, And outputs a high-level packet identification bit extraction signal 424 corresponding to the packet identification bit “1”. The destination identifier extracting circuit 22 analyzes the intermediate cell 423 to extract VPI and VCI, and VPI = “VP1”
And outputs a destination identifier extraction signal indicating that VCI = "VC1". The storage amount detection unit 25 detects the storage amount of the intermediate cell input before the intermediate cell 423 in the cell buffer 23 at that time, and FIG.
An accumulation amount detection signal shown in (c) is output.

The cell buffer control section 24 compares the storage amount of the intermediate cell corresponding to the storage amount detection signal in the cell buffer 23 with a predetermined congestion threshold amount 402. Then, at this time, the accumulated amount of the intermediate cell is equal to the congestion threshold amount 4
02, the output is switched from a high-level EPD control signal 421 indicating that EPD control is to be performed to a low-level EPD control signal 425 indicating that EPD control is not to be performed. The cell buffer control unit 24
Is a cell write address 426 required for writing the input intermediate cell 423 to the cell buffer 23.
The value “819” which is the value of the packet start address 416 stored earlier is stored. Then, the cell buffer control unit 24 outputs the low-level EPD control signal 425 described above.
At the same time, the cell write address 426 is output. In addition, the cell buffer control unit 24 determines that the intermediate cell 423
, Ie, the AT cell shown in FIG.
“819” is held as the packet head address 427 corresponding to the write address of the cell located at the head of the packet having the M cell 343 as one element.

The cell buffer 23 has a low-level EPD control signal 425 output from the cell buffer controller 24.
And cell write address 426, AT
The intermediate cell 423 input from the M switch 16 is stored at the address “819”. Therefore, a packet having a series of intermediate cells 413 and 417 stored earlier as elements is stored in intermediate cells 428 input after intermediate cell 423.
Cells will be discarded by overwriting.

(Summary of Circuit Operation After the ATM Switch 16) The packet identification bit extraction circuit 21, the destination identifier extraction circuit 22, the cell buffer 23, and the like in the intermediate cell check circuit 17 in the network congestion suppression device of the present embodiment described above. Cell buffer controller 24, storage amount detector 2
5 (g) and 6 (g) as a result of the circuit operation according to FIG.
Are stored in the cell buffer 23 in time series. In these intermediate cells, the packet identification bit signal “1” is multiplexed and addresses “812” to “81” are multiplexed.
8), a series of intermediate cell groups 429 and a packet identification bit signal “1” are multiplexed into an address “819”.
A series of intermediate cell groups 430 stored thereafter.

(Transmission of Intermediate Cells Stored in Cell Buffer) FIG. 7 is a diagram for explaining a read operation in the cell buffer 23 of the network congestion suppressing apparatus according to the present embodiment. As described above, the plurality of intermediate cells accumulated in the cell buffer 23 in time series are transmitted to the network according to the accumulation order under the control of the cell buffer control unit 24, as shown in FIG. That is, after the cell 501 which is the intermediate cell 407 shown in FIG. 4 is first output from “811” of the cell read address 500, the cell read addresses are changed to “812”, “813”,
.., And each cell is read out by incrementing sequentially like “820” and transmitted to the network.

In this embodiment, the destination identifier detection circuit 12 determines that VPI = “VP1” and VCI = “VC1”
, A high-level destination identifier selection signal is output, and each circuit provided after the destination identifier detection circuit 12 The description has simply been given assuming that the given ATM cell is to be processed only when the identifier selection signal is being output. However, for example, the destination identifier detection circuit 12 may be provided for each VPI and VCI. It is also possible to perform the processing for each destination identifier simultaneously and in parallel.

(Other Embodiment: A Plurality of Intermediate Cell Check Circuits are Paralleled) FIG. 8 is a block diagram showing the overall configuration of a network congestion suppressing device according to another embodiment of the present invention. The same parts as those described above are denoted by the same reference numerals. In the present embodiment, three systems of intermediate cell check circuits 17a, 17b, and 17c, all having the same configuration, are provided in parallel.
It is characterized in that output terminals 18a, 18b, 18c for transmitting cells from a, 17b, 17c to different networks are provided. With this configuration, each of the intermediate cell check circuits 17a, 17b, and 17c is optimized according to the characteristics of the destination network and the characteristics of the packet to be transmitted and the cells divided and generated from the packet. Can be.

[0077]

As described above, according to the first to sixth aspects of the present invention, the identification information extracted from the sorted intermediate cells by the identification information extracting means is the same and forms the same packet. A part of the series of cells considered to be lost is discarded, and a complete cell without any loss is sent to the network, so that the boundary cell is lost due to congestion of the distribution means. Even if a packet is lost, it is possible to discriminate between the preceding and succeeding packets and to reliably discard only cells forming an abnormal packet. Therefore, network resources are wasted due to communication accompanying a retransmission request for two packets due to packet confusion. Occupied by network resources, and network resources can be used efficiently.

Further, according to the third or fourth aspect of the present invention, the identification information to be integrated with the cell is one of two types of first value and second value, for example, “0” and “1”. ", The transmission amount of information is not greatly increased at the time of implementation, and the practicability is excellent.

Further, according to the fifth aspect of the present invention, in the first to fourth aspects of the present invention, only normal packets stored in the cell buffer of all cells can be transmitted to the network, so The meaningless packets are no longer transmitted on the network, and the occurrence of congestion due to data transmission on the network can be suppressed, and the reliability of the transmission path can be improved.

Further, according to the invention of claim 6, in the invention of claim 5, when the accumulated amount of the intermediate cells in the cell buffer exceeds a predetermined congestion threshold amount smaller than the capacity of the cell buffer, It is possible to discard a series of intermediate cells in which the entire series of intermediate cells forming the same packet has not yet been accumulated, suppress the occurrence of congestion due to the capacity of the cell buffer, and improve the reliability of the transmitting node. Can be improved.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating an overall configuration of a network congestion suppression device according to an embodiment of the present invention.

FIG. 2 is a block diagram illustrating a detailed configuration of an intermediate cell check circuit of the network congestion suppression device according to the embodiment.

FIG. 3 shows an AT of the network congestion suppressing apparatus according to the embodiment.
FIG. 4 is a timing chart (first half) for explaining a circuit operation in a stage preceding the M switch;

FIG. 4 shows an AT of the network congestion suppressing apparatus according to the embodiment.
FIG. 9 is a timing chart (second half) for explaining the operation of a circuit preceding the M switch;

FIG. 5 illustrates an AT of the network congestion suppression device according to the present embodiment.
FIG. 4 is a timing chart (first half) for explaining a circuit operation at a stage subsequent to the M switch.

FIG. 6 illustrates an AT of the network congestion suppression device according to the present embodiment.
FIG. 9 is a timing chart (second half) for explaining a circuit operation subsequent to the M switch;

FIG. 7 is a timing chart for explaining a read operation in a cell buffer of the network congestion suppression device of the present embodiment.

FIG. 8 is a block diagram showing an overall configuration of a network congestion suppressing device according to another embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 11 Input terminal 12 Destination identifier detection circuit 13 Last cell detection circuit 14 Packet identification bit output circuit 15 Intermediate cell generation circuit 16 ATM switch 17 Intermediate cell check circuit 18 Output terminal 21 Packet identification bit extraction circuit 22 Destination identifier extraction circuit 23 Cell buffer 24 Cell buffer controller 25 Storage amount detector

────────────────────────────────────────────────── ─── Continuation of front page (56) References JP-A-3-135248 (JP, A) JP-A-7-66807 (JP, A) JP-A-10-51458 (JP, A) JP-A-10-108 190679 (JP, A) JP-A-10-290234 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB name) H04L 12/28

Claims (6)

(57) [Claims] 1. An identification information output for outputting a plurality of cells forming a packet from a packet which is a logical data unit and outputting identification information different from other packets before and after the packet. Means, intermediate cell generating means for generating a plurality of intermediate cells each integrating the identification information output by the identification information output means and a plurality of cells generated from the corresponding packet, except when congestion occurs, Distribution means for distributing the intermediate cells generated by the cell generation means for each destination; identification information extraction means for extracting identification information from the intermediate cells allocated by the distribution means; and identification information extracted by the identification information extraction means. Discards a series of intermediate cells in which a series of identical cells are missing some of the cells forming the packet Congestion suppression devices of the network, characterized by comprising a sending node and a cell discard sending processing means for performing processing of transmitting a series of intermediate cells other than this to the network. 2. A method for monitoring a plurality of cells forming a packet, which is a logical data unit, and detecting a boundary cell for distinguishing successive packets from each other based on a value of a boundary identifier held by the boundary cell. When a large number of cells forming a plurality of packets are provided, each time the boundary cell detection means detects a boundary cell, the identification information determined to be different before and after the detection is output. Identification information output means, intermediate cell generation means for generating an intermediate cell integrating the identification information output by the identification information output means and the corresponding cell, and the intermediate cell generation means generates the intermediate cell except when congested. Allocating means for allocating intermediate cells by destination, and identification information extracting means for extracting identification information from the intermediate cells allocated by the allocating means Among a series of cells having the same identification information extracted by the identification information extracting means, a series of intermediate cells in which a part of a plurality of cells forming a packet are missing are discarded, and a series of intermediate cells other than this are discarded. A congestion suppression device for a network, comprising: a transmitting-side node; 3. The identification information output by the identification information output means includes a predetermined first value and a predetermined second value.
The network congestion suppression device according to claim 1 or 2, wherein the value is one of the following values: 4. An identification which always outputs one of a predetermined first value and a second value as identification information, and outputs according to a switching instruction signal indicating an instruction to switch the value of the identification information. Identification information output means for alternately switching the value of information; and a plurality of cells each integrating the identification information output by the identification information output means with a plurality of cells forming a packet determined from a packet which is a logical data unit. And an intermediate cell generating means for outputting the switching instruction signal when a packet is newly given; and distributing the intermediate cells generated by the intermediate cell generating means to each destination except when congested. Assigning means; identifying information extracting means for extracting identification information from the intermediate cells assigned by the assigning means; Among a series of cells having the same identification information extracted by the identification information extracting means, a series of intermediate cells in which a part of a plurality of cells forming a packet are missing are discarded, and a series of intermediate cells other than this are discarded. And a cell discarding transmission processing means for performing processing for transmitting the packet to the network. 5. The cell discarding transmission processing means forms a cell buffer for temporarily storing intermediate cells allocated by the distribution means, and the same packet among the intermediate cells stored in the cell buffer. 5. The network congestion suppression device according to claim 1, further comprising: a cell buffer control unit for transmitting a series of intermediate cells in which a plurality of cells are all stored in accordance with the storage order. 6. The cell discard / transmission processing means has an accumulation amount detection unit for detecting an accumulation amount of an intermediate cell in the cell buffer, and the cell buffer control unit detects the intermediate amount detected by the accumulation amount detection unit. When the storage amount of cells exceeds a predetermined congestion threshold amount, a series of intermediate cells in which some of the plurality of cells forming the same packet are not stored among the intermediate cells stored in the cell buffer. 6. The apparatus according to claim 5, wherein all cells are discarded.