JP2924320B2 - Hybrid IC - Google Patents
Hybrid ICInfo
- Publication number
- JP2924320B2 JP2924320B2 JP3177366A JP17736691A JP2924320B2 JP 2924320 B2 JP2924320 B2 JP 2924320B2 JP 3177366 A JP3177366 A JP 3177366A JP 17736691 A JP17736691 A JP 17736691A JP 2924320 B2 JP2924320 B2 JP 2924320B2
- Authority
- JP
- Japan
- Prior art keywords
- circuit board
- chip
- semiconductor element
- hybrid
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
Description
【０００１】[0001]
【産業上の利用分野】本発明はハイブリッドＩＣに関
し、特に小型化を図るとともに実装構造の簡略化を図っ
たハイブリッドＩＣに関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a hybrid IC, and more particularly, to a hybrid IC that has a reduced size and a simplified mounting structure.
【０００２】[0002]
【従来の技術】従来のハイブリッドＩＣの一例を図３の
一部破断斜視図に示す。このハイブリッドＩＣは複数枚
の回路基板２１〜２５を多層に重ねて多層回路基板２０
を形成し、各回路基板に形成した回路パターンをスルー
ホール２、盲目型ＩＶＨ（Interstitial Via Hole ）
３、埋込型ＩＶＨ４で相互に電気接続して所要の回路を
構成する。又、最上層の回路基板２１には半導体素子チ
ップ５や各種チップ部品６を搭載し、ボンディングワイ
ヤ９による接続やフェースダウンによる接続等により電
気接続し、所要のハイブリッド回路を構成している。
尚、７は半導体素子チップ５を封止するための樹脂であ
る。2. Description of the Related Art An example of a conventional hybrid IC is shown in FIG. This hybrid IC is formed by stacking a plurality of circuit boards 21 to 25 in multiple layers,
Is formed, and the circuit pattern formed on each circuit board is inserted into a through-hole 2, blind IVH (Interstitial Via Hole).
3. A required circuit is formed by mutually electrically connecting the embedded type IVHs 4 to each other. Further, the semiconductor element chip 5 and various chip components 6 are mounted on the circuit board 21 of the uppermost layer, and are electrically connected by bonding wires 9 or face-down connections to form a required hybrid circuit.
Reference numeral 7 denotes a resin for sealing the semiconductor element chip 5.
【０００３】[0003]
【発明が解決しようとする課題】このような従来のハイ
ブリッドＩＣでは、積層回路基板２０の最上層の回路基
板２１に半導体素子チップ５や各種チップ部品６を搭載
するため、これらの搭載部品が表面に露呈された状態と
なる。このため、ハイブリッドＩＣの上側に凹凸が生じ
るとともに、全体の高さ寸法が大きくなり、ハイブリッ
ドＩＣを実装するためのスペースが大きく必要になると
いう問題がある。又、半導体素子チップ等が露呈されて
いることで、周囲の雑音に影響され易く、特に高周波信
号を取り扱う場合には、所要の信頼性を確保するために
は別にシールド構造が必要とされ、実装構造が複雑化す
るという問題がある。本発明の目的は小型化を図るとと
もに実装構造の簡略化を図ったハイブリッドＩＣを提供
することにある。In such a conventional hybrid IC, since the semiconductor element chip 5 and various chip components 6 are mounted on the circuit board 21 on the uppermost layer of the laminated circuit board 20, these mounted components are not provided on the surface. Is exposed. For this reason, there is a problem that unevenness is generated on the upper side of the hybrid IC, the entire height dimension is increased, and a large space for mounting the hybrid IC is required. In addition, since the semiconductor device chip and the like are exposed, the device is easily affected by ambient noise. In particular, when handling high-frequency signals, a separate shield structure is required to secure required reliability. There is a problem that the structure is complicated. An object of the present invention is to provide a hybrid IC that is reduced in size and has a simplified mounting structure.
【０００４】[0004]
【課題を解決するための手段】本発明のハイブリッドＩ
Ｃは、複数枚の回路基板を積層して積層回路基板を構成
し、前記複数枚の回路基板間に半導体素子チップや各種
チップ部品の位置に対応した開口を有する絶縁板を有
し、前記絶縁板の開口に前記半導体素子チップや各種チ
ップ部品の全てを埋設し、前記半導体素子チップや各種
チップ部品を前記回路基板に設けた回路パターンに電気
接続し、かつ最上層の回路基板の上面及び最下層の回路
基板の下面のそれぞれの全面にシールド用の導電膜を形
成してなるたことを特徴とする。また、前記半導体素子
チップや各種チップ部品と前記開口との間に生じる空隙
内に不活性ガスを充填したことを特徴とする。 SUMMARY OF THE INVENTION The hybrid I of the present invention
C is a laminated circuit board formed by laminating a plurality of circuit boards
And a semiconductor element chip and various
Insulation plate with openings corresponding to chip component positions
And said buried all the semiconductor element chip and various chip parts into the opening of the insulating plate, the semiconductor device chip and various
The chip component is electrically connected to a circuit pattern provided on the circuit board , and the upper and lower circuits of the uppermost circuit board are connected.
A conductive film for shielding is formed on the entire lower surface of the substrate.
It is characterized by having formed. In addition, the semiconductor element
Voids generated between chips and various chip components and the openings
The inside is filled with an inert gas.
【０００５】[0005]
【作用】本発明によれば、半導体素子チップや各種チッ
プ部品を積層回路基板内に埋設させ、積層回路基板内の
スペースの有効利用を図ってハイブリッドＩＣの小型化
を可能とし、かつ各部品の露呈を防止してシールド効果
を高め、実装構造の簡略化を可能とする。According to the present invention, a semiconductor element chip and various chip components are embedded in a laminated circuit board, and the space in the laminated circuit board can be effectively used to reduce the size of the hybrid IC. This prevents the exposure and enhances the shielding effect, thereby simplifying the mounting structure.
【０００６】[0006]
【実施例】次に、本発明について図面を参照して説明す
る。図１は本発明の一実施例の一部破断斜視図である。
同図のように複数枚の回路基板（ここでは４枚）１１〜
１４を積層して積層回路基板１を形成し、各回路基板１
１〜１４に設けた回路パターンをスルーホール２、盲目
型ＩＶＨ３、埋込型ＩＶＨ４で相互に電気接続し、所要
の回路を構成している。又、積層回路基板１の中間部に
は絶縁板１５を介挿するとともに、この絶縁板には開口
を形成し、この開口に臨む下側の回路基板１３に半導体
素子チップ５や各種チップ部品６を搭載し、かつ樹脂７
で封止することでこれらの部品が前記積層回路基板１の
内部に埋設されるように構成している。更に、この実施
例では最上層回路基板１１の上面と、最下層回路基板１
４の下面には夫々導電膜１６，１７を形成し、シールド
膜として構成している。Next, the present invention will be described with reference to the drawings. FIG. 1 is a partially cutaway perspective view of one embodiment of the present invention.
As shown in the figure, a plurality of circuit boards (here, four) 11 to 11
14 to form a laminated circuit board 1, and each circuit board 1
The circuit patterns provided in Nos. 1 to 14 are electrically connected to each other by through-holes 2, blind IVH3, and embedded IVH4 to form a required circuit. An insulating plate 15 is inserted in the middle of the laminated circuit board 1 and an opening is formed in the insulating plate, and the semiconductor element chip 5 and various chip components 6 are mounted on the lower circuit board 13 facing the opening. And resin 7
These components are buried inside the laminated circuit board 1 by being sealed with the above. Further, in this embodiment, the upper surface of the uppermost circuit board 11 and the lower
Conductive films 16 and 17 are respectively formed on the lower surface of 4 to constitute a shield film.
【０００７】図２は図１の構成を製造する方法を工程順
に示す断面図である。同図（ａ）のように、回路基板１
３の上面に設けた回路パターン１３ａの一部にバンプ１
３ｂを形成し、半導体素子チップ５のパターン面を下側
にしてフェースダウンボンディングにより搭載する。
又、図示は省略するが各種チップ部品も回路基板に搭載
する。そして、これら半導体素子チップやチップ部品に
相当する箇所に開口１５ａを設けた絶縁板１５を回路基
板１３上に重ね、接着する。次いで、同図（ｂ）のよう
に、絶縁板１５の開口部に樹脂７を注入し、半導体素子
チップやチップ部品を封止する。このとき、各部品の下
側の空隙には窒素８を充填させておくことが好ましい。FIG. 2 is a sectional view showing a method of manufacturing the structure of FIG. 1 in the order of steps. As shown in FIG.
3 has a bump 1 on a part of the circuit pattern 13a provided on the upper surface thereof.
3b is formed and mounted by face-down bonding with the pattern surface of the semiconductor chip 5 facing downward.
Although not shown, various chip components are also mounted on the circuit board. Then, an insulating plate 15 provided with an opening 15a at a position corresponding to these semiconductor element chips and chip components is overlaid on the circuit board 13 and bonded. Next, as shown in FIG. 3B, a resin 7 is injected into the opening of the insulating plate 15 to seal the semiconductor element chip and the chip component. At this time, it is preferable to fill the gaps below the respective components with nitrogen 8.
【０００８】次いで、同図（ｃ）のように、その上に回
路基板１２を重ね、接着する。以後、同様に回路基板を
重ねることで積層回路基板を形成する。このとき、図示
は省略するが、埋込型ＩＶＨにより各回路基板の回路パ
ターンを導通させる。その後、所要の枚数の回路基板を
重ね、スルーホールや盲目型ＩＶＨで夫々の回路パター
ンを電気接続することで、図１のハイブリッドＩＣが完
成される。Next, as shown in FIG. 1C, the circuit board 12 is stacked thereon and bonded. Thereafter, the circuit boards are similarly stacked to form a laminated circuit board. At this time, although not shown, the circuit pattern of each circuit board is made conductive by the embedded type IVH. Thereafter, a required number of circuit boards are stacked, and the respective circuit patterns are electrically connected by through holes or blind IVHs, whereby the hybrid IC of FIG. 1 is completed.
【０００９】このハイブリッドＩＣによれば、半導体素
子チップ５や各種チップ部品６は、多層回路基板１内に
埋設されるため、これらの部品が露呈されることはな
い。このため、積層回路基板１内の空間を有効利用し、
ハイブリッドＩＣの全体の高さを低減させ、小型化を図
ることができる。又、半導体素子チップ５等は積層回路
基板１内に埋設されるため、外部雑音が影響することは
少なく、電気的特性の安定化を図ることができる。特
に、この実施例では最上層及び最下層の各回路基板１
１，１４にシールド膜１６，１７を設けているので、実
装に際してのシールド構造が不要となり、実装構造の簡
略化を図ることができる。According to this hybrid IC, since the semiconductor element chip 5 and various chip components 6 are embedded in the multilayer circuit board 1, these components are not exposed. Therefore, the space in the multilayer circuit board 1 is effectively used,
The overall height of the hybrid IC can be reduced, and the size can be reduced. Further, since the semiconductor element chip 5 and the like are buried in the multilayer circuit board 1, external noise is less affected, and electrical characteristics can be stabilized. In particular, in this embodiment, the uppermost and lowermost circuit boards 1
Since the shield films 16 and 17 are provided on the first and the first 14, a shield structure for mounting is not required, and the mounting structure can be simplified.
【００１０】尚、複数枚の回路基板の夫々に半導体素子
チップや各種チップ部品を搭載させるように構成しても
よく、これにより各回路基板に形成する回路パターンの
簡易化を図ることもできる。[0010] It should be noted that a semiconductor element chip and various chip components may be mounted on each of a plurality of circuit boards, thereby simplifying a circuit pattern formed on each circuit board.
【００１１】[0011]
【発明の効果】以上説明したように本発明は、複数枚の
回路基板を積層して積層回路基板を構成し、前記複数枚
の回路基板間に半導体素子チップや各種チップ部品の位
置に対応した開口を有する絶縁板を有し、前記絶縁板の
開口に前記半導体素子チップや各種チップ部品の全てを
埋設し、前記半導体素子チップや各種チップ部品を前記
回路基板に設けた回路パターンに電気接続し、かつ最上
層の回路基板の上面及び最下層の回路基板の下面のそれ
ぞれの全面にシールド用の導電膜を形成しているので、
積層回路基板の空間を利用して部品の搭載ができ、ハイ
ブリッドＩＣの小型化が実現できるとともに、外部から
の雑音の影響を無くしてシールド構造等を不要にし、実
装構造の簡略化が達成できる効果がある。また、積層回
路基板内に充填した不活性ガスにより、チップに接続さ
れる電極が封止材と接触して劣化してチップ性能を低下
させることを防止することも可能である。 As described above, according to the present invention, a laminated circuit board is formed by laminating a plurality of circuit boards,
Of semiconductor device chips and various chip components between circuit boards
An insulating plate having an opening corresponding to the position of the insulating plate;
Wherein the opening is buried all the semiconductor element chip and various chip components, electrically connected to the circuit pattern provided with the semiconductor element chip and various chip components on the <br/> circuit board, and the top
On the upper surface of the circuit board of the layer and on the lower surface of the circuit board of the lowest layer
Since a conductive film for shielding is formed on each whole surface ,
The components can be mounted by utilizing the space of the laminated circuit board, and the size of the hybrid IC can be reduced. In addition, the effect of external noise can be eliminated, thereby eliminating the need for a shield structure or the like, thereby achieving the simplification of the mounting structure. There is. Also, the lamination times
Connected to the chip by the inert gas filled in the circuit board.
The electrode to be contacted with the encapsulant deteriorates and deteriorates the chip performance
It is also possible to prevent that.
【図１】本発明のハイブリッドＩＣの一実施例の一部破
断斜視図である。FIG. 1 is a partially broken perspective view of an embodiment of a hybrid IC according to the present invention.
【図２】（ａ）乃至（ｃ）は図１の構造を製造する工程
を示す断面図である。FIGS. 2A to 2C are cross-sectional views showing steps of manufacturing the structure of FIG.
【図３】従来のハイブリッドＩＣの一部破断斜視図であ
る。FIG. 3 is a partially cutaway perspective view of a conventional hybrid IC.
１ 積層回路基板 ２ スルーホール ３ 盲目型ＩＶＨ ４ 埋込型ＩＶＨ ５ 半導体素子チップ ６ 各種チップ部品 ７ 樹脂 ８ 窒素 REFERENCE SIGNS LIST 1 laminated circuit board 2 through hole 3 blind IVH 4 embedded IVH 5 semiconductor element chip 6 various chip parts 7 resin 8 nitrogen
フロントページの続き (56)参考文献 特開 平２−135802（ＪＰ，Ａ) 特開 平４−291984（ＪＰ，Ａ) 特開 平１−134995（ＪＰ，Ａ) 特開 昭51−62687（ＪＰ，Ａ) 特開 平４−315458（ＪＰ，Ａ) 特開 平４−359462（ＪＰ，Ａ) 特開 平４−233265（ＪＰ，Ａ) 実開 平３−6867（ＪＰ，Ｕ) (58)調査した分野(Int.Cl.6，ＤＢ名) H01L 25/00 - 25/18 H05K 3/46 Continuation of the front page (56) References JP-A-2-135802 (JP, A) JP-A-4-291984 (JP, A) JP-A-1-134995 (JP, A) JP-A-51-62687 (JP) JP-A-4-315458 (JP, A) JP-A-4-359462 (JP, A) JP-A-4-233265 (JP, A) JP-A-3-6867 (JP, U) Field surveyed (Int. Cl. 6 , DB name) H01L 25/00-25/18 H05K 3/46
Claims (2)
板を構成し、前記複数枚の回路基板間に半導体素子チッ
プや各種チップ部品の位置に対応した開口を有する絶縁
板を有し、前記絶縁板の開口に前記半導体素子チップや
各種チップ部品の全てを埋設し、前記半導体素子チップ
や各種チップ部品を前記回路基板に設けた回路パターン
に電気接続し、かつ最上層の回路基板の上面及び最下層
の回路基板の下面のそれぞれの全面にシールド用の導電
膜を形成してなるたことを特徴とするハイブリッドＩ
Ｃ。 1. A laminated circuit board comprising a plurality of circuit boards , wherein a semiconductor element chip is provided between the plurality of circuit boards.
Insulation with openings corresponding to the positions of pumps and various chip components
It has a plate, buried all of the semiconductor element chip and various chip parts into the opening of the insulating plate, the semiconductor element chip
And various chip components are electrically connected to the circuit pattern provided on the circuit board, and the upper and lower layers of the uppermost circuit board
Conductive shielding for the entire lower surface of the circuit board
Hybrid I characterized by forming a film
C.
と前記開口との間に生じる空隙内に不活性ガスを充填し
たことを特徴とする請求項１に記載のハイブリッドＩ
Ｃ。2. The semiconductor element chip and various chip parts.
Filled with an inert gas in the space created between
The hybrid I according to claim 1, wherein
C.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3177366A JP2924320B2 (en) | 1991-06-22 | 1991-06-22 | Hybrid IC |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3177366A JP2924320B2 (en) | 1991-06-22 | 1991-06-22 | Hybrid IC |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH04373157A JPH04373157A (en) | 1992-12-25 |
| JP2924320B2 true JP2924320B2 (en) | 1999-07-26 |
Family
ID=16029704
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3177366A Expired - Lifetime JP2924320B2 (en) | 1991-06-22 | 1991-06-22 | Hybrid IC |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2924320B2 (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3213292B2 (en) * | 1999-07-12 | 2001-10-02 | ソニーケミカル株式会社 | Multilayer board and module |
| JP3246502B2 (en) * | 2000-01-27 | 2002-01-15 | 松下電器産業株式会社 | Method for manufacturing component-embedded double-sided wiring board and method for manufacturing electronic circuit component |
| JP3420748B2 (en) | 2000-12-14 | 2003-06-30 | 松下電器産業株式会社 | Semiconductor device and manufacturing method thereof |
| JP2008166428A (en) * | 2006-12-27 | 2008-07-17 | Sanyo Electric Co Ltd | Circuit equipment and digital broadcasting receiver |
-
1991
- 1991-06-22 JP JP3177366A patent/JP2924320B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH04373157A (en) | 1992-12-25 |
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