JP2919148B2 - A / D converter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an A / D converter,
In particular, it relates to a circuit for correcting a quantization error.

[0002]

2. Description of the Related Art As shown in FIG. 4, a conventional A / D converter has an output of a transfer gate 3 having an input terminal C as an input and a transfer gate 4 having an input terminal D as an input.
To the terminal I, and the terminal I is connected to the capacitor CAP.
4 is connected to the input terminal F of the comparator CAP4, the terminal I is connected to the input terminal F of the comparator, two resistors R 'are serially connected between VCC and GND, The connection point connects to input terminal E,
The output of the transfer gate 5 having the input terminal E as an input is connected to the terminal J, the terminal J is connected to the capacitor CAP5, and the terminal connected to the reverse of the capacitor CAP5 connected to the terminal J is connected to the input terminal G of the comparator. Is done.

The transfer gate 7 connected to VCC and the output of the transfer gate 7 are connected to the input terminal F of the comparator, and the transfer gate 6 connected to VCC and the output of the transfer gate 6 are connected to the input terminal G of the comparator. . The resistance of the resistance value R is 2
n-1 are connected in series, one end of this series connected resistor is connected to GND via a resistor having a resistance value of R / 2, and the other end is connected to VCC at a resistance value of 3 × R / 2 via a second resistor.

The voltage at the connection point of each resistor is (VCC /
2 ⁿ ) × 1−VCC / 2 ^{n + 1} (connection point close to GND is 1
= 1, 1 = 1, 2,..., 2 ⁿ⁻¹ ), and these voltages are applied to the input terminal D via a selector controlled by the output of the comparator, and the analog input voltage (hereinafter referred to as VA) Is applied to the input terminal C.

FIG. 5 shows a configuration of a successive approximation type A / D converter having a resolution of 2 bits, which is an example of the A / D converter shown in FIG.
Shown in

VA is applied to the terminal C of the comparator section,
The voltage at the contact point of the resistor connected in series between VCC and GND is A1 = VCC / 4−VCC / 8, A2 = (VCC /
4) × 2-VCC / 8, A3 = (VCC / 4) × 3-V
CC / 8, and the selector applies one of the voltages of the contacts A1, A2, and A3 to the terminal D of the comparator according to the output of the comparator. (Here, the voltage of VCC / 8 is 1 / when 2-bit A / D conversion is performed on VCC.
This is a voltage corresponding to 2LSB, and VA and (VCC / 2 ⁿ ) × 1−VCC / 2 ^{n + 1 in the n} -bit A / D converter.
, A digital value can be obtained with a maximum voltage difference of VCC / 2 ^{n + 1} . Next, the resolution 2 in FIG.
The operation of the bit successive approximation type A / D converter will be described with reference to the operation timing of FIG.

(1) During sampling period ( t1 period )
When the transfer gates 3, 5, 6, and 7 are turned on and the transfer gate 4 is turned off, the analog input voltage VA is applied from the input terminal C and the terminal I
Becomes VA, the voltage VCC / 2 is applied from the input terminal E, the potential of the terminal J becomes VCC / 2, and the input terminals F and G of the comparator are precharged to VCC. Here, VCC = 5V, VA = 1V, and the capacitance CAP4
Assuming that the capacitance value of 5 is 1F, the capacitance CAP4 has a charge of 4C,
The charge of the capacitor CAP5 is maintained at 2.5C.

(2) A period (t) for obtaining a digital value for the analog signal input during the sampling period (t1)
During the period t2), the transfer gates 3, 6, 7 are turned off and the transfer gates 4, 5 are turned on during the period t2. Further, the selector selects the contact A2, a voltage of 1.875 V is applied to the input terminal D, the terminal I becomes 1.875 V, and the CAP4 has a charge of 4C.
Assuming that the parasitic capacitance of the input terminal F of the comparator is 0F, the input terminal F of the comparator is 5.87.
It becomes 5V. The potential of the input terminal G of the comparator remains at 5 V because the potentials of the input terminals E and J do not change, and the potential of the input terminal F becomes higher than that of the input terminal G. Therefore, the output OUT of the comparator outputs a logical “L”. (The digital value for an analog signal is determined to be logically “0” for the most significant bit.)

Next, during the period of t3, the output of the comparator is "L" during the period of t2.
1 is selected and a voltage of 0.625 V is applied to the input terminal D,
The terminal I becomes 0.625 V, and the parasitic capacitance of the input terminal F of the comparator is reduced to 0 to save the charge 4C of CAP4.
If F, the input terminal F of the comparator is 4.625V
Becomes The potential of the input terminal G of the comparator remains at 5 V because the potentials of the input terminals E and J do not change, and the potential of the input terminal F becomes lower than that of the input terminal G. Therefore, the output OUT of the comparator outputs a logical “H”. (The digital value for an analog signal is determined to be logically “1” for the least significant bit.) The above operation completes the conversion.

[0010]

In this conventional A / D converter, the resistance value R / 2 for reducing the quantization error to 1/2 LSB is compared with the resistance value obtained by combining the resistance R and the resistance R / 2. Must be made with a value of 1/2 ^{n + 1.}
The resistance value for forming ⁿ × R, 1/2 LSB is R / 2, 1
Assuming that the variation of the resistance value for forming / 2 LSB is r, the variation of 1/2 LSB of the n-bit A / D conversion is r /
(R / 2), but in the case of (n + 1) -bit A / D conversion when the resolution is increased by 1 bit, if the mask layout area does not change, the total resistance of the resistors connected in series between VCC and GND The value is the same as in nbit A / D conversion. Therefore, the resistance value of each resistor is nbitA / D
It must be made with half the value of the conversion,
Assuming that the variation of the resistance value for forming / LSB remains unchanged, the error of 1 / 2LSB is {r / (R / 2)} ×
2, which is a problem that the error of 1/2 LSB of the quantization error becomes larger than that in the case of n-bit A / D conversion.

FIG. 5 shows a 2-bit A / D converter as an example.
This will be described with reference to the circuit diagram of FIG. Where VCC = 5V, R =
100Ω, 2R / 2 = 50Ω, error r of resistance value of R / 2
= 1Ω, the error of 1 / 2LSB is 1 / 2LS at the maximum.
B + 1/100 LSB, but when R = 25Ω and R / 2 = 12.5Ω at the time of 4-bit A / D conversion and the mask layout area is the same as at the time of the 2-bit A / D converter, the error of １ ／ LSB is 最大 LSB + 1/2 at the maximum. 25LS
B, which is a quantization error of 1 compared to the 2-bit A / D conversion.
There is a problem that the error of / 2 LSB is increased.

[0012]

SUMMARY OF THE INVENTION The present invention provides an n-bit A
/ D converter, between a power line and a ground line
A plurality of resistance elements connected in series and a first predetermined voltage
Receiving the first terminal and one electrode connected to the first terminal.
A first capacitive element, and a first capacitive element for receiving an analog input voltage.
Input terminal and the voltage at the connection node between multiple resistance elements.
Receiving a second input terminal, a first input terminal and a second input terminal.
A second terminal commonly connected to the input terminal, and a second terminal
A second capacitance element having one electrode connected to the first capacitance and a first capacitance
Other electrode of the capacitive element and the other electrode of the second capacitive element
And a second terminal connected in common to the third terminal
Receiving a fourth terminal and a second terminal based on the voltage of the second terminal.
And a comparator for comparing the voltage of the first terminal with the voltage of the first terminal.
Predetermined voltage × (capacitance value of first capacitance element / second capacitance)
(The capacitance value of the element)
Pressure / ²ⁿ ) .times.1 / 2.

Further , according to the present invention, the first terminal is connected to the first terminal.
A third input terminal for receiving a third predetermined voltage, a first terminal;
A fourth input terminal connected to the terminal and receiving a fourth predetermined voltage
And the first predetermined voltage is (third predetermined voltage).
Voltage−fourth predetermined voltage), and the analog input voltage is A
During the sampling period for input to the / D converter, the first terminal
To the third input terminal and to the second terminal
Period during which A / D conversion is performed by selectively connecting input terminals 1
Selectively connects the fourth input terminal to the first terminal and
A second input terminal is selectively connected to the second terminal.

According to a preferred embodiment of the present invention, a sump is provided.
During the ring period, the power supply is connected to the third terminal and the fourth terminal.
IN voltage is applied. In addition, multiple resistance elements
Have the same resistance value.

The present invention further comprises receiving a fifth predetermined voltage.
A fifth input terminal, and one electrode connected to the fifth input terminal.
A third capacitor connected and the other electrode connected to the fourth terminal
And a quantity element. At this time, preferably, the third capacitor element
The capacitance value of the capacitor is the capacitance value of the first capacitance element and the capacitance value of the second capacitance element.
And the third predetermined voltage and the fifth point.
The constant voltage is (voltage between power supply line and ground line /
2).

[0016]

FIG. 1 shows an embodiment of an nbit A / D converter according to the present invention. The output of a transfer gate 1 having an input terminal A as an input and the output of a transfer gate 2 having an input terminal B as an input are shown in FIG. Connect to terminal H. The terminal H is connected to the capacitor CAP1, and the oppositely connected terminal of the capacitor CAP1 to which the terminal H is connected is connected to the input terminal F of the comparator.

The output of the transfer gate 3 receiving the input terminal C and the output of the transfer gate 4 receiving the input terminal D are connected to the terminal I. The terminal I is connected to the capacitor CAP2, and the oppositely connected terminal of the capacitor CAP2 to which the terminal I is connected is connected to the input terminal F of the comparator.

Two resistors R 'are serially connected between VCC and GND, and the output of the transfer gate 5 having a connection point between the two resistors R' as an input is connected to a terminal J. The terminal J is connected to the capacitor CAP3, and the terminal of the capacitor CAP3 to which the terminal J is connected is connected in reverse to the terminal G of the comparator.

Transfer gate 6 connected to VCC
And the output of the transfer gate 6 is connected to the input terminal G of the comparator. The transfer gate 7 connected to VCC and the output of the transfer gate 7 are connected to the input terminal F of the comparator. Further, 2 ⁿ resistors having a resistance value R are connected in series, and VCC and GND are connected to both ends of the resistors connected in series. Also, the voltage at the connection point of each resistor is {(VCC / 2 ⁿ ) × 1} (where 1 = 1 is the connection point near GND = 1, 2,..., 2 ⁿ⁻¹ ), and these voltages are It is applied to input terminal D via a selector controlled by the output of the comparator. Also, VA
Is applied to the input terminal C.

Next, the configuration of a successive approximation type A / D converter having a resolution of 2 bits, which is an example of the A / D converter of FIG. 1, is shown in FIG.
Shown in Apply VA to the terminal C of the comparator section,
The voltage at the contact point of the resistor connected in series between C and GND is
A1 = VCC / 4, A2 = (VCC / 4) × 2, A3 =
(VCC / 4) × 3, and the selector applies one of the voltages A1, A2, and A3 to the terminal D of the comparator according to the output of the comparator.

Next, the operation of the successive approximation type A / D converter having the resolution of 2 bits shown in FIG. 2 will be described with reference to the operation timing shown in FIG.

(1) During sampling period (period t1)
Turns on the transfer gates 1, 3, 5, 6, and 7, and turns off the transfer gates 2 and 4. The analog input voltage VA is applied from the input terminal C, the potential of the terminal I becomes VA, and the voltage VC from the input terminal E is applied.
When C / 2 is applied, the potential of the terminal J becomes VCC / 2, and the input terminals F and G of the comparator are precharged to VCC. When the voltage V1 is applied from the input terminal A, the terminal H becomes V1. Here, VCC = 5V, VA
= 1V, V1 = 2.5V and the capacity CAP1 capacity is 1F
Assuming that the capacitance of CAP2 is 2F and the capacitance value of CAP3 is 3F, the charge of the capacitance CAP1 is 2.5C,
The charge of the capacitor CAP2 is 8C, and the charge of the capacitor CAP3 is 7.5C.

(2) A period (t) for obtaining a digital value for an analog signal input during the sampling period (t1)
During the period of t2, the transfer gates 1, 3, 6, and 7 are turned off and the transfer gates 2, 4, and 5 are turned on. The selector selects the contact A2, a voltage of 2.5 V is applied to the input terminal D, and the voltage of the terminal I becomes 2.5 V. Further, by applying a voltage (V1-ΔV) to the input terminal B, the terminal H becomes (V1-ΔV).
ΔV). Here, ΔV = 1.25 V (where,
1.25 V is a voltage corresponding to 1 LSB in 2-bit A / D conversion when VCC = 5 V).
The electric charge held by AP2 and the potential of terminal H are (2.5 V
−1.25 V), since the potential of the terminal I is 2.5 V and the potential of the terminal J is 2.5 V, assuming that the parasitic capacitance of the input terminal F of the comparator during the period t2 is 0F, the potential of the input terminal F of the comparator is obtained. Becomes 5.875V. Further, since the input terminal G holds 5 V, the output OUT of the comparator outputs a logical “L”. (The digital value for an analog signal is determined to be logically “0” for the most significant bit.)

Here, the potential of the input terminal F is [input terminal F
Potential] = ([potential of terminal I in period t2] − [potential of terminal I in period t1]) + ｛([potential of terminal H in period t2]
− [Potential of the terminal H during the period t1] × [capacitance value of the CAP1] / [capacitance value of the CAP2]｝ + [potential of the terminal F during the period t1] = (2.5V-1V) + (1.25V− 2.5
V) × １ ／ + 5V = 5.875V.

The expression for the potential of the input terminal F is "([potential of the terminal H during the period t2]-[potential of the terminal H during the period t1]). Times.
[Capacity value of CAP1] / [Capacity value of CAP2] = ｛(V
1−ΔV) −V1｝ × 1F / 2F ″ is the value of Ｌ LSB of the 2-bit A / D converter. That is, instead of using a resistor to create Ｌ LSB as in the conventional case, the present invention provides ΔV And the ratio of the capacitance values of CAP1 and CAP2 is 1 /
2LSB is being created. Further, since CAP1 and CAP2 can be created in the vicinity on the mask, CAP1 / CAP2
The ratio of CAP2 can be kept unchanged.

Next, during the period t3, the transfer gates 1, 3, 6, and 7 are in the OFF state and the transfer gates 2, 4, and 5 are in the ON state. L ”, the selector selects the terminal A1, a voltage of 1.25V is applied to the input terminal D, the terminal I becomes 1.25V, and the CAP during the period t2
1, the charge held by CAP2 and the potential of terminal H are (2.5 V-1.25 V), and the potential of terminal I is 1.25
Assuming that the parasitic capacitance of the input terminal F of the comparator during the period t3 is 0F from the relation of V and the potential of the terminal J being 2.5 V, the potential of the input terminal F of the comparator becomes ([the potential of the terminal I during the period t3]-[ Potential of terminal I during t2]) + [t2
Potential of terminal F during period] = (1.25 V−2.5 V) +
5.875V = 4.625V. Also, the input terminal G
Is the output O of the comparator because 5 V is held.
The UT outputs a logical “H”. (The digital value for an analog signal is determined to be logically “1” for the least significant bit.)

[0027]

As described above, according to the present invention, one of the quantization errors
/ 2 LSB (VCC / 2 ^{n + 1} ) with the capacitors CAP1, CA
The capacitance is created using the product of the ratio of the capacitance value of P2 and the potential difference ΔV. Since the capacitances CAP1 and CAP2 are formed close to each other on the mask layout, the ratio of these two capacitances can be kept constant. It is possible to guarantee that the conversion error is minimized.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of an A / D converter according to an embodiment of the present invention.

FIG. 2 is a diagram showing the A / A of the 2-bit successive approximation conversion method using FIG.
Configuration diagram of D converter

FIG. 3 is an operation timing chart of the configuration diagram shown in FIG. 2;

FIG. 4 is a configuration diagram of a conventional A / D converter.

FIG. 5 is a diagram showing A / A of a 2-bit successive approximation conversion method using FIG.
Configuration diagram of D converter

FIG. 6 is an operation timing chart of the configuration diagram shown in FIG. 5;

[Description of Signs] 1-7 Transfer gates A-E Input terminals F-J terminals CAP1-5 Capacitance R, R 'Resistance A1-3 Power supply voltage division point VCC Power supply GND Ground

Claims (7)

(57) [Claims] 1. An n-bit A / D converter, comprising: a power supply
Multiple resistors connected in series between the line and the ground line
An element, a first terminal receiving a first predetermined voltage,
A first capacitor having one electrode connected to the first terminal;
And a first input terminal for receiving an analog input voltage;
A second input for receiving a voltage at a connection node between the plurality of resistance elements;
Force terminal, the first input terminal and the second input terminal
A second terminal commonly connected to the second terminal and the second terminal
A second capacitive element to which one of the electrodes is connected;
The other electrode of the capacitor and the other of the second capacitor
A third terminal commonly connected to the electrodes of
A fourth terminal for receiving a voltage, and a voltage based on the voltage of the second terminal.
A comparator for comparing the voltage of the first terminal with the voltage of the first terminal
And the first predetermined voltage × (the capacitance value of the first capacitive element)
/ The capacitance value of the second capacitive element is
Voltage between the ground line / ^2/2 ) × 1/2
A / D converter, characterized in that. (2) A third predetermined terminal connected to the first terminal;
A third input terminal for receiving a voltage, connected to the first terminal;
And a fourth input terminal receiving a fourth predetermined voltage.
And the first predetermined voltage is (the third predetermined voltage).
Pressure-the fourth predetermined voltage) and the analog input
Before the sampling period when the voltage is input to the A / D converter,
The third input terminal is selectively connected to the first terminal.
Selectively connect the first input terminal to the second terminal
During the period for performing A / D conversion, the first terminal is connected to the first terminal.
4 input terminals and selectively connected to the second terminal.
The second input terminal is selectively connected.
The A / D converter according to claim 1. (3) In the sampling period, the third
The voltage of the power line is marked on the terminal and the fourth terminal.
3. The method according to claim 1, wherein the A /
D converter. (4) Each of the plurality of resistance elements has an equal resistance.
3. The method according to claim 1, wherein the first, second, and third components have a resistance value.
3. The A / D converter according to 3. (5) A fifth input terminal for receiving a fifth predetermined voltage
Child and the fifth input One electrode is connected to the terminal
A third capacitor in which the other electrode is connected to the fourth terminal;
4. The method according to claim 1, further comprising:
Is an A / D converter according to 4. 6. The capacitance value of the third capacitance element is
The capacitance value of the first capacitance element and the capacitance value of the second capacitance element
6. The A / D conversion according to claim 5, wherein
vessel. 7. The third predetermined voltage and the fifth predetermined voltage
Is the voltage between the power supply line and the ground line.
Voltage / (2).
D converter.