JP2916334B2 - Semiconductor storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device having a field memory such as a FIFO (first-in first-out) memory mounted on an HD (high definition) TV / MUSE system or the like, and more particularly to a final line. And a semiconductor memory device having the function of adjusting the number of pixels.

[0002]

2. Description of the Related Art Conventionally, as a general field memory provided in this type of semiconductor memory device, serial registers 102 and 103 having a size equal to the number of column cells of a memory block 101 are provided as shown in FIG. In some cases, input / output data is controlled.

[0003] The field memory shown in FIG.
Pixel (pixel) of the last line used in the USE system etc.
The number adjustment function can be realized very easily.

For example, only for the last line, the address pointer value is moved and the serial registers 102, 1
By changing the size of 03, the function of adjusting the number of pixels of the last line can be realized.

However, the basic configuration of the field memory requires a register length corresponding to the number of column addresses of the memory block 101, which increases the chip size and is disadvantageous in cost.

Accordingly, a field memory having a serial register length of 16 bits has been proposed. in this case,
The area for the serial register can be reduced, which is advantageous in cost.

However, since the register length is smaller than the number of column addresses of the memory block, there is a problem that the function of adjusting the number of pixels on the last line cannot be realized as easily as the above-mentioned field memory.

[0008]

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a semiconductor memory device which can easily realize the function of adjusting the number of pixels of the last line for horizontal motion compensation without increasing the chip size. Is to provide.

[0009]

In order to achieve the above object, a semiconductor memory device of the present invention selects a pixel number of a last line of image data and outputs a final line pixel number selection signal. A 16-bit read register for accumulating and outputting 16-bit output data of image data output from the main amplifier;
Based on the final line pixel number selection signal received from the pixel number selection unit, the output data from the 16-bit read register is stored based on the final line 32-bit register that stores and outputs input data after the eighth bit. Multiplex the output data from the 32-bit register for the last line to the image data from the first data of the first line to the 928th bit in the last line.
A multiplexer that receives and outputs from the 6-bit read register the input data after the 928th bit in the final line from the 32-bit register for the final line and outputs the data, and a write address for creating a write column address of the image data A counter, a read address counter for generating a read column address of the image data, and a RAS signal generating unit for outputting a row address strobe signal for latching addresses output by the write address counter and the read address counter. It is characterized by.

[0010]

According to the above construction, the multiplexer outputs the output data from the 16-bit read register and the output data from the 32-bit register for the last line based on the last line pixel number selection signal received from the pixel number selection section. Multiplexed with the output data of the first line, and after receiving and outputting the image data from the first data of the first line to the 928th bit in the last line from the 16-bit read register, input data after the 928th bit in the last line From the last line 32-bit register.

That is, according to the present invention, the image data up to the 928th bit of the normal line and the last line is
Since data is read from the bit read register, the chip size can be reduced as compared with the conventional example that requires a register length corresponding to the number of column addresses of the memory block.

Further, since the image data after the 928th bit of the last line is read out from the 32-bit register for the last line, compared with the conventional example in which the image data is read out only from the 16-bit register, it is necessary to perform horizontal motion correction and the like. The function of adjusting the number of pixels of the last line can be easily realized.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail with reference to the illustrated embodiments.

FIG. 1 shows the basic configuration of the field memory of the semiconductor memory device of this embodiment. This field memory has 16 bit registers 1 and 6 as shown in FIG.
It has.

FIG. 2 shows the basic system timing of the field memory. As shown in FIG. 2, the field memory generates a / RAS signal based on a system clock RCK or WCK as an input / output clock.

The field memory operates within the period of 16 clocks (for example, RCK) by the / RAS signal.
(Between 0 and RCK15), one read operation and one write operation are processed in series. The read operation is to output 16-bit data from the memory block 3 to the output data amplifier 5, and the write operation is to write 16-bit data from the input data amplifier 2 to the memory block 3.

As described above, the 8-bit data is accessed twice consecutively with the memory block 3 during one read operation. Therefore, as shown in FIG. Increments are incremented two and three times.

Similarly, since 8-bit data is written twice in the memory block 3 during one write operation, the column address of the memory block 3 becomes 11 in one write operation.
It is incremented twice to 8,119.

FIG. 3A shows the relationship between the column address of the memory block 3 and the column address in the column address counter (not shown) in the normal line.

This embodiment has a component shown in the block diagram of FIG. 5, and the component realizes the function of selecting the number of pixels of the last line. That is, in the last line, the number of pixels is not fixed to 960 bits, but is variable from 929 bits to 960 bits. FIG. 3B shows the timing of this last line.

The pixel number selection section 51 shown in FIG. 5 enables the number of pixels of the last line to be selected from 929 bits to 960 bits based on the pixel select data PS0 to PS4.

In FIG. 5, a 16-bit read register 52 takes in 16-bit data from a main amplifier regardless of a normal line / final line and outputs data based on a read clock signal RCK.

The last line 32-bit register 5
No. 3 captures input data after the 928th bit of the last line based on the write clock signal WCK. At this time, the required number of input data changes according to the pixel number selection signal created by the pixel number selection unit 51. For example, if the pixel number of the last line is selected as (928 bits + N bits), the 928th bit is selected. N bits become valid data later.

The write clock signal WCK is input to the last line 32-bit register 53 as 32 clock pulse signals, and the data after the 928th bit is shifted to the right end of the 32-bit register 53. .

At the same time, based on the read clock signal RCK, the 32-bit register 53 for the last line
Data after the 928th bit of the last line is output. For example, assuming now that the number of pixels of the last line is (928 bits + N bits), the effective data N bits of the last line that the 32-bit register 53 has fetched one field before based on the write clock signal WCK is:
The data is output as output data through a multiplexer (MUX) 55.

The multiplexer (MUX) 55 selects N bits of output data after the 928th bit of the last line, assuming that the pixel number selection signal of the last line has selected N bits. The multiplexer 55
Is the timing of the next clock pulse signal,
The output data of the bit read register 52 is selected and the first
Select data from the 0 bit of the line.

The RAS signal creating section 56 creates the / RAS signal as shown in FIG. 3A when accessing a normal line, while as shown in FIG. 3B when accessing the last line. , RAS signal to be precharged from the 928th bit to the last bit.

The write column address counter 57
The read column address counter 58 also counts only the last line as shown in FIG. 3B, so that a stop period of the counter increment signal and a counter reset signal need to be added.

The pixel number selecting section 51 includes a pixel select signal decoding section shown in FIG. This pixel select signal decoding unit decodes input signals PS0 to PS4 as pixel select data based on the relationship between pixel select data PS0 to PS4 and the number of pixels of the last line shown in FIG.
S1 to PSS32 are created.

Further, the pixel number selecting section 51 includes a final line pixel number extracting section shown in FIGS. (1) to (3) in FIG. 7 are connected to (1) to (3) in FIG. The final line pixel number extraction unit is configured to output the pixel number selection signal PS output from the pixel selection signal decoding unit.
Based on S1 to PSS32, a timing signal PSSL for switching from the last line pixel data to the first data of the first line is created.

For example, the pixel number 931 (P
S0 = L, PS1 = H, PS2 = L, PS3 = L, PS4 =
When L) is selected, the pixel number selection unit 51 shown in FIG.
The number-of-pixels selection signal PSS3 output from the pixel selection signal decoding unit shown in FIG. Next, since the pixel number selection signal PSS3 is at the H level, the PSS signal becomes H level at the timing when the signal RC930 'of the last line pixel number extraction unit shown in FIG. (See FIG. 12). Then, the last line pixel number extracting unit outputs the timing signals PSSL, PSFF, P at a timing one stage behind the read clock signal RCK.
An SF is created (see FIG. 12). And the signal PSF
F resets the 32-stage D flip-flop of the final line pixel number extraction unit.

As shown in FIG. 9, the last line 92 read from the memory cell and amplified by the main amplifier is used.
Normal line data other than the data after 8 bits
The 16-bit read register 52 is loaded at the timing of the signal RP0 '.

Thereafter, the 16-bit read register further outputs the data of the normal line as a signal PSD through the multiplexer MUX shown in FIG.

The 16-bit read register has
The last line (after the 928th bit) is not loaded, and the leading 16-bit data of the leading line, which is the output data of the main amplifier, is loaded at the timing of the timing signal PSF. Then, the multiplexer (M
UX), the head 16-bit data is converted to a signal PS.
Output as D. That is, the timing signal PS
At the timing of F, the signal FLR of the multiplexer (MUX) becomes L level, and the multiplexer (MUX) selects data from the 16-bit read register 52.

On the other hand, the 32-bit register for the last line shown in FIG. 9 stores the data of the 929th bit and subsequent bits of the last line. Then, the signal RCCF is input to each D flip-flop as 32 clock signals so that the 929th bit data becomes the output Q32 of the 32nd D flip-flop. The control of the clock signal RCCF is performed by the signal FLCSET. That is,
FLCSET only during the 32 clock signals
When the signal goes high, 32 clock signals RCK
Becomes the RCCF signal (see FIG. 12). And this 32
During the period of the clock signals, the last line 3 shown in FIG.
The 2-bit register contains 9 of the last line of this field.
Data after the 29th bit is input. At the same time as this data input, the data from the last 929th bit stored in the field before this field is
The signal passes through the multiplexer (MUX) 55.

The read column address counter 58
Reads 16-bit data from a memory cell for one read operation. Then, since the data processing after the data read is performed in units of 8 bits, two addresses are counted for one read operation. In addition, the write column address counter unit performs two write operations per write operation.
Count one write column address. 3 and 4 show a read clock signal RCK, a write clock signal WCK, a / RAS signal, a read column address,
This shows the relationship between the write column addresses.

As shown in FIG. 3B, the last line 929
Since the / RAS signal is precharged after the bit, both the read column address and the write column address have special addresses. FIG. 3B shows the read clock signal RCK and the write clock signal W at this time.
The relationship between the CK and / RAS signals is shown.

As shown in FIG. 4, the read address counter 58 shown in FIG. 10 is incremented at the timing of the pulse signals RT1 and RT6 input to the read address counter 58 during the read operation. Also, the signal RC
By resetting the read address counter 58 at the 946th timing of the read clock signal 945, the read column addresses RCA0 to RCA6 are reset.
Is obtained.

Also, during the read operation of the last line, the read address counter 58 is reset at the 917th read clock timing of the signal RC916 shown in FIG. 10 in order to make the address shown in FIG. 3B. After the timing of the signal RC928, the / FLR signal goes to L level, so that the counter clock signals RT1 and RT6 are not input to the read address counter 58. Therefore, at this time, the read address counter 58 is not incremented.

On the other hand, the write column address of the write address counter 57 shown in FIG.
Incremented at D clock timing. Since the write address counter 57 is reset at the timing of the signal WC25, the normal line has an address as shown in FIG. On the other hand, in the last line, the write address counter 57
Are the addresses shown in FIG. 3 (B) because the clock pulse signals of WT1 and WT4D are not input by the / FLR signal.

When the FLRSET signal goes high, the FLR signal goes high and the multiplexer M
The UX outputs a signal from the 32-bit register for the last line as a PSD signal.

As in the above example, the number of pixels in the last line is 93.
When the bit is set to 1, the 929th, 930th, and 931th bits of the last line are output from the 32 bit register 53 for the last line shown in FIG. Becomes Then, at the timing of the 932th bit, the PSF signal goes high and the FLR signal goes low. Then, data from the first bit of the first line stored in the 16-bit read register 52 shown in FIG. 9 is output as a PSD signal via the multiplexer (MUX). FIG. 12 shows the timing of the above operation.

In the case of a normal RAS signal as shown in FIG. 4, the RAS signal generator 56 shown in FIG. 10 outputs a / RAS signal based on a signal RT0 generated during a read operation and a signal WT0 generated during a write operation. It becomes H level. Then, the / RAS signal becomes L by the signal RT3 and the signal WT3.
Become level active. However, after the 928th bit of the last line, the / RAS signal is in a precharge state as shown in FIG. 3B, and data is not read from the memory cell (16 bits shown in FIG. 9). (The data of the read register 52 is not selected), and the data of the 32-bit register 53 for the last line shown in FIG. 9 is read.

The RAS signal generating section 56 generates the signal / FLR generated by the multiplexer (MUX) 55 shown in FIG.
, So that the signals RT3 and WT3 are not received only during the period after the 928th bit of the last line. Therefore, the RAS signal generator 56 determines that the period after the 928th bit of the last line is / R
The AS signal is set to the H level.

As described above, according to the above embodiment, the image data up to the 928th bit of the normal line and the last line is read from the 16-bit read register 52.
The chip size can be reduced as compared with a conventional example requiring a register length corresponding to the number of column addresses of a memory block.

Further, according to the above embodiment, since the image data after the 928th bit of the last line is read from the 32-bit register 53 for the last line, the image data is read as compared with the conventional example which reads the image data only from the 16-bit register. In addition, the function of adjusting the number of pixels of the last line for horizontal motion correction or the like can be easily realized.

[0047]

As is apparent from the above description, the semiconductor memory device of the present invention has a pixel number selection unit, a 16-bit read register, a 32-bit register for the last line, and a last line received from the pixel number selection unit. Based on the pixel number selection signal, the output data from the 16-bit read register and the output data from the 32-bit register for the last line are multiplexed, and from the first data of the first line to the 928th bit in the last line. After receiving and outputting the image data from the 16-bit read register, and receiving and outputting the input data after the 928th bit in the last line from the 32-bit register for the last line.

Therefore, according to the present invention, since the image data up to the 928th bit of the normal line and the last line is read from the 16-bit read register, the conventional example requiring a register length corresponding to the number of column addresses of the memory block is required. The chip size can be reduced as compared with.

Further, since the image data after the 928th bit of the last line is read out from the 32-bit register for the last line, compared with the conventional example in which the image data is read out only from the 16-bit register, it is necessary to perform the horizontal motion correction and the like. The function of adjusting the number of pixels of the last line can be easily realized.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a basic configuration of a field memory according to an embodiment of a semiconductor memory device of the present invention.

FIG. 2 is a diagram showing basic system timing of the field memory.

FIG. 3 is a diagram showing a relationship between a column address of a memory block and a column address in a column address counter in a normal line and a last line of the embodiment.

FIG. 4 is a diagram showing timings of a clock signal, a / RAS signal, and the like in the embodiment.

FIG. 5 is a block diagram of a portion for selecting the number of pixels of the last line in the embodiment.

FIG. 6 is a diagram showing a pixel select signal decoding unit of the embodiment.

FIG. 7 is a diagram showing a final line pixel number extraction unit of the embodiment.

FIG. 8 is a diagram showing a final line pixel number extraction unit of the embodiment.

FIG. 9 is a diagram showing a 16-bit register, a 32-bit register, and a multiplexer according to the embodiment.

FIG. 10 is a diagram showing a RAS signal generator and an address counter of the embodiment.

FIG. 11 is a diagram showing a relationship between pixel select data and the number of pixels of the last line in the embodiment.

FIG. 12 is a diagram showing the timing of a signal for determining the number of pixels on the last line in the embodiment.

FIG. 13 is a block diagram of a conventional semiconductor memory device.

[Explanation of symbols]

1: 16-bit write register, 2: input data amplifier, 3: memory block, 5: output data amplifier, 6:
16-bit read register, 51 ... pixel number selection unit,
52: 16-bit read register, 53: 32-bit register for last line, 55: multiplexer, 56: R
AS signal generation unit, 57: write address counter, 58
... Read address counter.

Claims (1)

(57) [Claims] 1. A pixel number selection unit for selecting the number of pixels of the last line of image data and outputting a last line pixel number selection signal, and accumulating 16-bit output data of image data output by a main amplifier. A 16-bit read register for output, a 32-bit register for the last line for storing and outputting input data after the 928th bit in the last line, and a last line pixel number selection signal received from the pixel number selection unit. The output data from the 16-bit read register and the output data from the 32-bit register for the last line are multiplexed, and the image data from the first data of the first line to the 928th bit in the last line is converted to the 16-bit image data. After receiving and outputting from the read register, from the 928th bit in the last line A multiplexer that receives and outputs the subsequent input data from the 32-bit register for the last line, a write address counter that creates a write column address of the image data, a read address counter that creates a read column address of the image data, And a RAS signal generator for outputting a row address strobe signal for latching an address output from the write address counter and the read address counter.